Hiroshi Miyashita

17 papers C 1Journal 5Unranked 11
YearRankTypeTitle / Venue / Authors
2023 — conf
Designing Researchmap: A Revolutionary Scholar Support Platform Achieved Through Human-AI Collaboration.
ICKII
Noriko H. Arai, Ryuji Masukawa, Hiroshi Miyashita
2021 J jnl
Human-centric data protection laws and policies: A lesson from Japan.
Comput. Law Secur. Rev.
Hiroshi Miyashita
2021 — conf
MN-Core - A Highly Efficient and Scalable Approach to Deep Learning.
VLSI Circuits
Ken Namura, Johannes Maximilian Kühn, Tohru Adachi, H. Imachi, H. Kaneko, T. Kato, Go Watanabe, Naoto Tanaka, S. Kashihara, Hiroshi Miyashita, Y. Tomonaga, Ryosuke Okuta, Takuya Akiba, Brian Vogel, S. Kitajo, F. Osawa, K. Takahashi, Y. Takatsukasa, K. Mizumaru, Takuya Yamauchi, J. Ono, A. Takahashi, Tanvir Ahmed, Y. Doi, K. Hiraki, Jun Makino
2017 — conf
Automated Historical Fact-Checking by Passage Retrieval, Word Statistics, and Virtual Question-Answering.
IJCNLP(1)
Mio Kobayashi, Ai Ishii, Chikara Hoshino, Hiroshi Miyashita, Takuya Matsuzaki
2016 — conf
NUL System at QA Lab-2 Task.
NTCIR
Mio Kobayashi, Hiroshi Miyashita, Ai Ishii, Chikara Hoshino
2014 — conf
NUL System at NTCIR RITE-VAL Tasks.
NTCIR
Ai Ishii, Hiroshi Miyashita, Mio Kobayashi, Chikara Hoshino
2014 — conf
NUL System at QALab Tasks.
NTCIR
Hiroshi Miyashita, Ai Ishii, Mio Kobayashi, Chikara Hoshino
2013 — conf
Basis of monitoring central blood pressure and hemodynamic parameters by peripheral arterial pulse waveform analyses.
EMBC
Hiroshi Miyashita, Shin-ichiro Katsuda
2007 C conf
Efficient Thermal Via Planning for Placement of 3D Integrated Circuits.
ISCAS
Jing Li, Hiroshi Miyashita
2006 — conf
Post-placement Thermal Via Planning for 3D Integrated Circuit.
APCCAS
Jing Li, Hiroshi Miyashita
2006 J jnl
Thermal-Aware Placement Based on FM Partition Scheme and Force-Directed Heuristic.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Jing Li, Hiroshi Miyashita
2005 J jnl
An Incremental Placement Algorithm for Building Block Layout Design Based on the O-Tree Representation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Jing Li, Juebang Yu, Hiroshi Miyashita
2005 J jnl
Equidistance routing in high-speed VLSI layout design.
Integr.
Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi
2004 — conf
Equidistance routing in high-speed VLSI layout design.
ACM Great Lakes Symposium on VLSI
Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi
2002 — conf
On the equivalence of the sequence pair for rectangle packing to the dimension of partial orders [floorplanning].
APCCAS (2)
Hiroshi Miyashita, Yoji Kajitani
1995 — conf
Extending pitchmaking algorithms to layouts with multiple grid constraints.
ASP-DAC
Hiroshi Miyashita
1986 J jnl
An automatic cell pattern generation system for CMOS transistor-pair array LSI.
Integr.
Hiroshi Miyashita, Tohru Adachi, Kazuhiro Ueda