Hiroshi Makino

48 papers A 3B 1C 4Journal 31Unranked 9

Year	Rank	Type	Title / Venue / Authors
2016	J	`jnl`	A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yoshifumi Kawamura, Naoya Okada, Yoshio Matsuda, Tetsuya Matsumura, Hiroshi Makino, Kazutami Arimoto
2016	—	`conf`	A study on fast motion estimation algorithm. GCCE Masahiro Hiramori, Ryota Bandou, Shuhei Iwade, Hiroshi Makino, Tsutomu Yoshimura, Yoshio Matsuda
2016	—	`conf`	A study on motion estimation algorithm for moving pictures. GCCE Ryota Bnadou, Masahiro Hiramori, Shuhei Iwade, Hiroshi Makino, Tutomu Yoshimura, Yoshio Matsuda
2015	J	`jnl`	The Challenge of Collaboration among Academies and Asia Pacific for ITS R&D. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroshi Makino, Shunsuke Kamijo
2014	—	`conf`	A new stepwise adiabatic charging circuit with a smaller capacitance in a regenerator than a load capacitance. MWSCAS Shunji Nakata, Hiroshi Makino, Yoshio Matsuda
2014	J	`jnl`	Analysis of voltage, Current and Energy dissipation of Stepwise Adiabatic Charging of a capacitor using a nonresonant inductor Current. J. Circuits Syst. Comput. Shunji Nakata, Hiroshi Makino, Ryota Honda, Masayuki Miyama, Yoshio Matsuda
2014	J	`jnl`	Development of the SCARA. J. Robotics Mechatronics Hiroshi Makino
2014	J	`jnl`	Energy Efficient Stepwise Charging of a Capacitor Using a DC-DC Converter With Consecutive Changes of its Duty Ratio. IEEE Trans. Circuits Syst. I Regul. Pap. Shunji Nakata, Hiroshi Makino, Junpei Hosokawa, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda
2014	J	`jnl`	Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage. IEEE Trans. Very Large Scale Integr. Syst. Shunji Nakata, Hiroki Hanazono, Hiroshi Makino, Hiroki Morimura, Masayuki Miyama, Yoshio Matsuda
2014	C	`conf`	The LSI implementation of a memory based field programmable device for MCU peripherals. DDECS Tetsuya Matsumura, Naoya Okada, Yoshifumi Kawamura, Koji Nii, Kazutami Arimoto, Hiroshi Makino, Yoshio Matsuda
2013	J	`jnl`	Analysis of Pull-in Range Limit by Charge Pump Mismatch in a Linear Phase-Locked Loop. IEEE Trans. Circuits Syst. I Regul. Pap. Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino, Yoshio Matsuda
2012	—	`conf`	Energy dissipation reduction during adiabatic charging and discharging with controlled inductor current. MWSCAS Shunji Nakata, Ryota Honda, Hiroshi Makino, Hiroki Morimura, Yoshio Matsuda
2012	J	`jnl`	General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology. IEEE Trans. Circuits Syst. I Regul. Pap. Shunji Nakata, Ryota Honda, Hiroshi Makino, Shin'ichiro Mutoh, Masayuki Miyama, Yoshio Matsuda
2012	J	`jnl`	Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield. IET Circuits Devices Syst. Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda
2011	J	`jnl`	Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution. IEEE Trans. Circuits Syst. II Express Briefs Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda
2010	C	`conf`	Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit. ISCAS Shunji Nakata, Hirotsugu Suzuki, Ryota Honda, Takahito Kusumoto, Shin'ichiro Mutoh, Hiroshi Makino, Masayuki Miyama, Yoshio Matsuda
2010	J	`jnl`	Stable adiabatic circuit using advanced series capacitors and time variation of energy dissipation. IEICE Electron. Express Shunji Nakata, Shin'ichiro Mutoh, Hiroshi Makino, Masayuki Miyama, Yoshio Matsuda
2009	J	`jnl`	Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access. IEEE J. Solid State Circuits Koji Nii, Yasumasa Tsukamoto, Makoto Yabuuchi, Yasuhiro Masuda, Susumu Imaoka, Keiichi Usui, Shigeki Ohbayashi, Hiroshi Makino, Hirofumi Shinohara
2008	J	`jnl`	A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues. IEEE J. Solid State Circuits Satoshi Ishikura, Marefusa Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi, Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara, Hironori Akamatsu
2008	J	`jnl`	A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations. IEEE J. Solid State Circuits Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara
2008	J	`jnl`	A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die. IEEE J. Solid State Circuits Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Tsutomu Yoshihara, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
2008	J	`jnl`	A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology. IEICE Trans. Electron. Masako Fujii, Koji Nii, Hiroshi Makino, Shigeki Ohbayashi, Motoshige Igarashi, Takeshi Kawamura, Miho Yokota, Nobuhiro Tsuda, Tomoaki Yoshizawa, Toshikazu Tsutsui, Naohiko Takeshita, Naofumi Murata, Tomohiro Tanaka, Takanari Fujiwara, Kyoko Asahina, Masakazu Okada, Kazuo Tomita, Masahiko Takeuchi, Shigehisa Yamamoto, Hiromitsu Sugimoto, Hirofumi Shinohara
2008	—	`conf`	On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect. ESSCIRC Masako Fujii, Hiroaki Suzuki, Hiromi Notani, Hiroshi Makino, Hirofumi Shinohara
2008	A	`conf`	Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology. ISLPED Hiroaki Suzuki, Masanori Kurimoto, Tadao Yamanaka, Hidehiro Takata, Hiroshi Makino, Hirofumi Shinohara
2007	—	`conf`	A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations. ISSCC Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara
2007	J	`jnl`	A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits. IEEE J. Solid State Circuits Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
2007	—	`conf`	A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die. ISSCC Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
2007	—	`conf`	Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCs. ISSCC Mitsuya Fukazawa, Tetsuro Matsuno, Toshifumi Uemura, Rei Akiyama, Tetsuya Kagemoto, Hiroshi Makino, Hidehiro Takata, Makoto Nagata
2007	J	`jnl`	Research and Commercialization of SCARA Robot -The Case of Industry-University Joint Research and Development-. Int. J. Autom. Technol. Hiroshi Makino, Akitaka Kato, Yasunori Yamazaki
2005	—	`conf`	A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure. ISCAS (1) Niichi Itoh, Yasumasa Tsukamoto, Takeshi Shibagaki, Koji Nii, Hidehiro Takata, Hiroshi Makino
2005	A	`conf`	Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. ICCAD Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
2004	J	`jnl`	A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications. IEEE J. Solid State Circuits Koji Nii, Yasumasa Tsukamoto, Tomoaki Yoshizawa, Susumu Imaoka, Yoshinobu Yamagami, Toshikazu Suzuki, Akinori Shibayama, Hiroshi Makino, Shuhei Iwade
2001	J	`jnl`	A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree. IEEE J. Solid State Circuits Niichi Itoh, Yuka Naemura, Hiroshi Makino, Yasunobu Nakase, Tsutomu Yoshihara, Yasutaka Horiba
1998	A	`conf`	A low power SRAM using auto-backgate-controlled MT-CMOS. ISLPED Koji Nii, Hiroshi Makino, Yoshiki Tsujihashi, Chikayoshi Morishima, Yasushi Hayakawa, Hiroyuki Nunogami, Takahiko Arakawa, Hisanori Hamano
1998	J	`jnl`	Robot contest "Robocon Yamanashi". J. Robotics Mechatronics Noriaki Kiyohiro, Hiroshi Makino, Hideo Mori
1997	C	`conf`	A Floating Point Divider using Redundant Binary Circuits and an Asynchronous Clock Scheme. ICCD Hiroaki Suzuki, Hiroshi Makino, Koichiro Mashiko, Hisanori Hamano
1997	J	`jnl`	Authors Reply. IEEE J. Solid State Circuits Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko
1997	J	`jnl`	Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]. IEEE J. Solid State Circuits Vojin G. Oklobdzija, Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi
1996	J	`jnl`	A 286 MHz 64-b floating point multiplier with enhanced CG operation. IEEE J. Solid State Circuits Hiroshi Makino, Hiroaki Suzuki, Hiroyuki Morinaka, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi
1996	J	`jnl`	An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture. IEEE J. Solid State Circuits Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko
1996	J	`jnl`	Leading-zero anticipatory logic for high-speed floating point addition. IEEE J. Solid State Circuits Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi
1995	J	`jnl`	A BiCMOS wired-OR logic. IEEE J. Solid State Circuits Yasunobu Nakase, Hiroaki Suzuki, Hiroshi Makino, Hirofumi Shinohara, Koichiro Mashiko
1993	C	`conf`	A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture. ICCD Hiroshi Makino, Yasunobu Nakase, Hirofumi Shinohara
1991	J	`jnl`	A 5-ns GaAs 16-kb SRAM. IEEE J. Solid State Circuits Shuichi Matsue, Hiroshi Makino, Minoru Noda, Hirofumi Nakano, Satoshi Takano, Kazuo Nishitani, Shimpei Kayano
1990	J	`jnl`	A 7-ns/850-mW GaAs 4-kb SRAM with little dependence on temperature. IEEE J. Solid State Circuits Hiroshi Makino, Shuichi Matsue, Minoru Noda, Noriyuki Tanino, Satoshi Takano, Kazuo Nishitani, Shimpei Kayano
1989	J	`jnl`	Development of the Spherical SCARA Robot. J. Robotics Mechatronics Hiroshi Makino
1985	J	`jnl`	Beta: An Automatic Kana-Kanji Translation System. Computer Hiroshi Makino
1980	B	`conf`	An Automatic Translation System Of Non-Segmented Kana Sentences Into Kanji-Kana Sentences. COLING Hiroshi Makino, Makoto Kizawa