Hiroshi Kadota

13 papers A* 1A 1Journal 6Unranked 5
YearRankTypeTitle / Venue / Authors
2011 J jnl
Neurophysiological and Dynamical Control Principles Underlying Variable and Stereotyped Movement Patterns During Motor Skill Acquisition.
J. Adv. Comput. Intell. Intell. Informatics
Kazutoshi Kudo, Makoto Miyazaki, Hirofumi Sekiguchi, Hiroshi Kadota, Shinya Fujii, Akito Miura, Michiko Yoshie, Hiroki Nakata
2004 — conf
A new reconfigurable architecture with smart data-transfer subsystems for the intelligent image processing.
FPT
Hiroshi Kadota, Yoshiaki Hori, Akiyoshi Wakatani
2004 J jnl
Selective activation and deactivation of the human brain structures between speeded and precisely timed tapping responses to identical visual stimulus: an fMRI study.
NeuroImage
Kazutoshi Kudo, Makoto Miyazaki, Toshitaka Kimura, Kentaro Yamanaka, Hiroshi Kadota, Masaya Hirashima, Yasoichi Nakajima, Kimitaka Nakazawa, Tatsuyuki Ohtsuki
2002 — conf
Classification of Rice Grain Using New Scale Invariant Zernike Moments.
JCIS
Chong-Yaw Wee, Paramesran Raveendran, Fumiaki Takeda, Takeo Tsuzuki, Hiroshi Kadota, Satoshi Shimanouchi
2002 — conf
Classification of rice grains using fuzzy artmap neural network.
APCCAS (2)
Chong-Yaw Wee, Raveendran Paramesran, Fumiaki Takeda, Takeo Tsuzuki, Hiroshi Kadota, Satoshi Shimanouchi
2001 — conf
A New Inter-Core Built-In-Self-Test Circuits for Tri-State Buffers in the System on a Chip.
Asian Test Symposium
Tetsuji Kishi, Mitsuyasu Ohta, Takashi Taniguchi, Hiroshi Kadota
1996 J jnl
An evaluation of the subframe parallel approach for image clustering.
Syst. Comput. Jpn.
Akiyoshi Wakatani, Yoshiteru Mino, Hiroshi Kadota
1992 J jnl
An 80-MFLOPS (peak) 64-b microprocessor for parallel computer.
IEEE J. Solid State Circuits
Hiraku Nakano, Masaitsu Nakajima, Yasuhiro Nakakura, Tadahiro Yoshida, Yoshiyuki Goi, Yuji Nakai, Reiji Segawa, Takeshi Kishida, Hiroshi Kadota
1991 A* conf
OHMEGA: A VLSI Superscalar Processor Architecture for Numerical Applications.
ISCA
Masaitsu Nakajima, Hiraku Nakano, Yasuhiro Nakakura, Tadahiro Yoshida, Yoshiyuki Goi, Yuji Nakai, Reiji Segawa, Takeshi Kishida, Hiroshi Kadota
1991 A conf
Parallel computer ADENART - its architecture and application.
ICS
Hiroshi Kadota, Katsuyuki Kaneko, Ichiro Okabayashi, Tadashi Okamoto, T. Mimura, Yasuhiro Nakakura, Akiyoshi Wakatani, Masaitsu Nakajima, Junji Nishikawa, K. Zaiki, Tatsuo Nogi
1990 J jnl
Processing element design for a parallel computer.
IEEE Micro
Katsuyuki Kaneko, Masaitsu Nakajima, Yasuhiro Kakakura, Junji Nishikawa, Ichiro Okabayashi, Hiroshi Kadota
1989 J jnl
A VLSI RISC with 20-MFLOPS peak, 64-bit floating-point unit.
IEEE J. Solid State Circuits
Katsuyuki Kaneko, Tadashi Okamoto, Masaitsu Nakajima, Yasuhiro Nakakura, Satoshi Gokita, Junji Nishikawa, Yuji Tanikawa, Hiroshi Kadota
1989 — conf
VLSI Parallel Computer with Data Transfer Network: ADENA.
ICPP (1)
Hiroshi Kadota, Katsuyuki Kaneko, Yuji Tanikawa, Tatsuo Nogi