Hiroshi Inokawa

20 papers Journal 13Unranked 7
YearRankTypeTitle / Venue / Authors
2024 — conf
Deconvolution of 3D Data Measured by FMCW LiDAR Based on Image Sensor under Influence of Spatially Inhomogeneous Frequency Modulation.
GCCE
Nobuhide Yokota, Masato Ohira, Hideyuki Takahashi, Kazuya Sugiyasu, Hiroshi Inokawa, Hiroshi Yasaka
2024 J jnl
Multiple Quantum Barrier Avalanche Photodiode Based on GaN/AlGaN Heterostructures for Long Wavelength Infrared Detection.
IEEE Access
Somrita Ghosh, Aritra Acharyya, Arindam Biswas, Amit Banerjee, Hiroshi Inokawa, Hiroaki Satoh, Alexey Y. Seteikin, Ilia Samusev
2023 J jnl
Folded-Dipole Antenna Geometrical Analysis for THz Microbolometer.
IEEE Access
Arie Pangesti Aji, Hiroaki Satoh, Catur Apriono, Eko Tjipto Rahardjo, Hiroshi Inokawa
2023 J jnl
Refractive Index Measurement Using SOI Photodiode with SP Antenna toward SOI CMOS-Compatible Integrated Optical Biosensor.
Sensors
Hiroaki Satoh, Koki Isogai, Shohei Iwata, Taiki Aso, Ryosuke Hayashi, Shu Takeuchi, Hiroshi Inokawa
2022 J jnl
Angle-sensitive pixel based on silicon-on-insulator p-n junction photodiode with aluminum grating gate electrode.
IEICE Electron. Express
Hiroaki Satoh, Ken Kawakubo, Atsushi Ono, Hiroshi Inokawa
2022 J jnl
Responsivity and NEP Improvement of Terahertz Microbolometer by High-Impedance Antenna.
Sensors
Arie Pangesti Aji, Hiroaki Satoh, Catur Apriono, Eko Tjipto Rahardjo, Hiroshi Inokawa
2020 J jnl
Angle-Sensitive Detector Based on Silicon-On-Insulator Photodiode Stacked with Surface Plasmon Antenna.
Sensors
Anitharaj Nagarajan, Shusuke Hara, Hiroaki Satoh, Aruna Priya Panchanathan, Hiroshi Inokawa
2020 J jnl
Angular selectivity of SOI photodiode with surface plasmon antenna.
IEICE Electron. Express
Anitharaj Nagarajan, Shusuke Hara, Hiroaki Satoh, Aruna Priya Panchanathan, Hiroshi Inokawa
2018 J jnl
Application of bow-tie surface plasmon antenna to silicon on insulator nanowire photodiode for enhanced light absorption.
IEICE Electron. Express
Yash Sharma, Hiroaki Satoh, Hiroshi Inokawa
2016 — conf
Evaluation of multidrug cancer chronotherapy based on cell cycle model under influences of circadian clock.
EMBC
Hiroshi Inokawa, Norihiro Katayama, Mitsuyuki Nakao
2012 J jnl
Effect of Arrangement of Input Gates on Logic Switching Characteristics of Nanodot Array Device.
IEICE Trans. Electron.
Mingu Jo, Yuki Kato, Masashi Arita, Yukinori Ono, Akira Fujiwara, Hiroshi Inokawa, Yasuo Takahashi, Jung-Bum Choi
2009 J jnl
Full Adder Operation Based on Si Nanodot Array Device with Multiple Inputs and Outputs.
Int. J. Nanotechnol. Mol. Comput.
Takuya Kaizawa, Mingyu Jo, Masashi Arita, Akira Fujiwara, Kenji Yamazaki, Yukinori Ono, Hiroshi Inokawa, Yasuo Takahashi
2007 J jnl
Design of a Two-Bit-Per-Cell Content-Addressable Memory Using Single-Electron Transistors.
J. Multiple Valued Log. Soft Comput.
Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi
2007 J jnl
Transfer and Detection of Single Electrons Using Metal-Oxide-Semiconductor Field-Effect Transistors.
IEICE Trans. Electron.
Wancheng Zhang, Katsuhiko Nishiguchi, Yukinori Ono, Akira Fujiwara, Hiroshi Yamaguchi, Hiroshi Inokawa, Yasuo Takahashi, Nan-Jian Wu
2006 — conf
A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors.
ISMVL
Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Katsuhiko Nishiguchi, Yasuo Takahashi
2005 — conf
A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors.
ISMVL
Katsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi, Yasuo Takahashi
2004 — conf
A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic.
ISMVL
Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi
2004 — conf
A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions.
ISMVL
Hiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi
2003 — conf
Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic.
ISMVL
Hiroshi Inokawa, Yasuo Takahashi
1997 J jnl
A 0.5-V MTCMOS/SIMOX logic gate.
IEEE J. Solid State Circuits
Takakuni Douseki, Satoshi Shigematsu, Junzo Yamada, Mitsuru Harada, Hiroshi Inokawa, Toshiaki Tsuchiya