Hiroshi Fuketa

59 papers A* 1A 3C 1Journal 29Unranked 25

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Cryogenic CMOS Microwave Signal Selector Using Dual-Stage Injection-Locked Oscillator for Frequency-Multiplexed Qubit Control System. IEEE J. Solid State Circuits Hiroshi Fuketa, Ippei Akita, Hanpei Koike, Takahiro Mori
2025	J	`jnl`	Fully Quantized Matrix Arithmetic-Only BERT Model and Its FPGA-Based Accelerator. IEEE Access Hiroshi Fuketa, Toshihiro Katashita, Yohei Hori, Masakazu Hioki
2024	J	`jnl`	Multiplication-Free Lookup-Based CNN Accelerator Using Residual Vector Quantization and Its FPGA Implementation. IEEE Access Hiroshi Fuketa, Toshihiro Katashita, Yohei Hori, Masakazu Hioki
2024	J	`jnl`	Temperature Dependent Variations of Low-Frequency Noise Sources in Cryogenic Short-Channel Bulk MOSFETs. IEEE Access Takumi Inaba, Hiroshi Oka, Hidehiro Asai, Hiroshi Fuketa, Shota Iizuka, Kimihiko Kato, Shunsuke Shitakata, Koichi Fukuda, Takahiro Mori
2023	J	`jnl`	A Cryogenic CMOS Current Integrator and Correlation Double Sampling Circuit for Spin Qubit Readout. IEEE Trans. Circuits Syst. I Regul. Pap. Hiroshi Fuketa, Ippei Akita, Tomohiro Ishikawa, Hanpei Koike, Takahiro Mori
2023	—	`conf`	Determining the low-frequency noise source in cryogenic operation of short-channel bulk MOSFETs. VLSI Technology and Circuits Takumi Inaba, Hiroshi Oka, Hidehiro Asai, Hiroshi Fuketa, Shota Iizuka, Kimihiko Kato, Shunsuke Shitakata, Koichi Fukuda, Takahiro Mori
2023	J	`jnl`	Lookup Table-Based Computing-in-Memory Macro Approximating Dot Products Without Multiplications for Energy-Efficient CNN Inference. IEEE Trans. Circuits Syst. I Regul. Pap. Hiroshi Fuketa
2023	J	`jnl`	Origin of Low-Frequency Noise in Si n-MOSFET at Cryogenic Temperatures: The Effect of Interface Quality. IEEE Access Hiroshi Oka, Takumi Inaba, Shunsuke Shitakata, Kimihiko Kato, Shota Iizuka, Hidehiro Asai, Hiroshi Fuketa, Takahiro Mori
2022	—	`conf`	A Cryogenic CMOS Current Comparator for Spin Qubit Readout Achieving Fast Readout Time and High Current Resolution. VLSI Technology and Circuits Hiroshi Fuketa, Ippei Akita, Tomohiro Ishikawa, Hanpei Koike, Takahiro Mori
2022	J	`jnl`	Time-Delay-Neural-Network-Based Audio Feature Extractor for Ultra-Low Power Keyword Spotting. IEEE Trans. Circuits Syst. II Express Briefs Hiroshi Fuketa
2021	J	`jnl`	Edge Artificial Intelligence Chips for the Cyberphysical Systems Era. Computer Hiroshi Fuketa, Kunio Uchiyama
2021	J	`jnl`	Ultra-Low Power Hand Gesture Sensor Using Electrostatic Induction. Sensors Hiroshi Fuketa
2020	J	`jnl`	Neural ODE with Temporal Convolution and Time Delay Neural Networks for Small-Footprint Keyword Spotting. CoRR Hiroshi Fuketa, Yukinori Morita
2019	—	`conf`	Ultra-low Power Human Motion Detection Sensor using Electrostatic Induction and Demonstration of Contactless Remote Light Switch. GCCE Hiroshi Fuketa, Yukinori Morita
2018	C	`conf`	Image-Classifier Deep Convolutional Neural Network Training by 9-bit Dedicated Hardware to Realize Validation Accuracy and Energy Efficiency Superior to the Half Precision Floating Point Format. ISCAS Shin-ichi O'Uchi, Hiroshi Fuketa, Tsutomu Ikegami, Wakana Nogami, Takashi Matsukawa, Tomohiro Kudoh, Ryousei Takano
2017	J	`jnl`	A 0.3-V 1-µW Super-Regenerative Ultrasound Wake-Up Receiver With Power Scalability. IEEE Trans. Circuits Syst. II Express Briefs Hiroshi Fuketa, Shin-ichi O'Uchi, Takashi Matsukawa
2017	J	`jnl`	A Closed-Form Expression for Minimum Operating Voltage of CMOS D Flip-Flop. IEEE Trans. Very Large Scale Integr. Syst. Hiroshi Fuketa, Shin-ichi O'Uchi, Takashi Matsukawa
2017	J	`jnl`	Design and Analysis of Ultra-Low Power Glitch-Free Programmable Voltage Detector Based on Multiple Voltage Copier. IEICE Trans. Electron. Teruki Someya, Hiroshi Fuketa, Kenichi Matsunaga, Hiroki Morimura, Takayasu Sakurai, Makoto Takamiya
2017	J	`jnl`	Fully Integrated, 100-mV Minimum Input Voltage Converter With Gate-Boosted Charge Pump Kick-Started by LC Oscillator for Energy Harvesting. IEEE Trans. Circuits Syst. II Express Briefs Hiroshi Fuketa, Shin-ichi O'Uchi, Takashi Matsukawa
2017	—	`conf`	Session 15 overview: Innovations in technologies and circuits. ISSCC Jan Genoe, Hiroshi Fuketa, Eugenio Cantatore
2016	J	`jnl`	Variation-Tolerant Quick-Start-Up CMOS Crystal Oscillator With Chirp Injection and Negative Resistance Booster. IEEE J. Solid State Circuits Shunta Iguchi, Hiroshi Fuketa, Takayasu Sakurai, Makoto Takamiya
2015	—	`conf`	16.4 Energy-autonomous fever alarm armband integrating fully flexible solar cells, piezoelectric speaker, temperature detector, and 12V organic complementary FET circuits. ISSCC Hiroshi Fuketa, Masamune Hamamatsu, Tomoyuki Yokota, Wakako Yukita, Teruki Someya, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai
2015	—	`conf`	248pW, 0.11mV/°C glitch-free programmable voltage detector with multiple voltage duplicator for energy harvesting. ESSCIRC Teruki Someya, Hiroshi Fuketa, Kenichi Matsunaga, Hiroki Morimura, Takayasu Sakurai, Makoto Takamiya
2015	—	`conf`	Analysis to optimize sensitivity of RF energy harvester with voltage boost circuit. ECCTD Dan Luo, Hiroshi Fuketa, Kenichi Matsunaga, Hiroki Morimura, Makoto Takamiya, Takayasu Sakurai
2015	—	`conf`	Optimal design to maximize efficiency of single-inductor multiple-output buck converters in discontinuous conduction mode for IoT applications. ICICDT Yoshitaka Yamauchi, Yuki Yanagihara, Hiroshi Fuketa, Takayasu Sakurai, Makoto Takamiya
2015	J	`jnl`	Wireless Power Transfer With Zero-Phase-Difference Capacitance Control. IEEE Trans. Circuits Syst. I Regul. Pap. Shunta Iguchi, Pyungwoo Yeon, Hiroshi Fuketa, Koichi Ishida, Takayasu Sakurai, Makoto Takamiya
2014	J	`jnl`	1 µm-Thickness Ultra-Flexible and High Electrode-Density Surface Electromyogram Measurement Sheet With 2 V Organic Transistors for Prosthetic Hand Control. IEEE Trans. Biomed. Circuits Syst. Hiroshi Fuketa, Kazuaki Yoshioka, Yasuhiro Shinozuka, Koichi Ishida, Tomoyuki Yokota, Naoji Matsuhisa, Yusuke Inoue, Masaki Sekino, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai
2014	—	`conf`	30.3 Organic-transistor-based 2kV ESD-tolerant flexible wet sensor sheet for biomedical applications with wireless power and data transmission using 13.56MHz magnetic resonance. ISSCC Hiroshi Fuketa, Kazuaki Yoshioka, Tomoyuki Yokota, Wakako Yukita, Mari Koizumi, Masaki Sekino, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai
2014	—	`conf`	92% start-up time reduction by variation-tolerant chirp injection (CI) and negative resistance booster (NRB) in 39MHz crystal oscillator. VLSIC Shunta Iguchi, Hiroshi Fuketa, Takayasu Sakurai, Makoto Takamiya
2014	—	`conf`	An 85-mV input, 50-µs startup fully integrated voltage multiplier with passive clock boost using on-chip transformers for energy harvesting. ESSCIRC Hiroshi Fuketa, Youichi Momiyama, Atsushi Okamoto, Tsuyoshi Sakata, Makoto Takamiya, Takayasu Sakurai
2014	—	`conf`	Flexible, large-area, and distributed organic electronics closely contacted with skin for healthcare applications. MWSCAS Makoto Takamiya, Hiroshi Fuketa, Koichi Ishida, Tomoyuki Yokota, Tsuyoshi Sekitani, Takao Someya, Takayasu Sakurai
2014	J	`jnl`	Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits. IEEE J. Solid State Circuits Hiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai
2013	—	`conf`	1µm-thickness 64-channel surface electromyogram measurement sheet with 2V organic transistors for prosthetic hand control. ISSCC Hiroshi Fuketa, Kazuaki Yoshioka, Yasuhiro Shinozuka, Koichi Ishida, Tomoyuki Yokota, Naoji Matsuhisa, Yusuke Inoue, Masaki Sekino, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai
2013	J	`jnl`	Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits. IEEE J. Solid State Circuits Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2013	J	`jnl`	Insole Pedometer With Piezoelectric Energy Harvester and 2 V Organic Circuits. IEEE J. Solid State Circuits Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Yasuhiro Shinozuka, Hiroshi Fuketa, Tomoyuki Yokota, Ute Zschieschang, Hagen Klauk, Gregory Tortissier, Tsuyoshi Sekitani, Hiroshi Toshiyoshi, Makoto Takamiya, Takao Someya, Takayasu Sakurai
2013	—	`conf`	Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits. ISSCC Hiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai
2013	—	`conf`	Large-area and flexible sensors with organic transistors. IWASI Hiroshi Fuketa, Koichi Ishida, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai
2013	J	`jnl`	Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: V IEEE Trans. Very Large Scale Integr. Syst. Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2013	—	`conf`	Reducing IR drop in 3D integration to less than 1/4 using Buck Converter on Top die (BCT) scheme. ISQED Yasuhiro Shinozuka, Hiroshi Fuketa, Koichi Ishida, Futoshi Furuta, Kenichi Osada, Kenichi Takeda, Makoto Takamiya, Takayasu Sakurai
2013	—	`conf`	Variation-aware subthreshold logic circuit design. ASICON Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2012	—	`conf`	13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO. ISSCC Koji Hirairi, Yasuyuki Okuma, Hiroshi Fuketa, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2012	—	`conf`	24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V ISQED Tadashi Yasufuku, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai
2012	J	`jnl`	Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits. IEEE Trans. Very Large Scale Integr. Syst. Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2012	—	`conf`	Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits. CICC Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2012	—	`conf`	Insole pedometer with piezoelectric energy harvester and 2V organic digital and analog circuits. ISSCC Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Yasuhiro Shinozuka, Hiroshi Fuketa, Tomoyuki Yokota, Ute Zschieschang, Hagen Klauk, Gregory Tortissier, Tsuyoshi Sekitani, Makoto Takamiya, Hiroshi Toshiyoshi, Takao Someya, Takayasu Sakurai
2012	J	`jnl`	Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature. IEEE Trans. Circuits Syst. II Express Briefs Ryo Takahashi, Hidehiro Takata, Tadashi Yasufuku, Hiroshi Fuketa, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2012	J	`jnl`	On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Xin Zhang, Koichi Ishida, Hiroshi Fuketa, Makoto Takamiya, Takayasu Sakurai
2011	A	`conf`	12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V ISLPED Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2011	A*	`conf`	A closed-form expression for estimating minimum operating voltage (V DAC Hiroshi Fuketa, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2011	J	`jnl`	An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion. IEEE Trans. Circuits Syst. II Express Briefs Hiroshi Fuketa, Dan Kuroda, Masanori Hashimoto, Takao Onoye
2011	A	`conf`	Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS. ISLPED Tadashi Yasufuku, Satoshi Iida, Hiroshi Fuketa, Koji Hirairi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai
2010	—	`conf`	Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits. ASP-DAC Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2010	J	`jnl`	Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits. IEEE Trans. Very Large Scale Integr. Syst. Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2009	—	`conf`	Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits. CICC Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2009	J	`jnl`	An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability. IEICE Trans. Electron. Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2009	J	`jnl`	Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2009	—	`conf`	Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction. ASP-DAC Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2008	A	`conf`	Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits. ISLPED Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2008	—	`conf`	Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --. ACM Great Lakes Symposium on VLSI Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye