Hiroomi Hikawa

73 papers B 17C 9Journal 23Unranked 24
YearRankTypeTitle / Venue / Authors
2025 J jnl
Hardware Self-Organizing Map With Dithered Step Neighborhood Function.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hiroomi Hikawa
2024 J jnl
Electroencephalogram-Based Facial Gesture Recognition Using Self-Organizing Map.
Sensors
Takahiro Kawaguchi, Koki Ono, Hiroomi Hikawa
2023 J jnl
A Survey of Hardware Self-Organizing Maps.
IEEE Trans. Neural Networks Learn. Syst.
Slavisa Jovanovic, Hiroomi Hikawa
2021 B conf
A Synthesis Method of Spiking Neural Oscillators with Considering Asymptotic Stability.
IJCNN
Yasuaki Kuroe, Seiji Miyoshi, Hiroomi Hikawa, Hidetaka Ito, Kimiko Motonaka, Yutaka Maeda
2021 J jnl
Hardware Self-Organizing Map Based on Digital Frequency-Locked Loop and Triangular Neighborhood Function.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hiroomi Hikawa
2020 — conf
Nested Pipeline Hardware Self-Organizing Map for High Dimensional Vectors.
ICECS
Hiroomi Hikawa
2019 B conf
Nested Hardware Architecture for Self-Organizing Map.
IJCNN
Hiroomi Hikawa
2018 C conf
A New Hardware Self-Organizing Map Architecture with High Expandability.
IPAS
Hiroomi Hikawa, Hidetaka Ito, Yutaka Maeda
2018 — conf
A New Self-Organizing Map with Continuous Learning Capability.
SSCI
Hiroomi Hikawa, Hidetaka Ito, Yutaka Maeda
2018 J jnl
A Subspace Newton-Type Method for Approximating Transversely Repelling Chaotic Saddles.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hidetaka Ito, Hiroomi Hikawa, Yutaka Maeda
2018 C conf
Hardware Self-Organizing Map Based on Frequency-Modulated Signal and Digital Frequency-Locked Loop.
ISCAS
Hiroomi Hikawa, Hidetaka Ito, Yutaka Maeda
2018 J jnl
Off-Chip Training with Additive Perturbation for FPGA-Based Hand Sign Recognition System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hiroomi Hikawa, Masayuki Tamaki, Hidetaka Ito
2018 J jnl
SOM-Based Vector Recognition with Pre-Grouping Functionality.
IEICE Trans. Inf. Syst.
Yuto Kurosaki, Masayoshi Ohta, Hidetaka Ito, Hiroomi Hikawa
2016 — conf
Effect of grouping in vector recognition system based on SOM.
SSCI
Masayoshi Ohta, Yuto Kurosaki, Hidetaka Ito, Hiroomi Hikawa
2016 — conf
Gesture Spotting by Using Vector Distance of Self-organizing Map.
ICONIP (2)
Yuta Ichikawa, Shuji Tashiro, Hidetaka Ito, Hiroomi Hikawa
2016 — conf
Improved winner-take-all circuit for neural network based on frequency-modulated signals.
ICECS
Hiroomi Hikawa
2016 C conf
Live demonstration: Off-chip learning for hardware hand-sign recognition system.
ISCAS
Masayuki Tamaki, Hiroomi Hikawa
2016 C conf
Off-chip learning for hardware hand-sign recognition system.
ISCAS
Masayuki Tamaki, Hiroomi Hikawa
2016 — conf
Real time gesture recognition system with gesture spotting function.
SSCI
Yuta Ichikawa, Shuji Tashiro, Hidetaka Ito, Hiroomi Hikawa
2015 J jnl
Improved Learning Performance of Hardware Self-Organizing Map Using a Novel Neighborhood Function.
IEEE Trans. Neural Networks Learn. Syst.
Hiroomi Hikawa, Yutaka Maeda
2015 J jnl
Low-Power Wiring Method for Band-Limited Signals in CMOS Logic Circuits by Segmentation Coding with Pseudo-Majority Voting.
IEICE Trans. Electron.
Katsuhiko Ueda, Zuiko Rikuhashi, Kentaro Hayashi, Hiroomi Hikawa
2015 J jnl
Novel FPGA Implementation of Hand Sign Recognition System With SOM-Hebb Classifier.
IEEE Trans. Circuits Syst. Video Technol.
Hiroomi Hikawa, Keishi Kaida
2015 J jnl
Scalable Hardware Winner-Take-All Neural Network with DPLL.
IEICE Trans. Inf. Syst.
Masaki Azuma, Hiroomi Hikawa
2015 B conf
Vector classification by a winner-take-all neural network with digital frequency-locked loop.
IJCNN
Hiroomi Hikawa
2015 C conf
Winner-take-all neural network with digital frequency-locked loop.
ISCAS
Hiroomi Hikawa
2014 C conf
Low-power wiring method in CMOS logics circuits by segmentation coding and pseudo majority voting.
ISCAS
Katsuhiko Ueda, Zuiko Rikuhashi, Kentaro Hayashi, Hiroomi Hikawa
2014 — conf
Supervised learning of DPLL based winner-take-all neural network.
ICES
Masaki Azuma, Hiroomi Hikawa
2013 — conf
A new winner-take-all neural network using DPLL and phase modulated signal.
ISPACS
Masaki Azuma, Hiroomi Hikawa
2013 — conf
Color-space image compression with hardware Self-organizing map.
ISPACS
Naoki Terahara, Yoshiro Oba, Hiroomi Hikawa
2013 B conf
DPLL based hardware SOM with a new winner-take-all circuit.
IJCNN
Hiroomi Hikawa
2012 B conf
Real time gesture recognition system using posture classifier and Jordan recurrent neural network.
IJCNN
Yusuke Araga, Makoto Shirabayashi, Keishi Kaida, Hiroomi Hikawa
2012 — conf
Sequential vector classifier based on SOM and feedback Hebbian network.
ISPACS
Yusuke Araga, Zuiko Rikuhashi, Hiroomi Hikawa
2011 — conf
Automatic generation of hardware self-organizing map for FPGA implementation.
ISPACS
Kota Yamamoto, Yoshiro Oba, Zuiko Rikuhashi, Hiroomi Hikawa
2011 B conf
Hand sign recognition system based on SOM-Hebb hybrid network.
SMC
Hiroomi Hikawa, Keishi Kaida
2011 — conf
Hardware design of a color quantization with self-organizing map.
ISPACS
Yoshiro Oba, Kota Yamamoto, Takahiro Nagai, Hiroomi Hikawa
2011 — conf
Learning Scheme for Complex Neural Networks Using Simultaneous Perturbation.
ICANN (2)
Yutaka Maeda, Takahiro Yamada, Seiji Miyoshi, Hiroomi Hikawa
2011 J jnl
ROM-Less Phase to Amplitude Converter Using Sine Wave Approximation Based on Harmonic Removal from Trapezoid Wave.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hiroomi Hikawa
2011 B conf
Study on gesture recognition system using posture classifier and Jordan recurrent neural network.
IJCNN
Hiroomi Hikawa, Yusuke Araga
2010 B conf
Comparison of range check classifier and hybrid network classifier for hand sign recognition system.
IJCNN
Hiroomi Hikawa, Seito Yamazaki, Tatsuya Ando, Simone Miyoshi, Yutaka Maeda
2010 B conf
Image compression with hardware self-organizing map.
IJCNN
Hiroomi Hikawa, Kenji Doumoto, Simone Miyoshi, Yutaka Maeda
2010 C conf
Phase amplitude converter with conditional shift operation.
ISCAS
Hiroomi Hikawa, Taketo Namba
2009 C conf
DDFS with New Sinusoid Approximation based on Harmonics Removal.
ISCAS
Hiroomi Hikawa
2009 B conf
Hand sign recognition system based on hybrid network classifier.
IJCNN
Yuuki Taki, Hiroomi Hikawa, Seiji Miyoshi, Yutaka Maeda
2009 B conf
On automatic generation of VHDL code for self-organizing map.
IJCNN
Akira Onoo, Hiroomi Hikawa, Seiji Miyoshi, Yutaka Maeda
2009 B conf
On simultaneous perturbation particle swarm optimization.
IEEE Congress on Evolutionary Computation
Yutaka Maeda, Naoto Matsushita, Seiji Miyoshi, Hiroomi Hikawa
2009 J jnl
Statistical Mechanical Analysis of Simultaneous Perturbation Learning.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Seiji Miyoshi, Hiroomi Hikawa, Yutaka Maeda
2008 — conf
Hardware Design of Japanese Hand Sign Recognition System.
ICONIP (2)
Hiroomi Hikawa, Hirotada Fujimura
2007 — conf
A New Hardware Friendly Vector Distance Evaluation Function for Vector Classifiers.
ICONIP (2)
Hiroomi Hikawa, Kaori Kugimiya
2007 J jnl
Hardware Feedback Self-Organizing Map and its Application to Mobile Robot Location Identification.
J. Adv. Comput. Intell. Intell. Informatics
Hiroomi Hikawa, Kazutoshi Harada, Takenori Hirabayashi
2007 — conf
Japanese Hand Sign Recognition System.
ICONIP (1)
Hirotada Fujimura, Yuuichi Sakai, Hiroomi Hikawa
2007 B conf
Performance Comparison of SOM Based Hybrid Hardware Classifiers.
IJCNN
Hiroomi Hikawa, Taku Miyanishi, Kousuke Tamaya
2007 B conf
Pseudo RBF Network for Position Independent Hand Posture Recognition System.
IJCNN
Hiroomi Hikawa, Shigeki Matsubara
2006 B conf
Vector Quantization System Based on Scalar SOM/AND-OR Hybrid Network.
IJCNN
Hiroomi Hikawa
2005 B conf
A new pulse mode self organizing map hardware with digital phase locked loops.
IJCNN
Hiroomi Hikawa
2005 J jnl
FPGA implementation of self organizing map with digital phase locked loops.
Neural Networks
Hiroomi Hikawa
2005 — conf
Hardware friendly vector quantization algorithm.
ISCAS (4)
Shigeki Matsubara, Hiroomi Hikawa
2004 B conf
Digital pulse mode neuron with robust nonlinear activation function.
IJCNN
Hiroomi Hikawa
2004 — conf
Direct digital frequency synthesizer with multi-stage linear interpolation.
ISCAS (4)
Hiroomi Hikawa
2003 J jnl
A digital hardware pulse-mode neuron with piecewise linear activation function.
IEEE Trans. Neural Networks
Hiroomi Hikawa
2003 J jnl
A multilayer neural network with pulse position modulation.
Syst. Comput. Jpn.
Hiroomi Hikawa
2003 J jnl
A new digital pulse-mode neuron with adjustable activation function.
IEEE Trans. Neural Networks
Hiroomi Hikawa
2003 — conf
Pulse mode neuron with leakage integrator and additive random noise.
ISCAS (5)
Hiroomi Hikawa
2001 — conf
Digital pulse mode neural network with simple synapse multiplier.
ISCAS (3)
Hiroomi Hikawa
2000 J jnl
An efficient three-valued multilayer neural network with on-chip learning suitable for hardware implementation.
Syst. Comput. Jpn.
Hiroomi Hikawa
2000 — conf
Pulse Mode Multilayer Neural Network with Floating Point Operation and On-Chip Learning.
IJCNN (2)
Hiroomi Hikawa
2000 C conf
Pulse mode multilayer neural network based on floating point number representation.
ISCAS
Hiroomi Hikawa
1999 — conf
An efficient pulse mode multilayer neural network.
ISCAS (5)
Hiroomi Hikawa
1999 J jnl
Frequency-based multilayer neural network with on-chip learning and enhanced neuron characteristics.
IEEE Trans. Neural Networks
Hiroomi Hikawa
1999 J jnl
Implementation of multilayer neural network with threshold neurons and its analysis.
Artif. Life Robotics
Kazuo Sato, Hiroomi Hikawa
1995 — conf
Implementation of simplified multilayer neural networks with on-chip learning.
ICNN
Hiroomi Hikawa
1994 — conf
Parallel Architecture for Universal Digital Signal Processing.
HICSS (1)
Vijay K. Jain, Hiroomi Hikawa
1992 J jnl
A radix-8 wafer scale FFT processor.
J. VLSI Signal Process.
Earl E. Swartzlander Jr., Vijay K. Jain, Hiroomi Hikawa
1992 J jnl
An Architecture for WSI Rapid Prototyping.
Computer
Vijay K. Jain, Hiroomi Hikawa, David C. Keezer