Hiroo Masuda

31 papers Journal 21Unranked 10
YearRankTypeTitle / Venue / Authors
2010 J jnl
A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Takashi Sato, Toshiki Kanamoto, Saiko Kobayashi, Nobuhiko Goto, Takao Sato, Hitoshi Sugihara, Hiroo Masuda
2010 J jnl
Impact of Self-Heating in Wire Interconnection on Timing.
IEICE Trans. Electron.
Toshiki Kanamoto, Takaaki Okumura, Katsuhiro Furukawa, Hiroshi Takafuji, Atsushi Kurokawa, Koutaro Hachiya, Tsuyoshi Sakata, Masakazu Tanaka, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto
2009 J jnl
An Approach for Reducing Leakage Current Variation due to Manufacturing Variability.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Tsuyoshi Sakata, Takaaki Okumura, Atsushi Kurokawa, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto, Koutaro Hachiya, Katsuhiro Furukawa, Masakazu Tanaka, Hiroshi Takafuji, Toshiki Kanamoto
2009 J jnl
Comprehensive Matching Characterization of Analog CMOS Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hiroo Masuda, Takeshi Kida, Shin-ichi Ohkawa
2009 J jnl
Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Takaaki Okumura, Atsushi Kurokawa, Hiroo Masuda, Toshiki Kanamoto, Masanori Hashimoto, Hiroshi Takafuji, Hidenari Nakashima, Nobuto Ono, Tsuyoshi Sakata, Takashi Sato
2008 J jnl
A Novel Expression of Spatial Correlation by a Random Curved Surface Model and Its Application to LSI Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shin-ichi Ohkawa, Hiroo Masuda, Yasuaki Inoue
2008 J jnl
Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis.
IEICE Trans. Electron.
Masakazu Aoki, Shin-ichi Ohkawa, Hiroo Masuda
2006 J jnl
Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Atsushi Kurokawa, Hiroo Masuda, Junko Fujii, Toshinori Inoshita, Akira Kasebe, Zhangcai Huang, Yasuaki Inoue
2006 J jnl
Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Atsushi Kurokawa, Akira Kasebe, Toshiki Kanamoto, Yun Yang, Zhangcai Huang, Yasuaki Inoue, Hiroo Masuda
2005 J jnl
A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Atsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Inoue, Hiroo Masuda
2005 — conf
Approach for physical design in sub-100 nm era.
ISCAS (6)
Hiroo Masuda, Shin-ichi Ohkawa, Masakazu Aoki
2005 — conf
Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture.
ISQED
Atsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda
2005 — conf
Challenge: variability characterization and modeling for 65- to 90-nm processes.
CICC
Hiroo Masuda, Shin-ichi Ohkawa, Atsushi Kurokawa, Masakazu Aoki
2005 J jnl
Design Guidelines and Process Quality Improvement for Treatment of Device Variations in an Lsi Chip.
IEICE Trans. Electron.
Masakazu Aoki, Shin-ichi Ohkawa, Hiroo Masuda
2005 — conf
Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills.
ISQED
Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda
2005 J jnl
Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda
2005 J jnl
Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Atsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda
2004 — conf
DEPOGIT: dense power-ground interconnect architecture for physical design integrity.
ASP-DAC
Atsushi Kurokawa, Nobuto Ono, Tetsuro Kage, Hiroo Masuda
2004 — conf
Efficient capacitance extraction method for interconnects with dummy fills.
CICC
Atsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Inoue, Hiroo Masuda
2004 — conf
Large-scale linear circuit simulation with an inversed inductance matrix.
ASP-DAC
Chieki Mizuta, Jiro Iwai, Ken Machida, Tetsuro Kage, Hiroo Masuda
2003 — conf
Approximate formulae approach for efficient inductance extraction.
ASP-DAC
Atsushi Kurokawa, Takashi Sato, Hiroo Masuda
2003 J jnl
Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Atsushi Kurokawa, Takashi Sato, Hiroo Masuda
2003 J jnl
Crosstalk delay analysis of a 0.13-μm node test chip and precise gate-level simulation technology.
IEEE J. Solid State Circuits
Yasuhiko Sasaki, Mitsumasa Sato, Masaru Kuramoto, Fujio Kikuchi, Tsutomu Kawashima, Hiroo Masuda, Kazuo Yano
2003 — conf
Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect Delay.
ISQED
Takashi Sato, Hiroo Masuda
2003 J jnl
Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Atsushi Kurokawa, Kotaro Hachiya, Takashi Sato, Kazuya Tokumasu, Hiroo Masuda
1998 — conf
TCAD/DA for MPU and ASIC Development.
ASP-DAC
Hiroo Masuda, Katsumi Tsuneno, Hisako Sato, Kazutaka Mori
1991 J jnl
A submicrometer MOS transistor I-V model for circuit simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hiroo Masuda, Jun'ichi Mano, Ryuichi Ikematsu, Hitoshi Sugihara, Yukio Aoki
1988 J jnl
MOSTSM: a physically based charge conservative MOSFET model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hiroo Masuda, Yukio Aoki, Jun'ichi Mano, Osamu Yamashiro
1987 J jnl
A New Design-Centering Methodology for VLSI Device Development.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yukio Aoki, Hiroo Masuda, Shozo Shimada, Shoji Sato
1987 J jnl
A Two-Dimensional Integrated Process Simulator: SPIRIT-I.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Masanori Ohgo, Yasuko Takano, Akemi Moniwa, Shuichi Yamamoto, Yoshio Sakai, Hiroo Masuda, Hideo Sunami
1985 J jnl
Three-Dimensional Device Simulator CADDETH with Highly Convergent Matrix Solution Algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Toru Toyabe, Hiroo Masuda, Yukio Aoki, Hiroko Shukuri, Takaaki Hagiwara