Hironori Nakajo

73 papers A 2B 2C 4Misc 17Journal 17Unranked 31

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Kyress: a secure, scalable, and resource-efficient CRYSTALS-Kyber cryptosystem for low-cost embedded devices. J. Supercomput. Kien Tran-Hoang, Hironori Nakajo
2026	J	`jnl`	Stacking Binary Neural Networks for Efficient Edge-Based Waste Classification. IEEE Access Duc-Anh Pham, Shimizu Ikuko, Hironori Nakajo
2025	J	`jnl`	Learning Algorithm for LesserDNN, a DNN with Quantized Weights. Informatica (Slovenia) Masashi Takemoto, Yasutake Masuda, Jingyong Cai, Hironori Nakajo
2025	—	`conf`	Loss-Decoupled Training in Deep Image Classification: Co-optimization of Encoder and Classifier with Gaussian Mixture Model. IIAI-AAI-Winter Kataru Hara, Ikuko Shimizu, Hironori Nakajo
2025	J	`jnl`	Preliminary evaluation of SHAVER: sharing vector registers with an accelerator. J. Supercomput. Tomoaki Tanaka, Michiya Kato, Yasunori Osana, Takefumi Miyoshi, Jubee Tada, Kiyofumi Tanaka, Hironori Nakajo
2025	J	`jnl`	Simulation environment for reconfigurable virtual accelerators using a field programmable gate array development environment. J. Supercomput. Shunya Kawai, Eriko Maeda, Kazuki Yaguchi, Yasunori Osana, Takefumi Miyoshi, Hironori Nakajo
2024	—	`conf`	Matthiola incana classification using CNN and class activation maps for model understanding. CANDARW Kentaro Machida, Soma Asuka, Tomomi Osaka, Fumikazu Watanabe, Hironori Nakajo
2024	—	`conf`	Weed Detection from the Duck's Perspective Using Aqua-Drone in Rice Paddies. GCCE Soma Asuka, Kentaro Machida, Tetsuya Nakamura, Ikuko Shimizu, Taiichiro Ookawa, Hironori Nakajo
2023	—	`conf`	Learning Algorithm for LesserDNN, a DNN with Quantized Weights. SoICT Masashi Takemoto, Yasutake Masuda, Jingyong Cai, Hironori Nakajo
2022	—	`conf`	Implementation of a RISC-V SMT Core in an AI processor. SoICT Hidetaro Tanaka, Tomoaki Tanaka, Ryosuke Higashi, Tsutomu Sekibe, Shuichi Takada, Hironori Nakajo
2021	J	`jnl`	Editor's Message to Special Issue of Embedded Systems Engineering. J. Inf. Process. Hironori Nakajo
2020	J	`jnl`	A Ruby-Based Hardware/Software Co-Design Environment with Functional Reactive Programming: Mulvery. IEICE Trans. Inf. Syst. Daichi Teruya, Hironori Nakajo
2020	J	`jnl`	Editor's Message to Special Issue on Embedded Systems Engineering. J. Inf. Process. Hironori Nakajo
2020	J	`jnl`	Editor's Message to Special Issue on Embedded Systems Engineering. J. Inf. Process. Hironori Nakajo
2019	—	`conf`	Cow estrus detection with low-frequency accelerometer sensor by unsupervised learning. SoICT Tran Viet Toan, Rin Nishikawa, Le Tien Thanh, Masashi Takemoto, Tran Van Hoai, Huynh Thi Thanh Binh, Hironori Nakajo
2019	J	`jnl`	Editor's Message to Special Issue on Embedded Systems Engineering. J. Inf. Process. Hironori Nakajo
2019	—	`conf`	Interactive Cultivation System for the Future IoT-Based Agriculture. CANDAR Workshops Kesevan Veloo, Hayate Kojima, Shogo Takata, Masashi Nakamura, Hironori Nakajo
2019	—	`conf`	Parallelization of Recursive Function in Ruby-Based High-Level Synthesis. FPT Ryota Yamashita, Daichi Teruya, Hironori Nakajo
2018	—	`conf`	A Deep Look into Logarithmic Quantization of Model Parameters in Neural Networks. IAIT Jingyong Cai, Masashi Takemoto, Hironori Nakajo
2018	—	`conf`	Cow estrus detection via Discrete Wavelet Transformation and Unsupervised Clustering. SoICT Le Tien Thanh, Rin Nishikawa, Masashi Takemoto, Huynh Thi Thanh Binh, Hironori Nakajo
2018	J	`jnl`	Editor's Message to Special Issue on Embedded Systems Engineering. J. Inf. Process. Hironori Nakajo
2018	J	`jnl`	Fault-tolerant Routing based on Routing Capabilities in a Hyper-Star Graph. J. Inf. Sci. Eng. Yo Nishiyama, Yuko Sasaki, Yuki Hirai, Hironori Nakajo, Keiichi Kaneko
2018	—	`conf`	Implementation of DNN on a RISC-V Open Source Microprocessor for IoT devices. GCCE Jingyong Cai, Masashi Takemoto, Hironori Nakajo
2018	—	`conf`	Operation in Partitioned Circuits with Scalable Hardware Mechanism. JCSSE Yusuke Katoh, Hironari Yoshiuchi, Yoshio Murata, Hironori Nakajo
2017	—	`conf`	Hardware Acceleration with Multi-Threading of Java-Based High Level Synthesis Tool. HEART Yuto Ishikawa, Keitaro Yanai, Keisuke Koike, Takefumi Miyoshi, Hironori Nakajo
2017	—	`conf`	Performance evaluation of an SoC for the real-time lens-free imager RALFIE. GCCE Masashi Takemoto, Ryota Suzuki, Katsuhiko Umeno, Masayuki Yashiro, Tetsuya Ryuchi, Kohta Ohshima, Naoya Kitagawa, Hironori Nakajo
2016	—	`conf`	Design of real-time advanced lens free imager. SoICT Masashi Takemoto, Ryota Suzuki, Katsuhiko Umeno, Masayuki Yashiro, Tetsuya Ryuchi, Kohta Ohshima, Naoya Kitagawa, Hironori Nakajo
2011	—	`conf`	A memory accelerator with gather functions for bandwidth-bound irregular applications. IA3@SC Noboru Tanabe, Boonyasitpichai Nuttapon, Hironori Nakajo, Yuka Ogawa, Junko Kogou, Masami Takata, Kazuki Joe
2011	Misc	`conf`	Detecting water waste activities for water-efficient living. UbiComp Trang Thuy Vu, Akifumi Sokan, Hironori Nakajo, Kaori Fujinami, Jaakko Suutala, Pekka Siirtola, Tuomo Alasalmi, Ari Pitkänen, Juha Röning
2011	J	`jnl`	Evaluation of GPU-Based Empirical Mode Decomposition for Off-Line Analysis. IEICE Trans. Inf. Syst. Pulung Waskito, Shinobu Miwa, Yasue Mitsukura, Hironori Nakajo
2011	—	`conf`	Feature Selection and Activity Recognition to Detect Water Waste from Water Tap Usage. RTCSA (2) Trang Thuy Vu, Akifumi Sokan, Hironori Nakajo, Kaori Fujinami, Jaakko Suutala, Pekka Siirtola, Tuomo Alasalmi, Ari Pitkänen, Juha Röning
2011	Misc	`conf`	Reconfigurable Android with an FPGA Accelerator for the Future Embedded Devices. ICNC Hironori Nakajo, Keisuke Koike, Atsushi Ohta, Kohta Ohshima, Kaori Fujinami
2010	—	`conf`	Acceleration for MPI derived datatypes using an enhancer of memory and network. IPDPS Workshops Noboru Tanabe, Hironori Nakajo
2010	—	`conf`	An Effective Replacement Policy Focusing on Lifetime of a Cache Line. CDES Hiroki Yokoyama, Yuhei Horibe, Peng Zhang, Shinobu Miwa, Hironori Nakajo
2010	J	`jnl`	An enhancer of memory and network for applications with large-capacity data and non-continuous data accessing. J. Supercomput. Noboru Tanabe, Hirotaka Hakozaki, Hiroshi Ando, Yasunori Dohi, Zhengzhe Luo, Hironori Nakajo
2010	Misc	`conf`	Parallelizing Hilbert-Huang Transform on a GPU. ICNC Pulung Waskito, Shinobu Miwa, Yasue Mitsukura, Hironori Nakajo
2009	C	`conf`	An Effective Replacement Strategy of Cache Memory for an SMT Processor. DSD Yoshiyasu Ogasawara, Hironori Nakajo
2009	—	`conf`	Dynamic Switching Techniques of Accessing L1/L2 Cache on an SMT Processor. CDES Yoshiyasu Ogasawara, Pulung Waskito, Shinobu Miwa, Hironori Nakajo
2009	B	`conf`	Network Interface Architecture for Scalable Message Queue Processing. ICPADS Noboru Tanabe, Atsushi Ohta, Pulung Waskito, Hironori Nakajo
2009	Misc	`conf`	The architecture of visualization system using memory with memory-side gathering and CPUs with DMA-type memory accessing. PDPTA Noboru Tanabe, Manami Sasaki, Hironori Nakajo, Masami Takata, Kazuki Joe
2008	C	`conf`	An Enhancer of Memory and Network for Cluster and its Applications. PDCAT Noboru Tanabe, Hironori Nakajo
2008	—	`conf`	Introduction to Acceleration for MPI Derived Datatypes Using an Enhancer of Memory and Network. PVM/MPI Noboru Tanabe, Hironori Nakajo
2008	—	`conf`	Low-Complexity Bypass Network Using Small RAM. CDES Shinobu Miwa, Hironori Ichibayashi, Hidetsugu Irie, Masahiro Goshima, Hironori Nakajo, Shinji Tomita
2007	Misc	`conf`	Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot. PDPTA Atsushi Ohta, Yoshihiro Hamada, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo
2007	J	`jnl`	Introduction. SIGARCH Comput. Archit. News Kenji Kise, Toshinori Sato, Hironori Nakajo
2007	—	`conf`	Performance evaluation on low-latency communication mechanism of DIMMnet-2. Parallel and Distributed Computing and Networks Akira Kitamura, Yasuo Miyabe, Tomotaka Miyashiro, Noboru Tanabe, Hironori Nakajo, Hideharu Amano
2007	Misc	`conf`	Toward Parallel and Distributed Processing on High-Density Network with Mobile Devices. PDPTA Satoshi Watanabe, Yoshiyasu Ogasawara, Ippei Tate, Hirofumi Yano, Hironori Nakajo
2006	Misc	`conf`	A Model of Implementable SMT Processor on FPGA. PDPTA Ippei Tate, Yoshiyasu Ogasawara, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Satoshi Watanabe, Mitaro Namiki, Hironori Nakajo
2006	B	`conf`	DIMMnet-2: A Reconfigurable Board Connected Into a Memory Slot. FPL Tomotaka Miyashiro, Akira Kitamura, Hironori Nakajo, Noboru Tanabe
2006	Misc	`conf`	Implementation of PC Cluster System with Memory Mapped File by Commodity OS. PDPTA Jun Kanai, Takuro Mori, Takeshi Araki, Noboru Tanabe, Hironori Nakajo, Mitaro Namiki
2006	Misc	`conf`	Towards Reconfigurable Cache Memory for a Multithreaded Processor. PDPTA Yoshiyasu Ogasawara, Ippei Tate, Satoshi Watanabe, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Mitaro Namiki, Hironori Nakajo
2005	Misc	`conf`	A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. PDPTA Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo
2005	Misc	`conf`	A Packet Forwarding Layer for DIMMnet and its Hardware Implementation. PDPTA Yoshihiro Hamada, Hiroaki Nishi, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo
2005	Misc	`conf`	Development of a Thread Scheduler for SMT Processor Architecture. PDPTA Kaname Uchikura, Koichi Sasada, Mikiko Sato, Masanori Yamato, Norito Kato, Hironori Nakajo, Mitaro Namiki
2005	C	`conf`	Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board. PDCAT Akira Kitamura, Yasuo Miyabe, Tetsu Izawa, Tomotaka Miyashiro, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano, Yoshihiro Hamada, Noboru Tanabe, Hironori Nakajo
2005	—	`conf`	Implementation and Evaluation of the Mechanisms for Low Latency Communication on DIMMnet-2. ISHPC Yasuo Miyabe, Akira Kitamura, Yoshihiro Hamada, Tomotaka Miyashiro, Tetsu Izawa, Noboru Tanabe, Hironori Nakajo, Hideharu Amano
2004	—	`conf`	A New Memory Module for Memory Intensive Applications. PARELEC Noboru Tanabe, Hironori Nakajo, Hirotaka Hakozaki, Masasige Nakatake, Yasunori Dohi, Hideharu Amano
2004	Misc	`conf`	Dynamic Allocation of Physical Register Banks for an SMT Processor. PDPTA Norito Kato, Masanori Yamato, Osamu Tujimoto, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo
2003	Misc	`conf`	A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture. PDPTA Mikiko Sato, Koichi Sasada, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki
2003	Misc	`conf`	Implementation and Evaluation of a Thread Library for Multithreaded Architecture. PDPTA Koichi Sasada, Mikiko Sato, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki
2003	Misc	`conf`	Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number. PDPTA Hironori Nakajo, Masanori Yamato, Shoji Kawahara, Norito Kato, Koichi Sasada, Mikiko Sato, Mitaro Namiki
2002	—	`conf`	Low Latency Communication on DIMMnet-1 Network Interface Plugged into a DIMM Slot. PARELEC Noboru Tanabe, Yoshihiro Hamada, Hironori Nakajo, Hideki Imashiro, Junji Yamamoto, Tomohiro Kudoh, Hideharu Amano
2002	J	`jnl`	Low Latency High Bandwidth Message Transfer Mechanisms for a Network Interface Plugged into a Memory Slot. Clust. Comput. Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano
2000	J	`jnl`	A Distributed Shared-Memory System on a Workstation Cluster Using Fast Serial Links. Int. J. Parallel Program. Hironori Nakajo, Akihiro Ichikawa, Yukio Kaneda
2000	Misc	`conf`	Coherence Protocol for Home Proxy Cache on RHiNET. PDPTA Hironori Nakajo, M. Ishii, T. Kudo, Hideharu Amano
2000	C	`conf`	MEMOnet : Network interface plugged into a memory slot. CLUSTER Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano
2000	—	`conf`	On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism. ISPAN Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano
1998	—	`conf`	Distributed Shared-Memory for a Workstation Cluster with a High Speed Serial Interface. HPCN Europe Hironori Nakajo, Hidekazu Tanaka, Yoshinori Nakanishi, Masaki Kohata, Yukio Kaneda
1997	A	`conf`	An I/O Network Architecture of the Distributed Shared-Memory Massively Parallel Computer JUMP-1. International Conference on Supercomputing Hironori Nakajo, Satoshi Ohtani, Takashi Matsumoto, Masadi Kohata, Kei Hiraki, Yukio Kaneda
1997	—	`conf`	An Implementation and Evaluation of a Distributed Shared-Memory System on Workstation Clusters Using Fast Serial Links. ISHPC Hironori Nakajo, Akihiro Ichikawa, Yukio Kaneda
1996	A	`conf`	A Simulation-based Evaluation of a Disk I/O Subsystem for a Massively Parallel Computer: JUMP-1. ICDCS Hironori Nakajo, Satoshi Ohtani, Yukio Kaneda
1995	—	`conf`	High Performance I/O System of the Distributed Shared-Memory Massively Parallel Computer JUMP-1. Parallel and Distributed Computing and Systems Hironori Nakajo, Takashi Matsumoto, Masaki Kohata, Hideo Matsuda, Kei Hiraki, Yukio Kaneda
1994	—	`conf`	Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations. ISPAN Kei Hiraki, Hideharu Amano, Morihiro Kuga, Toshinori Sueyoshi, Tomohiro Kudoh, Hiroshi Nakashima, Hironori Nakajo, Hideo Matsuda, Takashi Matsumoto, Shin-ichiro Mori