Hiromitsu Kimura

21 papers C 1Journal 7Unranked 13

Year	Rank	Type	Title / Venue / Authors
2018	J	`jnl`	A 11.3-µA Physical Activity Monitoring System Using Acceleration and Heart Rate. IEICE Trans. Electron. Motofumi Nakanishi, Shintaro Izumi, Mio Tsukahara, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Masahiko Yoshimoto
2017	—	`conf`	A 19-μA metabolic equivalents monitoring SoC using adaptive sampling. ASP-DAC Mio Tsukahara, Shintaro Izumi, Motofumi Nakanishi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori
2016	—	`conf`	A 15-μA metabolic equivalents monitoring system using adaptive acceleration sampling and normally off computing. ICECS Mio Tsukahara, Shintaro Izumi, Motofumi Nakanishi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori
2015	J	`jnl`	A Wearable Healthcare System With a 13.7 µ A Noise Tolerant ECG Processor. IEEE Trans. Biomed. Circuits Syst. Shintaro Izumi, Ken Yamashita, Masanao Nakano, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto
2015	—	`conf`	A ferroelectric-based non-volatile flip-flop for wearable healthcare systems. NVMTS Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Hiromitsu Kimura, Takaaki Fuchikami, Kyoji Marumoto, Yoshikazu Fujimori
2015	C	`conf`	A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques. ISCAS Tomoki Nakagawa, Shintaro Izumi, Koji Yanagida, Yuki Kitahara, Shusuke Yoshimoto, Yohei Umeki, Haruki Mori, Hiroto Kitahara, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Masahiko Yoshimoto
2015	J	`jnl`	Normally Off ECG SoC With Non-Volatile MCU and Noise Tolerant Heartbeat Detector. IEEE Trans. Biomed. Circuits Syst. Shintaro Izumi, Ken Yamashita, Masanao Nakano, Shusuke Yoshimoto, Tomoki Nakagawa, Yozaburo Nakai, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto
2014	—	`conf`	A 2.4 pJ ferroelectric-based non-volatile flip-flop with 10-year data retention capability. A-SSCC Hiromitsu Kimura, Takaaki Fuchikami, Kyoji Marumoto, Yoshikazu Fujimori, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2014	—	`conf`	A 6.14µA normally-off ECG-SoC with noise tolerant heart rate extractor for wearable healthcare systems. BioCAS Shintaro Izumi, Ken Yamashita, Masanao Nakano, Tomoki Nakagawa, Yuki Kitahara, Koji Yanagida, Shusuke Yoshimoto, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto
2014	J	`jnl`	Highly Reliable Non-volatile Logic Circuit Technology and Its Application. IEICE Trans. Inf. Syst. Hiromitsu Kimura, Zhiyong Zhong, Yuta Mizuochi, Norihiro Kinouchi, Yoshinobu Ichida, Yoshikazu Fujimori
2013	—	`conf`	A 14 µA ECG processor with robust heart rate monitor for a wearable healthcare system. ESSCIRC Shintaro Izumi, Ken Yamashita, Masanao Nakano, Toshihiro Konishi, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto
2013	—	`conf`	A 38 μA wearable biosignal monitoring system with near field communication. NEWCAS Ken Yamashita, Shintaro Izumi, Masanao Nakano, Takahide Fujii, Toshihiro Konishi, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto
2013	—	`conf`	Highly Reliable Non-Volatile Logic Circuit Technology and Its Application. ISMVL Hiromitsu Kimura, Zhiyong Zhong, Yuta Mizuochi, Norihiro Kinouchi, Yoshinobu Ichida, Yoshikazu Fujimori
2007	—	`conf`	Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic. ASP-DAC Shoun Matsunaga, Takahiro Hanyu, Hiromitsu Kimura, Takashi Nakamura, Hidemi Takasu
2005	J	`jnl`	TMR-Based Logic-in-Memory Circuit for Low-Power VLSI. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Akira Mochizuki, Hiromitsu Kimura, Mitsuru Ibuki, Takahiro Hanyu
2004	—	`conf`	A Study of Multiple-Valued Magnetoresistive RAM (MRAM) Using Binary MTJ Devices. ISMVL Hiromitsu Kimura, Kostas Pagiamtzis, Ali Sheikholeslami, Takahiro Hanyu
2004	J	`jnl`	Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI. IEEE J. Solid State Circuits Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama, Yoshikazu Fujimori, Takashi Nakamura, Hidemi Takasu
2003	J	`jnl`	Multiple-Valued Logic-in-Memory VLSI Using MFSFETs and its Applications. J. Multiple Valued Log. Soft Comput. Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama
2002	—	`conf`	Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition. ISMVL Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama
2000	—	`conf`	DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage. ISMVL Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama
1999	—	`conf`	Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs. ISMVL Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama