Hiroki Yamashita

34 papers C 2Misc 1Journal 14Unranked 17

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Mapping the political landscape from data traces: multidimensional opinions of users, politicians and media outlets on X. CoRR Antoine Vendeville, Jimena Royo-Letelier, Duncan Cassells, Jean-Philippe Cointet, Maxime Crépel, Tim Faverjon, Théophile Lenoir, Béatrice Mazoyer, Benjamin Ooghe-Tabanou, Armin Pournaki, Hiroki Yamashita, Pedro Ramaciotti
2026	J	`jnl`	Political attitudes differ but share a common low-dimensional structure across social media and survey data. CoRR Antoine Vendeville, Hiroki Yamashita, Pedro Ramaciotti
2023	—	`conf`	Highly Scalable Metal Induced Lateral Crystallization (MILC) Techniques for Vertical Si Channel in Ultra-High (> 300 Layers) 3D Flash Memory. VLSI Technology and Circuits Noritaka Ishihara, Yusuke Shimada, Takamitsu Ochi, Satoshi Seto, Haruki Matsuo, Hiroki Yamashita, Sho Morita, Masafumi Ukishima, K. Uejima, Yusuke Arayashiki, Suzuka Kajiwara, Akiyuki Murayama, Katsuya Nishiyama, Kikuko Sugimae, Shinji Mori, Yuta Saito, Takeshi Shundo, Aki Maeda, Hiroyuki Kamiya, Yasuhiro Uchiyama, Makoto Fujiwara, Fumiki Aiso, Katsuyuki Sekine, Norio Ohtani
2020	—	`conf`	Approaching Behavior Analysis for Improving a Mobile Communication Robot in a Nursing Home. HCI (44) Misato Nihei, Mio Nakamura, Kohei Ikeda, Kazuki Kawamura, Hiroki Yamashita, Minoru Kamata
2018	J	`jnl`	25-Gbps 3-mW/Gbps/ch VCSEL Driver Circuit in 65-nm CMOS for Multichannel Optical Transmitter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Toru Yazaki, Norio Chujo, Takeshi Takemoto, Hiroki Yamashita, Akira Hyogo
2018	J	`jnl`	A 50-Gb/s High-Sensitivity (-9.2 dBm) Low-Power (7.9 pJ/bit) Optical Receiver Based on 0.18-µm SiGe BiCMOS Technology. IEEE J. Solid State Circuits Takashi Takemoto, Yasunobu Matsuoka, Hiroki Yamashita, Yong Lee, Hideo Arimoto, Masaru Kokubo, Tatemi Ido
2017	J	`jnl`	Low-light color image enhancement via iterative noise reduction using RGB/NIR sensor. J. Electronic Imaging Hiroki Yamashita, Daisuke Sugimura, Takayuki Hamamoto
2017	Misc	`conf`	RGB-NIR imaging with exposure bracketing for joint denoising and deblurring of low-light color images. ICASSP Hiroki Yamashita, Daisuke Sugimura, Takayuki Hamamoto
2016	J	`jnl`	A 50-Gb/s Optical Transmitter Based on a 25-Gb/s-Class DFB-LD and a 0.18-µm SiGe BiCMOS LD Driver. IEICE Trans. Electron. Takashi Takemoto, Yasunobu Matsuoka, Hiroki Yamashita, Takahiro Nakamura, Yong Lee, Hideo Arimoto, Tatemi Ido
2016	—	`conf`	A 50.6-Gb/s 7.8-mW/Gb/s -7.4-dBm sensitivity optical receiver based on 0.18-µm SiGe BiCMOS technology. VLSI Circuits Takashi Takemoto, Yasunobu Matsuoka, Hiroki Yamashita, Yong Lee, Kenichi Akita, Hideo Arimoto, Masaru Kokubo, Tatemi Ido
2016	—	`conf`	A jitter-reduction packaging structure for a 56-Gb/s NRZ modulated optical receiver. OFC Takashi Takemoto, Yasunobu Matsuoka, Hiroki Yamashita, Yong Lee, Kenichi Akita, Hideo Arimoto, Masaru Kokubo
2015	—	`conf`	A 50-Gb/s NRZ-modulated optical transmitter based on a DFB-LD and a 0.18-µm SiGe BiCMOS LD driver. OFC Takashi Takemoto, Yasunobu Matsuoka, Yoshikazu Sugiyama, Hidenori Yonezawa, Hiroki Yamashita, Koichiro Adachi, Takahiro Nakamura, Etsuko Nomoto, Kouji Nakahara, Hideo Arimoto, Kenichi Osada, Tatemi Ido
2015	—	`conf`	An electrical and optical concurrent design methodology for enlarging jitter margin of 25.8-Gb/s optical interconnects. CICC Takashi Takemoto, Hiroki Yamashita, Yasunobu Matsuoka, Yong Lee, Masaru Kokubo
2015	J	`jnl`	Enhancing Color Images of Extremely Low Light Scenes Based on RGB/NIR Images Acquisition With Different Exposure Times. IEEE Trans. Image Process. Daisuke Sugimura, Takuya Mikami, Hiroki Yamashita, Takayuki Hamamoto
2015	C	`conf`	Enhancing low-light color images using an RGB-NIR single sensor. VCIP Hiroki Yamashita, Daisuke Sugimura, Takayuki Hamamoto
2014	C	`conf`	25-Gbps×4 optical transmitter with adjustable asymmetric pre-emphasis in 65-nm CMOS. ISCAS Toru Yazaki, Norio Chujo, Hiroki Yamashita, Takashi Takemoto, Yong Lee, Yasunobu Matsuoka
2014	J	`jnl`	A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion. IEEE J. Solid State Circuits Takashi Takemoto, Hiroki Yamashita, Fumio Yuki, Noboru Masuda, Hidehiro Toyoda, Norio Chujo, Yong Lee, Shinji Tsuji, Shinji Nishimura
2014	J	`jnl`	A 25-to-28 Gb/s High-Sensitivity (-9.7 dBm) 65 nm CMOS Optical Receiver for Board-to-Board Interconnects. IEEE J. Solid State Circuits Takashi Takemoto, Hiroki Yamashita, Toru Yazaki, Norio Chujo, Yong Lee, Yasunobu Matsuoka
2013	—	`conf`	A 25-Gb/s × 4-Ch, 8 × 8 mm OFC/NFOEC Norio Chujo, Toru Yazaki, Toshiaki Takai, Daichi Kawamura, Yasunobu Matsuoka, Yong Lee, Toshiki Sugawara, Hiroki Yamashita, Takashi Takemoto, Yoshiaki Ishigami, Kinya Yamazaki, Yoshinori Sunaga, Naoki Matsushima
2013	—	`conf`	A 4× 25-to-28Gb/s 4.9mW/Gb/s -9.7dBm high-sensitivity optical receiver based on 65nm CMOS for board-to-board interconnects. ISSCC Takashi Takemoto, Hiroki Yamashita, Toru Yazaki, Norio Chujo, Yong Lee, Yasunobu Matsuoka
2013	—	`conf`	Compact and power-efficient 100-Gbps CMOS-based transceiver. OFC/NFOEC Takashi Takemoto, Hiroki Yamashita, Fumio Yuki, Shinji Tsuji, Yong Lee, Koichiro Adachi, Kazunori Shinoda, Yasunobu Matsuoka, Toshiki Sugawara, Shinji Nishimura, Norio Chujo, Masaaki Nido, Kazuhiko Kurata, Junji Baba, Yoshinori Watanabe, Naoya Ikeda
2013	—	`conf`	High-frequency circuit design for 25 Gb/s×4 optical transceiver. ASP-DAC Norio Chujo, Takashi Takemoto, Fumio Yuki, Hiroki Yamashita
2012	—	`conf`	A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS. VLSIC Takashi Takemoto, Hiroki Yamashita, Takehito Kamimura, Fumio Yuki, Noboru Masuda, Hidehiro Toyoda, Norio Chujo, Kenji Kogo, Yong Lee, Shinji Tsuji, Shinji Nishimura
2011	—	`conf`	10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link. ISSCC Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Akihiro Kambe, Tatsuya Saito, Shinji Nishimura
2011	J	`jnl`	A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link. IEEE J. Solid State Circuits Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Masashi Kono, Akihiro Kambe, Seiichi Umai, Tatsuya Saito, Shinji Nishimura
2010	J	`jnl`	A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process. IEEE J. Solid State Circuits Koji Fukuda, Hiroki Yamashita, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Noboru Masuda, Takashi Takemoto, Fumio Yuki, Tatsuya Saito
2010	—	`conf`	A 12.3mW 12.5Gb/s complete transceiver in 65nm CMOS. ISSCC Koji Fukuda, Hiroki Yamashita, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Tatsuya Saito
2010	—	`conf`	A 25 Gb/s × 4-channel 74 mW/ch transimpedance amplifier in 65 nm CMOS. CICC Takashi Takemoto, Fumio Yuki, Hiroki Yamashita, Shinji Tsuji, Tatsuya Saito, Shinji Nishimura
2009	—	`conf`	10Gb/s receiver with track-and-hold-type linear phase detector and charge-redistribution 1 ISSCC Koji Fukuda, Hiroki Yamashita, Fumio Yuki, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Tatsuya Saito
2009	J	`jnl`	A 10-Gb/s Receiver With Track-and-Hold-Type Linear Phase Detector and Charge-Redistribution First-Order ΔΣ Modulator in 90-nm CMOS. IEEE J. Solid State Circuits Koji Fukuda, Hiroki Yamashita, Fumio Yuki, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Masashi Kono, Tatsuya Saito
2008	—	`conf`	An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane. ISSCC Koji Fukuda, Hiroki Yamashita, Fumio Yuki, Masayoshi Yagyu, Ryo Nemoto, Takashi Takemoto, Tatsuya Saito, Norio Chujo, Keiichi Yamamoto, Hisaaki Kanai, Atsuhiro Hayashi
2006	J	`jnl`	A Low-Power Write Driver for Hard Disk Drives. IEICE Trans. Electron. Tatsuya Kawashimo, Hiroki Yamashita, Masayoshi Yagyu, Fumio Yuki
2005	—	`conf`	A 1.2Gb/s write driver with pre-emphasis overshoot control optimized for high density HDD applications. CICC Y. Hayashi, Masahito Sonehara, S. Ueno, Y. Ito, Akio Koyama, Hiroki Yamashita
2004	J	`jnl`	A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface with digital eye-tracking. IEEE J. Solid State Circuits Yoshio Miki, Tatsuya Saito, Hiroki Yamashita, Fumio Yuki, Takashige Baba, Akio Koyama, Masahito Sonehara