Hiroki Noguchi

41 papers A 2B 2C 5Misc 1Journal 15Unranked 16
YearRankTypeTitle / Venue / Authors
2024 — conf
15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 10
ISSCC
Ku-Feng Lin, Hiroki Noguchi, Yi-Chun Shih, Perng-Fei Yuh, Yuan-Jen Lee, Tung-Cheng Chang, Sheng-Po Huang, Yu-Fan Lin, Chun-Ying Lee, Yen-Hsiang Huang, Jui-Che Tsai, Saman Adham, Peter Noel, Ramin Yazdi, Marat Gershoig, YangJae Shin, Vineet Joshi, Ted Wong, Meng-Ru Jiang, J. J. Wu, Chun-Tai Cheng, Yu-Jen Wang, Harry Chuang, Yu-Der Chih, Yih Wang, Tsung-Yung Jonathan Chang
2024 J jnl
Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaoyu Sun, Weidong Cao, Brian Crafton, Kerem Akarvardar, Haruki Mori, Hidehiro Fujiwara, Hiroki Noguchi, Yu-Der Chih, Meng-Fan Chang, Yih Wang, Tsung-Yung Jonathan Chang
2022 C conf
RoboCup2022 KidSize League Winner CIT Brains: Open Platform Hardware SUSTAINA-OP and Software.
RoboCup
Yasuo Hayashibara, Masato Kubotera, Hayato Kambe, Gaku Kuwano, Dan Sato, Hiroki Noguchi, Riku Yokoo, Satoshi Inoue, Yuta Mibuchi, Kiyoshi Irie
2020 J jnl
Network theory-based accident scenario analysis for hazardous material transport: A case study of liquefied petroleum gas transport in japan.
Reliab. Eng. Syst. Saf.
Hiroki Noguchi, Shunichi Hienuki, Masaaki Fuse
2017 — conf
Novel memory hierarchy with e-STT-MRAM for near-future applications.
VLSI-DAT
Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe
2016 — conf
7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.
ISSCC
Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura
2015 — conf
7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture.
ISSCC
Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Naoharu Shimomura, Junichi Ito, Atsushi Kawasumi, Hiroyuki Hara, Shinobu Fujita
2015 C conf
Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches.
ICCD
Eishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Susumu Takeda, Shinobu Fujita, Hiroshi Nakamura
2014 — conf
Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU.
VLSIC
Hiroki Noguchi, Kazutaka Ikegami, Naoharu Shimomura, Tetsufumi Tanamoto, Junichi Ito, Shinobu Fujita
2014 — conf
Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures.
ISIC
Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe
2014 — conf
Novel nonvolatile memory hierarchies to realize "normally-off mobile processors".
ASP-DAC
Shinobu Fujita, Kumiko Nomura, Hiroki Noguchi, Susumu Takeda, Keiko Abe
2013 — conf
A 40-nm 144-mW VLSI processor for real-time 60-kWord continuous speech recognition.
ASP-DAC
Guangji He, Takanobu Sugahara, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013 A conf
D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory.
DATE
Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura
2012 J jnl
A 40 nm 144 mW VLSI Processor for Real-Time 60-kWord Continuous Speech Recognition.
IEEE Trans. Circuits Syst. I Regul. Pap.
Guangji He, Takanobu Sugahara, Yuki Miyamoto, Tsuyoshi Fujinaga, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011 — conf
0.45-V operating Vt-variation tolerant 9T/18T dual-port SRAM.
ISQED
Hiroki Noguchi, Shunsuke Okumura, Tomoya Takagi, Koji Kugata, Masahiko Yoshimoto, Hiroshi Kawaguchi
2011 — conf
A 40 nm 144 mW VLSI processor for realtime 60 kWord continuous speech recognition.
CICC
Guangji He, Takanobu Sugahara, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011 J jnl
A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition.
IEICE Trans. Electron.
Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Tsuyoshi Fujinaga, Shintaro Izumi, Yasuo Ariki, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011 B conf
Data Aggregation Protocol for Multiple Sound Sources Acquisition with Microphone Array Network.
ICCCN
Shintaro Izumi, Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shinpei Soda, Masahiko Yoshimoto, Hiroshi Kawaguchi
2011 J jnl
Data-Intensive Sound Acquisition System with Large-scale Microphone Array.
Inf. Media Technol.
Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2011 J jnl
Data-Intensive Sound Acquisition System with Large-scale Microphone Array.
J. Inf. Process.
Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2011 J jnl
Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential.
Inf. Media Technol.
Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011 J jnl
Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential.
IPSJ Trans. Syst. LSI Des. Methodol.
Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011 J jnl
VLSI Architecture of GMM Processing and Viterbi Decoder for 60, 000-Word Real-Time Continuous Speech Recognition.
IEICE Trans. Electron.
Hiroki Noguchi, Kazuo Miura, Tsuyoshi Fujinaga, Takanobu Sugahara, Hiroshi Kawaguchi, Masahiko Yoshimoto
2010 — conf
A 34.7-mW quad-core MIQP solver processor for robot control.
CICC
Hiroki Noguchi, Junichi Tani, Yusuke Shimai, Masanori Nishino, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2010 B conf
Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video.
FPL
Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto
2010 C conf
Intelligent ubiquitous sensor network for sound acquisition.
ISCAS
Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2010 C conf
Live demonstration: Intelligent ubiquitous sensor network for sound acquisition.
ISCAS
Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2010 C conf
Parallel-processing VLSI architecture for mixed integer linear programming.
ISCAS
Hiroki Noguchi, Junichi Tani, Yusuke Shimai, Hiroshi Kawaguchi, Masahiko Yoshimoto
2009 — conf
A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme.
ISQED
Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2009 Misc conf
A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection.
VLSI Design
Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2009 J jnl
A Dependable SRAM with 7T/14T Memory Cells.
IEICE Trans. Electron.
Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2009 — conf
An ultra-low-power VAD hardware implementation for intelligent ubiquitous sensor networks.
SiPS
Hiroki Noguchi, Tomoya Takagi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2009 A conf
Parallelized viterbi processor for 5, 000-word large-vocabulary real-time continuous speech recognition FPGA system.
INTERSPEECH
Tsuyoshi Fujinaga, Kazuo Miura, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2008 J jnl
A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing.
IEICE Trans. Electron.
Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2008 — conf
A low memory bandwidth Gaussian mixture model (GMM) processor for 20, 000-word real-time speech recognition FPGA system.
FPT
Kazuo Miura, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2008 J jnl
Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering.
IEEE Trans. Very Large Scale Integr. Syst.
Hidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto
2008 — conf
Quality of a Bit (QoB): A New Concept in Dependable SRAM.
ISQED
Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto
2007 — conf
A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing.
ISVLSI
Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2007 J jnl
Area Comparison between 6T and 8T SRAM Cells in Dual-
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2007 J jnl
Area Optimization in 6T and 8T SRAM Cells Considering
IEICE Trans. Electron.
Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2006 J jnl
A 0.3-V Operating,
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Kentaro Kawakami, Junichi Miyakoshi, Shinji Mikami, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto