Hiroki Nakahara

110 papers A 5B 10C 3Misc 3Journal 29Unranked 59

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A Novel Data Representation Towards Efficient FPGA-based Quantum Computer Simulation. ISMVL Haruhiko Hasegawa, Masayuki Shimoda, Hiroki Nakahara, Takefumi Miyoshi
2024	—	`conf`	A Stacked FPGA utilizing 3D-SRAM with Latency Optimization. MCSoC Ryo Takahashi, Kota Ando, Hiroki Nakahara
2024	—	`conf`	A Table Look-Up Based Quantum Simulation Accelerator on an FPGA. ICFPT Haruhiko Hasegawa, Masayuki Shimoda, Hiroki Nakahara, Takefumi Miyoshi
2024	—	`conf`	A Weight Ternary Ensemble Vision Transformer Toward Memory Size Reduction. ISMVL Ryota Kayanoma, Hiroki Nakahara
2023	—	`conf`	A Consideration on Ternary Adversarial Generative Networks. ISMVL Kennichi Nakamura, Hiroki Nakahara
2023	—	`conf`	A Light-Weight Vision Transformer Toward Near Memory Computation on an FPGA. ARC Takeshi Senoo, Ryota Kayanoma, Akira Jinguji, Hiroki Nakahara
2023	—	`conf`	A Many-core Architecture for an Ensemble Ternary Neural Network Toward High-Throughput Inference. MCSoC Ryota Kayanoma, Akira Jinguji, Hiroki Nakahara
2023	J	`jnl`	Remarn: A Reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks. ACM Trans. Reconfigurable Technol. Syst. Zhiqiang Que, Hiroki Nakahara, Hongxiang Fan, He Li, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi, Wayne Luk
2022	—	`conf`	Fast Interface with Ensemble Ternary Neural Network. ISMVL Ryota Kayanoma, Hiroki Nakahara
2022	—	`conf`	Message from the General Chair and Program Co-Chairs. FPT Wei Zhang, Ray C. C. Cheung, Yun Liang, Hiroki Nakahara
2022	J	`jnl`	Multilayer Perceptron Training Accelerator Using Systolic Array. IEICE Trans. Inf. Syst. Takeshi Senoo, Akira Jinguji, Ryosuke Kuramochi, Hiroki Nakahara
2022	—	`conf`	Optimizations of Ternary Generative Adversarial Networks. ISMVL Kennichi Nakamura, Hiroki Nakahara
2022	—	`conf`	Preface. FPT Yun Liang, Hiroki Nakahara, Wei Zhang, Fubing Mao, Ray C. C. Cheung
2022	J	`jnl`	Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Andrew Boutros, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Wayne Luk
2021	—	`conf`	A High-Throughput Detection Circuit based on 2 ISMVL Naoto Soga, Ryosuke Kuramochi, Hiroki Nakahara
2021	J	`jnl`	A Low-Latency Inference of Randomly Wired Convolutional Neural Networks on an FPGA. IEICE Trans. Inf. Syst. Ryosuke Kuramochi, Hiroki Nakahara
2021	—	`conf`	A Multilayer Perceptron Training Accelerator using Systolic Array. APCCAS Takeshi Senoo, Akira Jinguji, Ryosuke Kuramochi, Hiroki Nakahara
2021	J	`jnl`	A novel compact planar magic-T using CPS and microstrip-to-CPS transition. IEICE Electron. Express Hiroki Nakahara, Takayuki Tanaka, Ichihiko Toyoda
2021	—	`conf`	Detection of Wrong Direction Vehicles on Two-Way Traffic. KSE Pintusorn Suttiponpisarn, Chalermpol Charnsripinyo, Sasiporn Usanavasin, Hiroki Nakahara
2021	—	`conf`	Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner. HCS Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
2021	J	`jnl`	Energy-Efficient ECG Signals Outlier Detection Hardware Using a Sparse Robust Deep Autoencoder. IEICE Trans. Inf. Syst. Naoto Soga, Shimpei Sato, Hiroki Nakahara
2021	J	`jnl`	FPGA-Based Inter-layer Pipelined Accelerators for Filter-Wise Weight-Balanced Sparse Fully Convolutional Networks with Overlapped Tiling. J. Signal Process. Syst. Masayuki Shimoda, Youki Sada, Hiroki Nakahara
2021	J	`jnl`	Weight Sparseness for a Feature-Map-Split-CNN Toward Low-Cost Embedded FPGAs. IEICE Trans. Inf. Syst. Akira Jinguji, Shimpei Sato, Hiroki Nakahara
2020	—	`conf`	2 ISMVL Hiroki Nakahara
2020	—	`conf`	A Reconfigurable Multithreaded Accelerator for Recurrent Neural Networks. FPT Zhiqiang Que, Hiroki Nakahara, Hongxiang Fan, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi, Wayne Luk
2020	—	`conf`	A Table Look-Up Based Ternary Neural Network Processor. ISMVL Yuta Suzuki, Naoto Soga, Shimpei Sato, Hiroki Nakahara
2020	B	`conf`	An FPGA-Based Low-Latency Accelerator for Randomly Wired Neural Networks. FPL Ryosuke Kuramochi, Hiroki Nakahara
2020	—	`conf`	Design Method for an LUT Network-Based CNN with a Sparse Local Convolution. FPT Naoto Soga, Hiroki Nakahara
2020	—	`conf`	Fast Monocular Depth Estimation on an FPGA. IPDPS Workshops Youki Sada, Naoto Soga, Masayuki Shimoda, Akira Jinguji, Shimpei Sato, Hiroki Nakahara
2020	Misc	`conf`	High-Throughput Convolutional Neural Network on an FPGA by Customized JPEG Compression. FCCM Hiroki Nakahara, Zhiqiang Que, Wayne Luk
2020	Misc	`conf`	Optimizing Reconfigurable Recurrent Neural Networks. FCCM Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Xinyu Niu, Wayne Luk
2020	A	`conf`	R2CNN: Recurrent Residual Convolutional Neural Network on FPGA. FPGA Hiroki Nakahara, Zhiqiang Que, Akira Jinguji, Wayne Luk
2020	J	`jnl`	SENTEI: Filter-Wise Pruning with Distillation towards Efficient Sparse Convolutional Neural Network Accelerators. IEICE Trans. Inf. Syst. Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Shimpei Sato, Hiroki Nakahara
2020	Misc	`conf`	Tiny On-Chip Memory Realization of Weight Sparseness Split-CNNs on Low-end FPGAs. FCCM Akira Jinguji, Shimpei Sato, Hiroki Nakahara
2019	—	`conf`	A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGA. FPT Youki Sada, Masayuki Shimoda, Akira Jinguji, Hiroki Nakahara
2019	B	`conf`	An FPGA Implementation of Real-Time Object Detection with a Thermal Camera. FPL Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Hiroki Nakahara
2019	A	`conf`	An FPGA-based Fine Tuning Accelerator for a Sparse CNN. FPGA Hiroki Nakahara, Akira Jinguji, Masayuki Shimoda, Shimpei Sato
2019	B	`conf`	FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network. FPL Hiroki Nakahara, Youki Sada, Masayuki Shimoda, Kouki Sayama, Akira Jinguji, Shimpei Sato
2019	—	`conf`	FPGA-based Accurate Pedestrian Detection with Thermal Camera for Surveillance System. ReConFig Ryosuke Kuramochi, Masayuki Shimoda, Youki Sada, Shimpei Sato, Hiroki Nakahara
2019	—	`conf`	Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation. ARC Masayuki Shimoda, Youki Sada, Hiroki Nakahara
2019	J	`jnl`	GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers. IEICE Trans. Inf. Syst. Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Shimpei Sato
2019	—	`conf`	Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks. MCSoC Ryosuke Kuramochi, Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
2019	—	`conf`	Noise Convolutional Neural Networks and FPGA Implementation. ISMVL Atsuki Munakata, Hiroki Nakahara, Shimpei Sato
2019	J	`jnl`	Power Efficient Object Detector with an Event-Driven Camera for Moving Object Surveillance on an FPGA. IEICE Trans. Inf. Syst. Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
2019	B	`conf`	Real-Time Multi-Pedestrian Detection in Surveillance Camera using FPGA. FPL Akira Jinguji, Youki Sada, Hiroki Nakahara
2018	B	`conf`	A Demonstration of FPGA-Based You Only Look Once Version2 (YOLOv2). FPL Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato
2018	C	`conf`	A High-speed Low-power Deep Neural Network on an FPGA based on the Nested RNS: Applied to an Object Detector. ISCAS Hiroki Nakahara, Tsutomu Sasao
2018	A	`conf`	A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA. FPGA Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Shimpei Sato
2018	—	`conf`	A Performance Per Power Efficient Object Detector on an FPGA for Robot Operating System (ROS). HEART Haoxuan Cheng, Shimpei Sato, Hiroki Nakahara
2018	—	`conf`	A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor. ISMVL Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara
2018	J	`jnl`	A Threshold Neuron Pruning for a Binarized Deep Neural Network on an FPGA. IEICE Trans. Inf. Syst. Tomoya Fujii, Shimpei Sato, Hiroki Nakahara
2018	—	`conf`	A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector. FPT Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato
2018	—	`conf`	An FPGA Realization of OpenPose Based on a Sparse Weight Convolutional Neural Network. FPT Akira Jinguji, Tomoya Fujii, Shimpei Sato, Hiroki Nakahara
2018	J	`jnl`	An FPGA Realization of a Random Forest with IEICE Trans. Inf. Syst. Akira Jinguji, Shimpei Sato, Hiroki Nakahara
2018	J	`jnl`	BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. IEEE J. Solid State Circuits Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura
2018	B	`conf`	Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUs. FPL Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
2018	—	`ch.`	Hardware Algorithms. Principles and Structures of FPGAs Kentaro Sano, Hiroki Nakahara
2018	—	`conf`	New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications. VLSI Circuits Taro Fujii, Takao Toi, Teruhito Tanaka, Katsumi Togawa, Toshiro Kitaoka, Kengo Nishino, Noritsugu Nakamura, Hiroki Nakahara, Masato Motomura
2018	—	`conf`	Power Efficient Object Detector with an Event-Driven Camera on an FPGA. HEART Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
2017	A	`conf`	A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only). FPGA Hiroki Nakahara, Haruyoshi Yonekawa, Hisashi Iwamoto, Masato Motomura
2017	—	`conf`	A Random Forest Using a Multi-valued Decision Diagram on an FPGA. ISMVL Hiroki Nakahara, Akira Jinguji, Simpei Sato, Tsutomu Sasao
2017	B	`conf`	A fully connected layer elimination for a binarizec convolutional neural network on an FPGA. FPL Hiroki Nakahara, Tomoya Fujii, Shimpei Sato
2017	—	`conf`	All binarized convolutional neural network and its implementation on an FPGA. FPT Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
2017	—	`conf`	An FPGA Realization of a Deep Convolutional Neural Network Using a Threshold Neuron Pruning. ARC Tomoya Fujii, Simpei Sato, Hiroki Nakahara, Masato Motomura
2017	—	`conf`	An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA. FPT Hiroki Nakahara, Haruyoshi Yonekawa, Shimpei Sato
2017	—	`conf`	In-memory area-efficient signal streaming processor design for binary neural networks. MWSCAS Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
2017	—	`conf`	On-Chip Memory Based Binarized Convolutional Deep Neural Network Applying Batch Normalization Free Technique on an FPGA. IPDPS Workshops Haruyoshi Yonekawa, Hiroki Nakahara
2016	—	`conf`	A memory-based realization of a binarized deep convolutional neural network. FPT Hiroki Nakahara, Haruyoshi Yonekawa, Tsutomu Sasao, Hisashi Iwamoto, Masato Motomura
2016	—	`conf`	An FFT Circuit Using Nested RNS in a Digital Spectrometer for a Radio Telescope. ISMVL Hiroki Nakahara, Tsutomu Sasao, Hiroyuki Nakanishi, Kazumasa Iwai, Tohru Nagao, Naoya Ogawa
2016	J	`jnl`	An FFT Circuit for a Spectrometer of a Radio Telescope using the Nested RNS including the Constant Division. SIGARCH Comput. Archit. News Hiroki Nakahara, Hiroyuki Nakanishi, Kazumasa Iwai, Tsutomu Sasao
2016	J	`jnl`	An Update Method for a Low Power Cam Emulator Using an LUT Cascade Based on an EVMDD ( J. Multiple Valued Log. Soft Comput. Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Hisashi Iwamoto
2016	—	`conf`	An acceleration of a random forest classification using Altera SDK for OpenCL. FPT Hiroki Nakahara, Akira Jinguji, Tomonori Fujii, Simpei Sato
2016	J	`jnl`	LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification. IEEE J. Emerg. Sel. Topics Circuits Syst. Hiroki Nakahara, Tsutomu Sasao, Hisashi Iwamoto, Munehiro Matsuura
2015	—	`conf`	A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank. ARC Hiroki Nakahara, Hideki Yoshida, Shin-ich Shioya, Renji Mikami, Tsutomu Sasao
2015	J	`jnl`	A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units. IEICE Trans. Inf. Syst. Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Hisashi Iwamoto, Yasuhiro Terao
2015	B	`conf`	A deep convolutional neural network based on nested residue number system. FPL Hiroki Nakahara, Tsutomu Sasao
2015	—	`conf`	An RNS FFT Circuit Using LUT Cascades Based on a Modulo EVMDD. ISMVL Hiroki Nakahara, Tsutomu Sasao, Hiroyuki Nakanishi, Kazumasa Iwai
2014	J	`jnl`	A Heterogeneous Multi-valued Decision Diagram Machine for Encoded Characteristic Function for Non-zero Outputs. J. Multiple Valued Log. Soft Comput. Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2014	J	`jnl`	A Packet Classifier Based on Prefetching EVMDD ( IEICE Trans. Inf. Syst. Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2014	—	`conf`	An AWF digital spectrometer for a radio telescope. ReConFig Hiroki Nakahara, Hiroyuki Nakanishi, Kazumasa Iwai
2014	—	`conf`	An Update Method for a CAM Emulator Using an LUT Cascade Based on an EVMDD (K). ISMVL Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2014	—	`conf`	Automatic adjustment system for optical interconnection transmitter using improved particle swarm optimization. ISIC Kenichi Ohhata, Hiroki Nakahara, Takuya Inoue, Toru Yazaki, Norio Chujo, Takuma Nishimoto
2013	—	`conf`	A Machine to Evaluate Decomposed Multi-Terminal Multi-Valued Decision Diagrams for Characteristic Functions. ISMVL Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2013	J	`jnl`	A Virus Scanning Engine Using an MPU and an IGU Based on Row-Shift Decomposition. IEICE Trans. Inf. Syst. Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2013	—	`conf`	A high-speed FFT based on a six-step algorithm: Applied to a radio telescope for a solar radio burst. FPT Hiroki Nakahara, Kazumasa Iwai, Hiroyuki Nakanishi
2013	B	`conf`	A packet classifier using LUT cascades based on EVMDDS (k). FPL Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2013	—	`conf`	An Architecture for IPv6 Lookup Using Parallel Index Generation Units. ARC Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2012	J	`jnl`	A Comparison of Multi-Valued and Heterogeneous Decision Diagram Machines. J. Multiple Valued Log. Soft Comput. Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2012	J	`jnl`	A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton. IEICE Trans. Inf. Syst. Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2012	—	`conf`	A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPU. ARC Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2012	J	`jnl`	A regular expression matching circuit: Decomposed non-deterministic realization with prefix sharing and multi-character transition. Microprocess. Microsystems Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2012	—	`conf`	Multi-terminal Multi-valued Decision Diagrams for Characteristic Function Representing Cluster Decomposition. ISMVL Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2012	—	`conf`	On a Wideband Fast Fourier Transform Using Piecewise Linear Approximations: Application to a Radio Telescope Spectrometer. ICA3PP (1) Hiroki Nakahara, Hiroyuki Nakanishi, Tsutomu Sasao
2012	J	`jnl`	On a wideband fast fourier transform for a radio telescope. SIGARCH Comput. Archit. News Hiroki Nakahara, Hiroyuki Nakanishi, Tsutomu Sasao
2011	—	`conf`	A Comparison of Heterogeneous Multi-valued Decision Diagram Machines for Multiple-Output Logic Functions. ISMVL Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2011	—	`conf`	A Regular Expression Matching Circuit Based on a Decomposed Automaton. ARC Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2010	—	`conf`	A Comparison of Architectures for Various Decision Diagram Machines. ISMVL Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2010	C	`conf`	A Packet Classifier Using a Parallel Branching Program Machine. DSD Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2010	J	`jnl`	A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation. IEICE Trans. Inf. Syst. Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura
2010	J	`jnl`	A Quaternary Decision Diagram Machine: Optimization of Its Code. IEICE Trans. Inf. Syst. Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler
2009	—	`conf`	A Parallel Branching Program Machine for Emulation of Sequential Circuits. ARC Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura
2009	—	`conf`	A Quaternary Decision Diagram Machine and the Optimization of its Code. ISMVL Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler
2009	B	`conf`	A virus scanning engine using a parallel finite-input memory machine and MPUs. FPL Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura
2009	C	`conf`	The Parallel Sieve Method for a Virus Scanning Engine. DSD Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura
2007	A	`conf`	A CAM Emulator Using Look-Up Table Cascades. IPDPS Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2007	—	`conf`	Implementations of Reconfigurable Logic Arrays on FPGAs. FPT Tsutomu Sasao, Hiroki Nakahara
2006	J	`jnl`	A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2006	—	`conf`	A Soft Error Tolerant LUT Cascade Emulator. ATS Hiroki Nakahara, Tsutomu Sasao
2006	—	`conf`	A fast logic simulator using a look up table cascade emulator. ASP-DAC Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2005	J	`jnl`	A Design Algorithm for Sequential Circuits Using LUT Rings. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura