Hiroki Morimura

28 papers A 2C 1Misc 1Journal 15Unranked 9
YearRankTypeTitle / Venue / Authors
2019 J jnl
A 0.90-4.39-V Detection Voltage Range, 56-Level Programmable Voltage Detector Using Fine Voltage-Step Subtraction for Battery Management.
IEEE Trans. Circuits Syst. I Regul. Pap.
Teruki Someya, Kenichi Matsunaga, Hiroki Morimura, Takayasu Sakurai, Makoto Takamiya
2017 J jnl
Analysis and Experimental Study of Magnetic-Field Amplification by a Double Coil.
IEEE Trans. Ind. Electron.
Ai-ichiro Sasaki, Olivier Ouellette, Maxime Beaudry-Marchand, Akihiko Hirata, Hiroki Morimura
2017 J jnl
Design and Analysis of Ultra-Low Power Glitch-Free Programmable Voltage Detector Based on Multiple Voltage Copier.
IEICE Trans. Electron.
Teruki Someya, Hiroshi Fuketa, Kenichi Matsunaga, Hiroki Morimura, Takayasu Sakurai, Makoto Takamiya
2016 — conf
56-Level programmable voltage detector in steps of 50mV for battery management.
A-SSCC
Teruki Someya, Kenichi Matsunaga, Hiroki Morimura, Takayasu Sakurai, Makoto Takamiya
2015 — conf
248pW, 0.11mV/°C glitch-free programmable voltage detector with multiple voltage duplicator for energy harvesting.
ESSCIRC
Teruki Someya, Hiroshi Fuketa, Kenichi Matsunaga, Hiroki Morimura, Takayasu Sakurai, Makoto Takamiya
2015 C conf
A Wide Frequency PLL-less Clock Generator with Fast Intermittent Operation for Low-Power Wearable Medical Applications.
APCC
Ahmed Musa, Tadashi Minotani, Toshihiko Kondo, Hiroki Morimura
2015 — conf
An 8-mode reconfigurable sensor-independent readout circuit for trillion sensors era.
ISSNIP
Ahmed Musa, Tadashi Minotani, Kenichi Matsunaga, Toshihiko Kondo, Hiroki Morimura
2015 — conf
Analysis to optimize sensitivity of RF energy harvester with voltage boost circuit.
ECCTD
Dan Luo, Hiroshi Fuketa, Kenichi Matsunaga, Hiroki Morimura, Makoto Takamiya, Takayasu Sakurai
2014 J jnl
Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage.
IEEE Trans. Very Large Scale Integr. Syst.
Shunji Nakata, Hiroki Hanazono, Hiroshi Makino, Hiroki Morimura, Masayuki Miyama, Yoshio Matsuda
2014 J jnl
Ultra-low-power circuit techniques for mm-size wireless sensor nodes with energy harvesting.
IEICE Electron. Express
Hiroki Morimura, Shoichi Oshima, Kenichi Matsunaga, Toshishige Shimamura, Mitsuru Harada
2012 Misc conf
1-cm
ICCS
Shoichi Oshima, Kenichi Matsunaga, Toshishige Shimamura, Hiroki Morimura, Mitsuru Harada
2012 — conf
Energy dissipation reduction during adiabatic charging and discharging with controlled inductor current.
MWSCAS
Shunji Nakata, Ryota Honda, Hiroshi Makino, Hiroki Morimura, Yoshio Matsuda
2010 J jnl
Capacitive-Sensing Circuit Technique for Image Quality Improvement on Fingerprint Sensor LSIs.
IEEE J. Solid State Circuits
Toshishige Shimamura, Hiroki Morimura, Satoshi Shigematsu, Mamoru Nakanishi, Katsuyuki Machida
2010 — conf
Nano-watt power management and vibration sensing on a dust-size batteryless sensor node for ambient intelligence applications.
ISSCC
Toshishige Shimamura, Mamoru Ugajin, Kenji Suzuki, Kazuyoshi Ono, Norio Sato, Kei Kuwabara, Hiroki Morimura, Shin'ichiro Mutoh
2008 — conf
A Fingerprint Sensor with Impedance Sensing for Fraud Detection.
ISSCC
Toshishige Shimamura, Hiroki Morimura, Nobuhiro Shimoyama, Tomomi Sakata, Satoshi Shigematsu, Katsuyuki Machida, Mamoru Nakanishi
2007 J jnl
Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI.
IEICE Trans. Electron.
Satoshi Shigematsu, Hiroki Morimura, Toshishige Shimamura, Takahiro Hatano, Namiko Ikeda, Yukio Okazaki, Katsuyuki Machida, Mamoru Nakanishi
2006 J jnl
Fingerprint Image Enhancement and Rotation Schemes for a Single-Chip Fingerprint Sensor and Identifier.
IEICE Trans. Electron.
Satoshi Shigematsu, Koji Fujii, Hiroki Morimura, Takahiro Hatano, Mamoru Nakanishi, Namiko Ikeda, Toshishige Shimamura, Katsuyuki Machida, Yukio Okazaki, Hakaru Kyuragi
2005 J jnl
Pixel-Parallel Image-Matching Circuit Schemes for a Single-Chip Fingerprint Sensor and Identifier.
IEICE Trans. Electron.
Satoshi Shigematsu, Hiroki Morimura, Katsuyuki Machida, Yukio Okazaki, Hakaru Kyuragi
2002 — conf
A 500-dpi cellular-logic processing array for fingerprint-image enhancement and verification.
CICC
Koji Fujii, Mamoru Nakanishi, Satoshi Shigematsu, Hiroki Morimura, Takahiro Hatano, Namiko Ikeda, Toshishige Shimamura, Yukio Okazaki, Hakaru Kyuragi
2002 — conf
A Fingerprint Verification Algorithm Using the Differential Matching Rate.
ICPR (3)
Takahiro Hatano, Takuya Adachi, Satoshi Shigematsu, Hiroki Morimura, Shigehiko Onishi, Yukio Okazaki, Hakaru Kyuragi
2002 J jnl
A pixel-level automatic calibration circuit scheme for capacitive fingerprint sensor LSIs.
IEEE J. Solid State Circuits
Hiroki Morimura, Satoshi Shigematsu, Toshishige Shimamura, Katsuyuki Machida, Hakaru Kyuragi
2000 J jnl
1-V 100-MHz embedded SRAM techniques for battery-operated MTCMOS/SIMOX ASICs.
IEEE J. Solid State Circuits
Nobutaro Shibata, Hiroki Morimura, Mitsuru Harada
2000 J jnl
A novel sensor cell architecture and sensing circuit scheme for capacitive fingerprint sensors.
IEEE J. Solid State Circuits
Hiroki Morimura, Satoshi Shigematsu, Katsuyuki Machida
1999 J jnl
A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with charge-recycling input/output buffers.
IEEE J. Solid State Circuits
Nobutaro Shibata, Hiroki Morimura, Mayumi Watanabe
1999 A conf
A shared-bitline SRAM cell architecture for 1-V ultra low-power word-bit configurable macrocells.
ISLPED
Hiroki Morimura, Satoshi Shigematsu, Shinsuke Konaka
1999 J jnl
A single-chip fingerprint sensor and identifier.
IEEE J. Solid State Circuits
Satoshi Shigematsu, Hiroki Morimura, Yasuyuki Tanabe, Takuya Adachi, Katsuyuki Machida
1998 J jnl
A step-down boosted-wordline scheme for 1-V battery-operated fast SRAM's.
IEEE J. Solid State Circuits
Hiroki Morimura, Nobutaro Shibata
1996 A conf
A 1-V 1-Mb SRAM for portable equipment.
ISLPED
Hiroki Morimura, Nobutaro Shibata