Hiroki Matsutani

210 papers A* 6A 5B 12C 13Misc 6Journal 78Unranked 87

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	Accelerating Local LLMs on Resource-Constrained Edge Devices via Distributed Prompt Caching. EuroMLSys@EuroSys Hiroki Matsutani, Naoki Matsuda, Naoto Sugiura
2026	J	`jnl`	Accelerating Local LLMs on Resource-Constrained Edge Devices via Distributed Prompt Caching. CoRR Hiroki Matsutani, Naoki Matsuda, Naoto Sugiura
2025	J	`jnl`	ElasticZO: A Memory-Efficient On-Device Learning with Combined Zeroth- and First-Order Optimization. CoRR Keisuke Sugiura, Hiroki Matsutani
2025	J	`jnl`	FPGA-accelerated Correspondence-free Point Cloud Registration with PointNet Features. ACM Trans. Reconfigurable Technol. Syst. Keisuke Sugiura, Hiroki Matsutani
2025	J	`jnl`	InstantFT: An FPGA-Based Runtime Subsecond Fine-tuning of CNN Models. CoRR Keisuke Sugiura, Hiroki Matsutani
2025	J	`jnl`	Performance and Power-Efficiency Improvements on Graph Embedding Using Sequential Training Algorithm and FPGA. IEICE Trans. Inf. Syst. Kazuki Sunaga, Keisuke Sugiura, Hiroki Matsutani
2025	J	`jnl`	PointODE: Lightweight Point Cloud Learning with Neural Ordinary Differential Equations on Edge. CoRR Keisuke Sugiura, Mizuki Yasuda, Hiroki Matsutani
2025	—	`conf`	Skip2-LoRA: A Lightweight On-device DNN Fine-tuning Method for Low-cost Edge Devices. ASP-DAC Hiroki Matsutani, Masaaki Kondo, Kazuki Sunaga, Radu Marculescu
2024	J	`jnl`	A Cost-Efficient FPGA Implementation of Tiny Transformer Model using Neural ODE. CoRR Ikumi Okubo, Keisuke Sugiura, Hiroki Matsutani
2024	J	`jnl`	A Cost-Efficient FPGA-Based CNN-Transformer Using Neural ODE. IEEE Access Ikumi Okubo, Keisuke Sugiura, Hiroki Matsutani
2024	—	`conf`	A Scalable Secure Fault Tolerant Aggregation for P2P Federated Learning. IPDPS (Workshops) Yujiro Yahata, Keisuke Sugiura, Hiroki Matsutani
2024	J	`jnl`	A Sequential Approach to Detect Drifts and Retrain Neural Networks on Resource-Limited Edge Devices. IEICE Trans. Inf. Syst. Kazuki Sunaga, Takeya Yamada, Hiroki Matsutani
2024	C	`conf`	A Tiny Supervised ODL Core with Auto Data Pruning for Human Activity Recognition. BSN Hiroki Matsutani, Radu Marculescu
2024	J	`jnl`	A Tiny Supervised ODL Core with Auto Data Pruning for Human Activity Recognition. CoRR Hiroki Matsutani, Radu Marculescu
2024	J	`jnl`	An Efficient Distributed Reinforcement Learning Architecture for Long-Haul Communication Between Actors and Learner. IEEE Access Shin Morishima, Hiroki Matsutani
2024	—	`conf`	An FPGA-Based Accelerator for Graph Embedding using Sequential Training Algorithm. IPDPS (Workshops) Kazuki Sunaga, Keisuke Sugiura, Hiroki Matsutani
2024	J	`jnl`	An Integrated FPGA Accelerator for Deep Learning-Based 2D/3D Path Planning. IEEE Trans. Computers Keisuke Sugiura, Hiroki Matsutani
2024	J	`jnl`	Data Poisoning Attack against Neural Network-Based On-Device Learning Anomaly Detector by Physical Attacks on Sensors. Sensors Takahito Ino, Kota Yoshida, Hiroki Matsutani, Takeshi Fujino
2024	J	`jnl`	FPGA-Accelerated Correspondence-free Point Cloud Registration with PointNet Features. CoRR Keisuke Sugiura, Hiroki Matsutani
2024	J	`jnl`	Federated Learning of Neural ODE Models with Different Iteration Counts. IEICE Trans. Inf. Syst. Yuto Hoshino, Hiroki Kawakami, Hiroki Matsutani
2024	J	`jnl`	Skip2-LoRA: A Lightweight On-device DNN Fine-tuning Method for Low-cost Edge Devices. CoRR Hiroki Matsutani, Masaaki Kondo, Kazuki Sunaga, Radu Marculescu
2024	—	`conf`	The Case for Coherence Directories in Memory Cubes. MCSoC Yuki Kameyama, Naoya Niwa, Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2023	J	`jnl`	A Case for Offloading Federated Learning Server on Smart NIC. CoRR Naoki Shibahara, Michihiro Koibuchi, Hiroki Matsutani
2023	—	`conf`	A Lightweight Concept Drift Detection Method for On-Device Learning on Resource-Limited Edge Devices. IPDPS Workshops Takeya Yamada, Hiroki Matsutani
2023	J	`jnl`	A Lightweight Reinforcement Learning Based Packet Routing Method Using Online Sequential Learning. IEICE Trans. Inf. Syst. Kenji Nemoto, Hiroki Matsutani
2023	—	`conf`	A Lightweight Transformer Model using Neural ODE for FPGAs. IPDPS Workshops Ikumi Okubo, Keisuke Sugiura, Hiroki Kawakami, Hiroki Matsutani
2023	J	`jnl`	A Low-Cost Neural ODE with Depthwise Separable Convolution for Edge Domain Adaptation on FPGAs. IEICE Trans. Inf. Syst. Hiroki Kawakami, Hirohisa Watanabe, Keisuke Sugiura, Hiroki Matsutani
2023	J	`jnl`	Addressing the Gap Between Training Data and Deployed Environment by On-Device Learning. IEEE Micro Kazuki Sunaga, Masaaki Kondo, Hiroki Matsutani
2023	—	`conf`	An Edge-Server Partitioning Method for 3D LiDAR SLAM on FPGAs. IPDPS Workshops Mizuki Yasuda, Keisuke Sugiura, Ryuto Kojima, Hiroki Matsutani
2023	C	`conf`	An Efficient Accelerator for Deep Learning-based Point Cloud Registration on FPGAs. PDP Keisuke Sugiura, Hiroki Matsutani
2023	J	`jnl`	An FPGA-Based Accelerator for Graph Embedding using Sequential Training Algorithm. CoRR Kazuki Sunaga, Keisuke Sugiura, Hiroki Matsutani
2023	J	`jnl`	An Integrated FPGA Accelerator for Deep Learning-based 2D/3D Path Planning. CoRR Keisuke Sugiura, Hiroki Matsutani
2023	J	`jnl`	Designing low-diameter interconnection networks with multi-ported host-switch graphs. Concurr. Comput. Pract. Exp. Ryota Yasudo, Koji Nakano, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano
2023	—	`conf`	Performance Improvement of Federated Learning Server using Smart NIC. CANDARW Naoki Shibahara, Michihiro Koibuchi, Hiroki Matsutani
2022	—	`conf`	A Packet Routing using Lightweight Reinforcement Learning Based on Online Sequential Learning. CANDARW Kenji Nemoto, Hiroki Matsutani
2022	J	`jnl`	A Sequential Concept Drift Detection Method for On-Device Learning on Low-End Edge Devices. CoRR Takeya Yamada, Hiroki Matsutani
2022	J	`jnl`	A Universal LiDAR SLAM Accelerator System on Low-Cost FPGA. IEEE Access Keisuke Sugiura, Hiroki Matsutani
2022	J	`jnl`	A traffic-aware memory-cube network using bypassing. Microprocess. Microsystems Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi
2022	C	`conf`	Accelerating Distributed Deep Reinforcement Learning by In-Network Experience Sampling. PDP Masaki Furukawa, Hiroki Matsutani
2022	J	`jnl`	An Efficient Accelerator for Deep Learning-based Point Cloud Registration on FPGAs. CoRR Keisuke Sugiura, Hiroki Matsutani
2022	J	`jnl`	An Overflow/Underflow-Free Fixed-Point Bit-Width Optimization Method for OS-ELM Digital Circuit. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Mineto Tsukada, Hiroki Matsutani
2022	—	`conf`	Communication Size Reduction of Federated Learning based on Neural ODE Model. CANDARW Yuto Hoshino, Hiroki Kawakami, Hiroki Matsutani
2022	J	`jnl`	Communication Size Reduction of Federated Learning based on Neural ODE Model. CoRR Yuto Hoshino, Hiroki Kawakami, Hiroki Matsutani
2022	—	`conf`	Dynamic Routing Reconfiguration for Low-Latency and Deadlock-Free Interconnection Networks. CANDAR Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2022	—	`conf`	ONLAD-IDS: ONLAD-Based Intrusion Detection System Using SmartNIC. HPCC/DSS/SmartCity/DependSys Man Wu, Hiroki Matsutani, Masaaki Kondo
2022	J	`jnl`	On-Device Learning: A Neural Network Based Field-Trainable Edge AI. CoRR Hiroki Matsutani, Mineto Tsukada, Masaaki Kondo
2022	—	`conf`	P3Net: PointNet-based Path Planning on FPGA. FPT Keisuke Sugiura, Hiroki Matsutani
2022	C	`conf`	dsODENet: Neural ODE and Depthwise Separable Convolution for Domain Adaptation on FPGAs. PDP Hiroki Kawakami, Hirohisa Watanabe, Keisuke Sugiura, Hiroki Matsutani
2021	J	`jnl`	A DPDK-Based Acceleration Method for Experience Sampling of Distributed Reinforcement Learning. CoRR Masaki Furukawa, Hiroki Matsutani
2021	J	`jnl`	A Low-Cost Neural ODE with Depthwise Separable Convolution for Edge Domain Adaptation on FPGAs. CoRR Hiroki Kawakami, Hirohisa Watanabe, Keisuke Sugiura, Hiroki Matsutani
2021	—	`conf`	A unified accelerator design for LiDAR SLAM algorithms for low-end FPGAs. FPT Keisuke Sugiura, Hiroki Matsutani
2021	—	`conf`	Accelerating ODE-Based Neural Networks on Low-Cost FPGAs. IPDPS Workshops Hirohisa Watanabe, Hiroki Matsutani
2021	J	`jnl`	An Area-Efficient Recurrent Neural Network Core for Unsupervised Time-Series Anomaly Detection. IEICE Trans. Electron. Takuya Sakuma, Hiroki Matsutani
2021	J	`jnl`	An FPGA Acceleration and Optimization Techniques for 2D LiDAR SLAM Algorithm. IEICE Trans. Inf. Syst. Keisuke Sugiura, Hiroki Matsutani
2021	—	`conf`	An FPGA-Based On-Device Reinforcement Learning Approach using Online Sequential Learning. IPDPS Workshops Hirohisa Watanabe, Mineto Tsukada, Hiroki Matsutani
2021	J	`jnl`	An FPGA-Based Optimizer Design for Distributed Deep Learning with Multiple GPUs. IEICE Trans. Inf. Syst. Tomoya Itsubo, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani
2021	J	`jnl`	An In-Network Parameter Aggregation using DPDK for Multi-GPU Deep Learning. Int. J. Netw. Comput. Masaki Furukawa, Tomoya Itsubo, Hiroki Matsutani
2021	J	`jnl`	An On-Device Federated Learning Approach for Cooperative Model Update Between Edge Devices. IEEE Access Rei Ito, Mineto Tsukada, Hiroki Matsutani
2021	J	`jnl`	An Overflow/Underflow-Free Fixed-Point Bit-Width Optimization Method for OS-ELM Digital Circuit. CoRR Mineto Tsukada, Hiroki Matsutani
2021	—	`conf`	GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph. ACIT Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2021	C	`conf`	Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths. PDP Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi
2021	J	`jnl`	Particle Filter-based vs. Graph-based: SLAM Acceleration on Low-end FPGAs. CoRR Keisuke Sugiura, Hiroki Matsutani
2020	J	`jnl`	A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks. IEICE Trans. Inf. Syst. Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2020	J	`jnl`	A Neural Network-Based On-Device Learning Anomaly Detector for Edge Devices. IEEE Trans. Computers Mineto Tsukada, Masaaki Kondo, Hiroki Matsutani
2020	—	`conf`	A Selective Model Aggregation Approach in Federated Learning for Online Anomaly Detection. iThings/GreenCom/CPSCom/SmartData/Cybermatics Yang Qin, Hiroki Matsutani, Masaaki Kondo
2020	C	`conf`	Accelerating Deep Learning using Multiple GPUs and FPGA-Based 10GbE Switch. PDP Tomoya Itsubo, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani
2020	J	`jnl`	Accelerating ODE-Based Neural Networks on Low-Cost FPGAs. CoRR Hirohisa Watanabe, Hiroki Matsutani
2020	—	`conf`	An Area-Efficient Implementation of Recurrent Neural Network Core for Unsupervised Anomaly Detection. COOL CHIPS Takuya Sakuma, Hiroki Matsutani
2020	—	`conf`	An Edge Attribute-Wise Partitioning and Distributed Processing of R-GCN Using GPUs. Euro-Par Workshops Tokio Kibata, Mineto Tsukada, Hiroki Matsutani
2020	J	`jnl`	An FPGA Acceleration and Optimization Techniques for 2D LiDAR SLAM Algorithm. CoRR Keisuke Sugiura, Hiroki Matsutani
2020	J	`jnl`	An FPGA-Based On-Device Reinforcement Learning Approach using Online Sequential Learning. CoRR Hirohisa Watanabe, Mineto Tsukada, Hiroki Matsutani
2020	—	`conf`	An In-Network Parameter Aggregation using DPDK for Multi-GPU Deep Learning. CANDAR Masaki Furukawa, Tomoya Itsubo, Hiroki Matsutani
2020	J	`jnl`	An On-Device Federated Learning Approach for Cooperative Anomaly Detection. CoRR Rei Ito, Mineto Tsukada, Hiroki Matsutani
2020	—	`conf`	Fast Semi-Supervised Anomaly Detection of Drivers' Behavior using Online Sequential Extreme Learning Machine. ITSC Hiroki Oikawa, Tomoya Nishida, Ryuichi Sakamoto, Hiroki Matsutani, Masaaki Kondo
2020	J	`jnl`	In-GPU Cache for Acceleration of Anomaly Detection in Blockchain. IEICE Trans. Inf. Syst. Shin Morishima, Hiroki Matsutani
2020	—	`conf`	Layout-Oriented Low-Diameter Topology for HPC Interconnection Networks. CANDAR (Workshops) Ryuta Kawano, Hiroki Matsutani, Hideharu Amano
2020	J	`jnl`	Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks. IEICE Trans. Inf. Syst. Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2019	J	`jnl`	A Neural Network Based On-device Learning Anomaly Detector for Edge Devices. CoRR Mineto Tsukada, Masaaki Kondo, Hiroki Matsutani
2019	—	`conf`	An Adaptive Abnormal Behavior Detection using Online Sequential Learning. CSE/EUC Rei Ito, Mineto Tsukada, Masaaki Kondo, Hiroki Matsutani
2019	J	`jnl`	An FPGA-Based Change-Point Detection for 10Gbps Packet Stream. IEICE Trans. Inf. Syst. Takuma Iwata, Kohei Nakamura, Yuta Tokusashi, Hiroki Matsutani
2019	—	`conf`	Deadlock-Free Layered Routing for Infiniband Networks. CANDAR Workshops Ryuta Kawano, Hiroki Matsutani, Hideharu Amano
2019	J	`jnl`	Designing High-Performance Interconnection Networks with Host-Switch Graphs. IEEE Trans. Parallel Distributed Syst. Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano
2019	—	`conf`	Key-value Store Chip Design for Low Power Consumption. COOL CHIPS Yuta Tokusashi, Hiroki Matsutani, Hideharu Amano
2019	—	`conf`	Performance and Cost Evaluations of Online Sequential Learning and Unsupervised Anomaly Detection Core. COOL CHIPS Tomoya Itsubo, Mineto Tsukada, Hiroki Matsutani
2019	A*	`conf`	Sparse 3-D NoCs with Inductive Coupling. DAC Michihiro Koibuchi, Lambert T. Leong, Tomohiro Totoki, Naoya Niwa, Hiroki Matsutani, Hideharu Amano, Henri Casanova
2018	J	`jnl`	A Hardware-Based Caching System on FPGA NIC for Blockchain. IEICE Trans. Inf. Syst. Yuma Sakakibara, Shin Morishima, Kohei Nakamura, Hiroki Matsutani
2018	C	`conf`	Accelerating Blockchain Search of Full Nodes Using GPUs. PDP Shin Morishima, Hiroki Matsutani
2018	—	`conf`	Accelerating Blockchain Transfer System Using FPGA-Based NIC. ISPA/IUCC/BDCloud/SocialCom/SustainCom Yuma Sakakibara, Yuta Tokusashi, Shin Morishima, Hiroki Matsutani
2018	—	`conf`	Accelerating Online Change-Point Detection Algorithm Using 10 GbE FPGA NIC. Euro-Par Workshops Takuma Iwata, Kohei Nakamura, Yuta Tokusashi, Hiroki Matsutani
2018	—	`conf`	Acceleration of Anomaly Detection in Blockchain Using In-GPU Cache. ISPA/IUCC/BDCloud/SocialCom/SustainCom Shin Morishima, Hiroki Matsutani
2018	—	`conf`	Adaptive Body Bias Control Scheme for Ultra Low-Power Network-on-Chip Systems. MCSoC Akram Ben Ahmed, Hayate Okuhara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2018	—	`conf`	An Trace-Driven Performance Prediction Method for Exploring NoC Design Optimization. CANDAR Workshops Naoya Niwa, Tomohiro Totoki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2018	—	`conf`	AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation. NOCS Akram Ben Ahmed, Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2018	J	`jnl`	Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface. Int. J. Netw. Comput. Akio Nomura, Yusuke Matsushita, Junichiro Kadomoto, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano
2018	J	`jnl`	LaKe: An Energy Efficient, Low Latency, Accelerated Key-Value Store. CoRR Yuta Tokusashi, Hiroki Matsutani, Noa Zilberman
2018	—	`conf`	LaKe: The Power of In-Network Computing. ReConFig Yuta Tokusashi, Hiroki Matsutani, Noa Zilberman
2018	B	`conf`	Low-Reliable Low-Latency Networks Optimized for HPC Parallel Applications. NCA Truong Thao Nguyen, Hiroki Matsutani, Michihiro Koibuchi
2018	—	`conf`	MultiMQC: A Multilevel Message Queuing Cache Combining In-NIC and In-Kernel Memories. FPT Koya Mitsuzuka, Yuta Tokusashi, Hiroki Matsutani
2018	—	`conf`	Network Optimizations on Prediction Server with Multiple Predictors. ISPA/IUCC/BDCloud/SocialCom/SustainCom Kaho Okuyama, Yuta Tokusashi, Takuma Iwata, Mineto Tsukada, Kazumasa Kishiki, Hiroki Matsutani
2018	—	`conf`	OS-ELM-FPGA: An FPGA-Based Online Sequential Unsupervised Anomaly Detector. Euro-Par Workshops Mineto Tsukada, Masaaki Kondo, Hiroki Matsutani
2018	J	`jnl`	Proxy Responses by FPGA-Based Switch for MapReduce Stragglers. IEICE Trans. Inf. Syst. Koya Mitsuzuka, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani
2018	Misc	`conf`	Special session on bringing cores closer together: The wireless revolution in on-chip communication. VTS Terrence S. T. Mak, Hiroki Matsutani, Partha Pratim Pande
2018	—	`conf`	k-Optimized Path Routing for High-Throughput Data Center Networks. CANDAR Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano
2017	—	`conf`	3D Layout of Spidergon, Flattened Butterfly and Dragonfly on a Chip Stack with Inductive Coupling Through Chip Interface. ISPAN-FCST-ISCC Hiroshi Nakahara, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi
2017	—	`conf`	A Case for Remote GPUs over 10GbE Network for VR Applications. HEART Shin Morishima, Masahiro Okazaki, Hiroki Matsutani
2017	C	`conf`	A Case for Uni-directional Network Topologies in Large-Scale Clusters. CLUSTER Michihiro Koibuchi, Tomohiro Totoki, Hiroki Matsutani, Hideharu Amano, Fabien Chaix, Ikki Fujiwara, Henri Casanova
2017	J	`jnl`	A Layout-Oriented Routing Method for Low-Latency HPC Networks. IEICE Trans. Inf. Syst. Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2017	J	`jnl`	A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing. IEICE Trans. Inf. Syst. Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2017	—	`conf`	An FPGA NIC Based Hardware Caching for Blockchain. HEART Yuma Sakakibara, Kohei Nakamura, Hiroki Matsutani
2017	C	`conf`	An FPGA-based In-NIC Cache Approach for Lazy Learning Outlier Filtering. PDP Ami Hayashi, Hiroki Matsutani
2017	—	`conf`	Building block multi-chip systems using inductive coupling through chip interface. ISOCC Hideharu Amano, Tadahiro Kuroda, Hiroshi Nakamura, Kimiyoshi Usami, Masaaki Kondo, Hiroki Matsutani, Mitaro Namiki
2017	B	`conf`	HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies. ICPADS Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2017	A*	`conf`	High-Bandwidth Low-Latency Approximate Interconnection Networks. HPCA Daichi Fujiki, Kiyo Ishii, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Henri Casanova, Michihiro Koibuchi
2017	J	`jnl`	High-Performance with an In-GPU Graph Database Cache. IT Prof. Shin Morishima, Hiroki Matsutani
2017	B	`conf`	In-switch approximate processing: Delayed tasks management for MapReduce applications. FPL Koya Mitsuzuka, Ami Hayashi, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani
2017	J	`jnl`	Multilevel NoSQL Cache Combining In-NIC and In-Kernel Approaches. IEEE Micro Yuta Tokusashi, Hiroki Matsutani
2017	B	`conf`	Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks. ICPP Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano
2017	—	`ed.`	Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2017, Seoul, Republic of Korea, October 19 - 20, 2017 NOCS Axel Jantsch, Hiroki Matsutani, Zhonghai Lu, Ümit Y. Ogras
2017	J	`jnl`	Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers. IEEE Trans. Computers Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura
2017	—	`conf`	Towards Tightly-coupled Datacenter with Free-space Optical Links. ICCBDC Yao Hu, Hiroaki Hara, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi
2016	—	`conf`	A Multilevel NOSQL Cache Design Combining In-NIC and In-Kernel Caches. Hot Interconnects Yuta Tokusashi, Hiroki Matsutani
2016	C	`conf`	ACRO: Assignment of channels in reverse order to make arbitrary routing deadlock-free. ICIS Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2016	B	`conf`	Accelerating Spark RDD Operations with Local and Remote GPU Devices. ICPADS Yasuhiro Ohno, Shin Morishima, Hiroki Matsutani
2016	—	`conf`	An FPGA-based low-latency network processing for spark streaming. IEEE BigData Kohei Nakamura, Ami Hayashi, Hiroki Matsutani
2016	—	`conf`	Design and implementation of hardware cache mechanism and NIC for column-oriented databases. ReConFig Akihiko Hamada, Hiroki Matsutani
2016	—	`conf`	Distributed In-GPU Data Cache for Document-Oriented Data Store via PCIe over 10 Gbit Ethernet. Euro-Par Workshops Shin Morishima, Hiroki Matsutani
2016	J	`jnl`	Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces. IEEE Trans. Very Large Scale Integr. Syst. Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano
2016	—	`conf`	LOREN: A Scalable Routing Method for Layout-Conscious Random Topologies. CANDAR Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2016	J	`jnl`	Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Systems. IEICE Trans. Electron. Akram Ben Ahmed, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano
2016	—	`conf`	NOSQL hardware appliance with multiple data structure. Hot Chips Symposium Yuta Tokusashi, Hiroki Matsutani
2016	J	`jnl`	Novel Chip Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface. IEICE Trans. Inf. Syst. Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2016	J	`jnl`	Optical network technologies for HPC: computer-architects point of view. IEICE Electron. Express Michihiro Koibuchi, Ikki Fujiwara, Kiyo Ishii, Shu Namiki, Fabien Chaix, Hiroki Matsutani, Hideharu Amano, Tomohiro Kudoh
2016	C	`conf`	Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication. PDP Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2016	B	`conf`	Randomly Optimized Grid Graph for Low-Latency Interconnection Networks. ICPP Koji Nakano, Daisuke Takafuji, Satoshi Fujita, Hiroki Matsutani, Ikki Fujiwara, Michihiro Koibuchi
2016	Misc	`conf`	The Future of NoCs: New Technologies and Architectures. VLSID Partha Pratim Pande, Sudeep Pasricha, Hiroki Matsutani
2016	—	`conf`	Vertical Packet Switching Elevator Network Using Inductive Coupling ThruChip Interface. CANDAR Akio Nomura, Hiroki Matsutani, Tadahiro Kuroda, Junichiro Kadomoto, Yusuke Matsushita, Hideharu Amano
2015	—	`conf`	3D Shared Bus Architecture Using Inductive Coupling Interconnect. MCSoC Akio Nomura, Yu Fujita, Hiroki Matsutani, Hideharu Amano
2015	J	`jnl`	A Line Rate Outlier Filtering FPGA NIC using 10GbE Interface. SIGARCH Comput. Archit. News Ami Hayashi, Yuta Tokusashi, Hiroki Matsutani
2015	—	`conf`	A metamorphotic Network-on-Chip for various types of parallel applications. ASAP Seiichi Tade, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi
2015	A*	`conf`	Augmenting low-latency HPC network with free-space optical links. HPCA Ikki Fujiwara, Michihiro Koibuchi, Tomoya Ozaki, Hiroki Matsutani, Henri Casanova
2015	—	`conf`	Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips. MCSoC Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2015	—	`conf`	On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck. NOCS Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura
2015	C	`conf`	Optimized Core-Links for Low-Latency NoCs. PDP Ryuta Kawano, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi
2015	—	`conf`	Performance Evaluations of Document-Oriented Databases Using GPU and Cache Structure. TrustCom/BigDataSE/ISPA (3) Shin Morishima, Hiroki Matsutani
2015	J	`jnl`	Swap-And-Randomize: A Method for Building Low-Latency HPC Interconnects. IEEE Trans. Parallel Distributed Syst. Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova
2014	J	`jnl`	3D NoC with Inductive-Coupling Links for Building-Block SiPs. IEEE Trans. Computers Yasuhiro Take, Hiroki Matsutani, Daisuke Sasaki, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano
2014	J	`jnl`	Dynamic Power Consumption Optimization for Inductive-Coupling based Wireless 3D NoCs. IPSJ Trans. Syst. LSI Des. Methodol. Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2014	—	`conf`	Introduction to the special session on "Interconnect enhances architecture: Evolution of wireless NoC from planar to 3D". NOCS Radu Marculescu, Partha Pratim Pande, Deuk Hyoun Heo, Hiroki Matsutani
2014	A	`conf`	Low-latency wireless 3D NoCs via randomized shortcut chips. DATE Hiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, Paul Bogdan, Radu Marculescu, Hideharu Amano
2014	J	`jnl`	Performance Evaluations of Graph Database using CUDA and OpenMP Compatible Libraries. SIGARCH Comput. Archit. News Shin Morishima, Hiroki Matsutani
2014	A	`conf`	Skywalk: A Topology for HPC Networks with Low-Delay Switches. IPDPS Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova
2013	—	`conf`	A Routing Strategy for Inductive-Coupling Based Wireless 3-D NoCs by Maximizing Topological Regularity. ICA3PP (2) Daisuke Sasaki, Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2013	J	`jnl`	A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface. IEEE Micro Noriyuki Miura, Yusuke Koizumi, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2013	—	`conf`	A case for wireless 3D NoCs for CMPs. ASP-DAC Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Yasuhiro Take, Daisuke Sasaki, Hao Zhang, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano
2013	—	`conf`	A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. COOL Chips Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2013	—	`conf`	A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. Hot Chips Symposium Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2013	B	`conf`	Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. FPL Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2013	—	`conf`	Dynamic power on/off method for 3D NoCs with wireless inductive-coupling links. COOL Chips Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2013	—	`conf`	Headfirst sliding routing: A time-based routing scheme for bus-NoC hybrid 3-D architecture. NOCS Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2013	A*	`conf`	Layout-conscious random topologies for HPC off-chip interconnects. HPCA Michihiro Koibuchi, Ikki Fujiwara, Hiroki Matsutani, Henri Casanova
2013	—	`conf`	Research Challenges on 2-D and 3-D Network-on-Chips. CANDAR Hiroki Matsutani
2013	J	`jnl`	Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs. IEICE Trans. Inf. Syst. Hao Zhang, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano
2012	A*	`conf`	A case for random shortcut topologies for HPC interconnects. ISCA Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casanova
2012	—	`conf`	A multi-Vdd dynamic variable-pipeline on-chip router for CMPs. ASP-DAC Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano
2012	J	`jnl`	Adaptive Data Compression on 3D Network-on-Chips. Inf. Media Technol. Yuan He, Hiroki Matsutani, Hiroshi Sasaki, Hiroshi Nakamura
2012	B	`conf`	CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. FPL Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2012	—	`conf`	Dependable Responsive Multithreaded Processor for distributed real-time systems. COOL Chips Kazutoshi Suito, Kei Fujii, Hiroki Matsutani, Nobuyuki Yamasaki
2012	—	`conf`	Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. FPT Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2012	—	`conf`	Fine-Grained Power Control Using A Multi-Voltage Variable Pipeline Router. MCSoC Takeo Nakamura, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano
2012	J	`jnl`	The Dependable Responsive Multithreaded Processor for Distributed Real-Time Systems. IEEE Micro Kazutoshi Suito, Rikuhei Ueda, Kei Fujii, Takuma Kogo, Hiroki Matsutani, Nobuyuki Yamasaki
2012	—	`conf`	Vertical Link On/Off Control Methods for Wireless 3-D NoCs. ARCS Hao Zhang, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano
2011	—	`ch.`	3-D NoC on Inductive Wireless Interconnect. 3D Integration for NoC-based SoC Architectures Hiroki Matsutani, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano
2011	—	`conf`	A Dynamic Link-Width Optimization for Network-on-Chip. RTCSA (2) Daihan Wang, Michihiro Koibuchi, Tomohiro Yoneda, Hiroki Matsutani, Hideharu Amano
2011	—	`conf`	A vertical bubble flow network using inductive-coupling for 3-D CMPs. NOCS Hiroki Matsutani, Yasuhiro Take, Daisuke Sasaki, Masayuki Kimura, Yuki Ono, Yukinori Nishiyama, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano
2011	J	`jnl`	An Efficient Path Setup for a Hybrid Photonic Network-on-Chip. Int. J. Netw. Comput. Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga
2011	—	`conf`	Design and Implementation of On-Chip Adaptive Router with Predictor for Regional Congestion. RTCSA (2) Masakazu Taniguchi, Hiroki Matsutani, Nobuyuki Yamasaki
2011	—	`conf`	Dynamic Voltage and Frequency Scaling for Real-Time Scheduling on a Prioritized SMT Processor. RTCSA (2) Kei Fujii, Hiroyuki Chishiro, Hiroki Matsutani, Nobuyuki Yamasaki
2011	Misc	`conf`	Performance Evaluation of Power-Aware Multi-tree Ethernet for HPC Interconnects. ICNC Michihiro Koibuchi, Takafumi Watanabe, Atsushi Minamihata, Masahiro Nakao, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano
2011	J	`jnl`	Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano
2011	J	`jnl`	Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors. IEEE Trans. Computers Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga
2011	—	`ch.`	Run-Time Power-Gating Techniques for Low-Power On-Chip Networks. Low Power Networks-on-Chip Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura, Hideharu Amano
2010	—	`conf`	A Deadlock-Free Non-minimal Fully Adaptive Routing Using Virtual Cut-Through Switching. NAS Yuri Nishikawa, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano
2010	—	`conf`	A variable-pipeline on-chip router optimized to traffic pattern. NoCArc@MICRO Yuto Hirata, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2010	Misc	`conf`	An Efficient Path Setup for a Photonic Network-on-Chip. ICNC Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga
2010	—	`conf`	Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks. NAS José Miguel Montañana Aliaga, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano
2010	—	`conf`	Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs. NOCS Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano
2009	J	`jnl`	A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs. IEICE Trans. Inf. Syst. Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2009	Misc	`conf`	An On/Off Link Activation Method for Power Regulation in InfiniBand. PDPTA José Miguel Montañana Aliaga, Michihiro Koibuchi, Takafumi Watanabe, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano
2009	A	`conf`	An on/off link activation method for low-power ethernet in PC clusters. IPDPS Michihiro Koibuchi, Tomohiro Otsuka, Hiroki Matsutani, Hideharu Amano
2009	—	`conf`	Balanced Dimension-Order Routing for k-ary n-cubes. ICPP Workshops José Miguel Montañana Aliaga, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano
2009	A	`conf`	Evaluation of a multicore reconfigurable architecture with variable core sizes. IPDPS Vu Manh Tuan, Naohiro Katsura, Hiroki Matsutani, Hideharu Amano
2009	J	`jnl`	Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. IEEE Trans. Parallel Distributed Syst. Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, D. Frank Hsu, Hideharu Amano
2009	B	`conf`	MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. FPL Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano
2009	A*	`conf`	Prediction router: Yet another low latency on-chip router architecture. HPCA Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga
2008	—	`conf`	A Lightweight Fault-Tolerant Mechanism for Network-on-Chip. NOCS Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy Mark Pinkston
2008	B	`conf`	A link removal methodology for Networks-on-Chip on reconfigurable systems. FPL Daihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi
2008	—	`conf`	Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks. NOCS Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano
2008	—	`conf`	Run-time power gating of on-chip routers using look-ahead routing. ASP-DAC Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang
2008	—	`conf`	Three-Dimensional Layout of On-Chip Tree-Based Networks. ISPAN Hiroki Matsutani, Michihiro Koibuchi, D. Frank Hsu, Hideharu Amano
2007	J	`jnl`	A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs. IEICE Trans. Inf. Syst. Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2007	B	`conf`	A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems. FPL Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2007	A	`conf`	Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. IPDPS Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2007	B	`conf`	Tightly-Coupled Multi-Layer Topologies for 3-D NoCs. ICPP Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2006	—	`conf`	A Parametric Study of Scalable Interconnects on FPGAs. ERSA Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano
2006	—	`conf`	A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks. PDCS Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2006	C	`conf`	Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels. ISPA Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2005	—	`conf`	An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor. FPT Yohei Hasegawa, Shohei Abe, Hiroki Matsutani, Hideharu Amano, Kenichiro Anjo, Toru Awashima
2005	Misc	`conf`	Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips. PDPTA Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2005	—	`conf`	Mobile Gateways for Mobile Ad-Hoc Networks with Network Mobility Support. ICN (2) Ryuji Wakikawa, Hiroki Matsutani, Rajeev Koodli, Anders Nilsson, Jun Murai
2005	—	`conf`	Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips. ICPP Workshops Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano