Hiroki Koike

24 papers A 1C 2Journal 12Unranked 9
YearRankTypeTitle / Venue / Authors
2022 — conf
Design and Heavy-Ion Testing of MTJ/CMOS Hybrid LSIs for Space-Grade Soft-Error Reliability.
IRPS
K. Watanabe, T. Shimada, K. Hirose, H. Shindo, D. Kobayashi, Takaho Tanigawa, Shoji Ikeda, Takamitsu Shinada, Hiroki Koike, Tetsuo Endoh, T. Makino, Takeshi Ohshima
2019 J jnl
A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications.
IEEE J. Solid State Circuits
Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2019 — conf
A novel memory test system with an electromagnet for STT-MRAM testing.
NVMTS
Ryo Tamura, N. Watanabe, Hiroki Koike, Hideo Sato, Shoji Ikeda, Tetsuo Endoh, Soshi Sato
2019 — conf
An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz.
ISSCC
Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2019 J jnl
Cyclic groups are CI-groups for balanced configurations.
Des. Codes Cryptogr.
Hiroki Koike, István Kovács, Dragan Marusic, Mikhail E. Muzychuk
2018 — conf
Accurate error bit mode analysis of STT-MRAM chip with a novel current measurement module implemented to gigabit class memory test system.
NVMTS
Ryo Tamura, I. Mori, N. Watanabe, Hiroki Koike, Tetsuo Endoh
2017 J jnl
Flag Bicolorings, Pseudo-Orientations, and Double Covers of Maps.
Electron. J. Comb.
Hiroki Koike, Daniel Pellicer, Miguel Raggi, Steve Wilson
2016 J jnl
An Overview of Nonvolatile Emerging Memories - Spintronics for Working Memories.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Tetsuo Endoh, Hiroki Koike, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno
2016 J jnl
Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing.
Proc. IEEE
Takahiro Hanyu, Tetsuo Endoh, Daisuke Suzuki, Hiroki Koike, Yitao Ma, Naoya Onizawa, Masanori Natsui, Shoji Ikeda, Hideo Ohno
2016 C conf
Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design.
ISCAS
Masanori Natsui, Akira Tamakoshi, Akira Mochizuki, Hiroki Koike, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2014 J jnl
Isomorphic tetravalent cyclic Haar graphs.
Ars Math. Contemp.
Hiroki Koike, István Kovács
2013 J jnl
A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme.
IEEE J. Solid State Circuits
Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
2012 — conf
1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times.
VLSIC
Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keiichi Tokutome, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
2012 C conf
High-speed simulator including accurate MTJ models for spintronics integrated circuit design.
ISCAS
Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
2011 J jnl
An Electrically Adjustable 3-Terminal Regulator for Post-Fabrication Level-Trimming with a Reliable 1-Wire Serial I/O.
IEICE Trans. Electron.
Hiroyuki Morimoto, Hiroki Koike, Kazuyuki Nakamura
2010 — conf
An electrically adjustable 3-terminal regulator with post-fabrication level-trimming function.
ASP-DAC
Hiroyuki Morimoto, Hiroki Koike, Kazuyuki Nakamura
2002 J jnl
A 128-kb FeRAM macro for contact/contactless smart-card microcontrollers.
IEEE J. Solid State Circuits
Junichi Yamada, Tohru Miwa, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Toru Tatsumi, Yukihiko Maejima, Hiromitsu Hada, Hidemitsu Mori, Seiichi Takahashi, Hidenori Takeuchi, Takemitsu Kunio
2001 — conf
FeRAM device and circuit technologies fully compatible with advanced CMOS.
CICC
Hideo Toyoshima, Sota Kobayashi, Junichi Yamada, Tohru Miwa, Hiroki Koike, Hidenori Takeuchi, Hidemitsu Mori, Naoki Kasai, Yukihiko Maejima, Nobuhira Tanabe, Toru Tatsumi, Hiromitsu Hada
2001 J jnl
NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors.
IEEE J. Solid State Circuits
Tohru Miwa, Junichi Yamada, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Toru Tatsumi, Yukihiko Maejima, Hiromitsu Hada, Takemitsu Kunio
2000 — conf
NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors.
CICC
Tohm Miwa, Junichi Yamada, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Tom Tatsumi, Yukihiro Maejima, Hiromitsu Hada, Takemitsu Kunio
1998 — conf
An embedded FeRAM macro cell for a smart card microcontroller.
CICC
Tohru Miwa, Junichi Yamada, Yuji Okamoto, Hiroki Koike, Hideo Toyoshiina, Hiromitsu Hada, Yoshihiro Hayashi, Hiroaki Oliizaki, Yoichi Miyasalca, Takemitsu Kunio, Hidenobu Miyamoto, Hideki Gomi, Hiroshi Kitajima
1992 J jnl
A 30-ns 64-Mb DRAM with built-in self-test and self-repair function.
IEEE J. Solid State Circuits
Akira Tanabe, Toshio Takeshima, Hiroki Koike, Yoshiharu Aimoto, Masahide Takada, Toshiyuki Ishijima, Naoki Kasai, Hiromitsu Hada, Kentaro Shibahara, Takemitsu Kunio, Takaho Tanigawa, Takanori Saeki, Masato Sakao, Hidenobu Miyamoto, Hiroshi Nozue, Shuichi Ohya, Tatsunori Murotani, Kuniaki Koyama, Takashi Okuda
1990 J jnl
A 55-ns 16-Mb DRAM with built-in self-test function using microprogram ROM.
IEEE J. Solid State Circuits
Toshio Takeshima, Masahide Takada, Hiroki Koike, Hiroshi Watanabe, Shigeru Koshimaru, Kenjiro Mitake, Wataru Kikuchi, Takaho Tanigawa, Tatsunori Murotani, Kenji Noda, Kazuhiro Tasaka, Koji Yamanaka, Kuniaki Koyama
1990 A conf
A BIST scheme using microprogram ROM for large capacity memories.
ITC
Hiroki Koike, Toshio Takeshima, Masahide Takada