Hiroki Ishikuro

134 papers C 8Journal 48Unranked 78

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 4.2-373 K Functional 800-MS/s 12-b Buffer-Then-Amplify Charge-Pump-Based Pipelined TI-SAR ADC With Integrated Active-Hold Technique. IEEE J. Solid State Circuits Kaoru Yamashita, Kentaro Yoshioka, Christian Ziegler, Vadim Issakov, Hiroki Ishikuro
2026	J	`jnl`	A Continuous-Time Pulse Compressor with Linear Frequency-Dependent Delay Achieving 1.66- IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shinya Kajiyama, Mizuki Mori, Yuki Koroyasu, Tomonari Nagata, Takahisa Mitsui, Nobuhiko Nakano, Hiroki Ishikuro
2026	J	`jnl`	A Cryo-BiCMOS Controller for Quantum Computers based on Trapped Beryllium Ions. IEEE J. Solid State Circuits Peter Toth, Paul Shine Eugine, Yerzhan Kudabay, Kaoru Yamashita, Sebastian Halama, Judi Parvizinejad, Marco Bonkowski, Hiroki Ishikuro, Christian Ospelkaus, Vadim Issakov
2025	—	`conf`	13.3 A Cryo-BiCMOS Controller for ISSCC Peter Toth, Paul Shine Eugine, Sebastian Halama, Yerzhan Kudabay, Kaoru Yamashita, Hiroki Ishikuro, Christian Ospelkaus, Vadim Issakov
2025	—	`conf`	A 4.6-373K Functional 800MS/s 12b Buffer-then-Amplify Charge-Pump-Based Pipelined TI-SAR ADC with Integrated-Active-Hold Technique. CICC Kaoru Yamashita, Kentaro Yoshioka, Christian Ziegler, Vadim Issakov, Hiroki Ishikuro
2024	C	`conf`	A 10-bit 100kS/s SAR ADC With a Monotonic Capacitor Switching Procedure for Single-Ended Inputs in 22nm CMOS FDSOI. ISCAS Alexander Meyer, Kaoru Yamashita, Adilet Dossanov, Martin Maier, Finn Stapelfeldt, Yerzhan Kudabay, Peter Toth, Fa Foster Dai, Hiroki Ishikuro, Vadim Issakov
2024	J	`jnl`	A 4.6-400 K Functional Ringamp-Based 250 MS/s 12 b Pipelined ADC With PVT-Robust Unity-Gain-Frequency-Aware Bias Calibration. IEEE J. Solid State Circuits Kaoru Yamashita, Benjamin P. Hershberg, Kentaro Yoshioka, Hiroki Ishikuro
2024	J	`jnl`	A Cryo-CMOS 10-bit 60-MS/s SAR ADC with common-mode variation suppression switching scheme and gain boosting dynamic comparator. Microelectron. J. Chia-Wei Pai, Ken Uchida, Munehiro Tada, Hiroki Ishikuro
2024	—	`conf`	A Direct Digital Synthesizer-Based Arbitrary Waveform Generator for Envelope Modulation in Trapped-Ion Quantum Computer Operating at 4K. BCICTS Paul Shine Eugine, Peter Toth, Kaoru Yamashita, Sebastian Halama, Christian Ospelkaus, Hiroki Ishikuro, Vadim Issakov
2024	J	`jnl`	Design and analysis of a high-speed low-power comparator with regeneration enhancement and through current suppression techniques from 4 K to 300 K in 65-nm Cryo-CMOS. Microelectron. J. Chia-Wei Pai, Ken Uchida, Munehiro Tada, Hiroki Ishikuro
2024	J	`jnl`	Design of Dual Lower Bound Hysteresis Control in Switched-Capacitor DC-DC Converter for Optimum Efficiency and Transient Speed in Wide Loading Range for IoT Application. IEEE J. Solid State Circuits Yi Tan, Cheng Huang, Hiroki Ishikuro
2024	—	`conf`	Orthogonal Decomposition Based Digital Controller Design for Hybrid Converter. MWSCAS Yi Tan, Jianqiang Jiang, Cheng Huang, Hiroki Ishikuro
2023	—	`conf`	A 4.6K to 400K Functional PVT-Robust Ringamp-Based 250MS/s 12b Pipelined ADC with Pole-Aware Bias Calibration. CICC Kaoru Yamashita, Benjamin P. Hershberg, Kentaro Yoshioka, Hiroki Ishikuro
2023	J	`jnl`	A Cryogenic 12 GHz Frequency Doubler With Temperature Compensation for Trapped-Ion Quantum Computer. IEEE Trans. Circuits Syst. II Express Briefs Peter Toth, Alexander Meyer, Sebastian Halama, Hiroki Ishikuro, Vadim Issakov
2023	—	`conf`	A High-Speed Low-Power Two-Stage Comparator with Regeneration Enhancement and Through Current Suppression Techniques. MWSCAS Chia-Wei Pai, Hiroki Ishikuro
2023	J	`jnl`	An Active Slew Rate Control Gate Driver IC With Robust Discrete-Time Feedback Technique for 600-V Superjunction MOSFETs. IEEE J. Solid State Circuits Shusuke Kawai, Takeshi Ueno, Hiroki Ishikuro, Kohei Onizuka
2023	—	`conf`	An Oscillator with Inductively Coupled Resonators for Readout of Stretchable Resistive Strain Sensor. MWSCAS Billy Mårtensson, Hinata Mitomo, Baktash Behmanesh, Naoji Matsuhisa, Hiroki Ishikuro
2022	—	`conf`	A Dual-Mode 2: 1 Switched Capacitor Converter with >65% Efficiency over 1000x Load Current Range and One Clock Cycle Transient Response. ICECS 2022 Yi Tan, Hiroki Ishikuro
2022	—	`conf`	Enhanced Drain Current in Transient Mode due to Long Ionization Time of Shallow Impurities at 4 K in 65-nm bulk Cryo CMOS Transistors. DRC Tomohisa Miyao, Takahisa Tanaka, Itsuki Imanishi, Masayuki Ichikawa, Shuya Nakagawa, Hiroki Ishikuro, Toshitsugu Sakamoto, Munehiro Tada, Ken Uchida
2022	J	`jnl`	Optimization of Gate Voltage in Capacitive DC-DC Converters for Thermoelectric Energy Harvesting. IEEE Trans. Very Large Scale Integr. Syst. Yi Tan, Yohsuke Shiiki, Hiroki Ishikuro
2022	J	`jnl`	T/R Switch Composed of Three HV-MOSFETs With 12.1-μW Consumption That Enables Per-Channel Self-Loopback AC Tests and -18.1-dB Switching Noise Suppression for 3-D Ultrasound Imaging With 3072-Ch Transceiver. IEEE Trans. Very Large Scale Integr. Syst. Shinya Kajiyama, Yutaka Igarashi, Toru Yazaki, Yusaku Katsube, Takuma Nishimoto, Tatsuo Nakagawa, Yohei Nakamura, Yoshihiro Hayashi, Takuya Kaneko, Hiroki Ishikuro, Taizo Yamawaki
2021	—	`conf`	A Fast Wake-Up and High Accuracy Sensor Interface by Synchronous Sampling with Power-Efficient Switching Regulator. MWSCAS Yuya Fuketa, Kohei Tatehora, Yohsuke Shiiki, Shuya Nakagawa, Hiroki Ishikuro
2021	—	`conf`	A Switched-Capacitor DC-DC Converter with >77.3% Efficiency and 80 ns Active Transient Response in 40 µA - 4 mA Load Current Range. ESSCIRC Yi Tan, Hiroki Ishikuro
2021	—	`conf`	An 18 Bit Time-to-Digital Converter Design with Large Dynamic Range and Automated Multi-Cycle Concept. ASP-DAC Peter Toth, Hiroki Ishikuro
2021	—	`conf`	An Amp-Less Time-Domain AC Bridge for Impedance Spectroscopy with 1-bit $\Delta \Sigma$ DAC. ICECS Yuya Maekawa, Hiroki Ishikuro
2021	—	`conf`	An up to 35 dBc/Hz Phase Noise Improving Design Methodology for Differential-Ring-Oscillators Applied in Ultra-Low Power Systems. ASP-DAC Peter Toth, Hiroki Ishikuro
2021	—	`conf`	Gate Voltage Optimization in Capacitive DC-DC Converters for Thermoelectric Energy Harvesting. ASP-DAC Yi Tan, Yohsuke Shiiki, Hiroki Ishikuro
2021	—	`conf`	Robust Readout Circuit with Leakage Current Cancellation Technique for Stretchable Touch Sensors. ICECS Kaoru Yamashita, Tokihiko Shimura, Shun Sato, Naoji Matsuhisa, Hiroki Ishikuro
2020	C	`conf`	A 0.12V Fully Integrated Charge Pump with Gate Voltage Optimization for Energy Harvesting Applications. ISCAS Yi Tan, Yohsuke Shiiki, Hiroki Ishikuro
2020	—	`conf`	A Digital-to-Resistance Converter with an Automatic Offset Calibration Method for Evaluating Dynamic Performance of Resistive Sensor Readout Circuits. I2MTC Shuya Nakagawa, Takumi Miyazaki, Hiroki Ishikuro
2020	—	`conf`	A Discrete-Time Model for Frequency Modulated Charge Pumps with Synchronized Controller. MWSCAS Yi Tan, Hiroki Ishikuro
2020	C	`conf`	A High-Resolution Oscillator Based Resistance-to-Digital Converter with Non-Linearity Canceling Feedback by ΔΣ Modulated Variable Resistor. ISCAS Shuya Nakagawa, Takumi Miyazaki, Hiroki Ishikuro
2020	—	`conf`	A Highly Linear Amp-Less Interface Circuit for Capacitive Sensors with ΔΣ C-DAC. APCCAS Yuya Maekawa, Syuya Nakagawa, Hiroki Ishikuro
2020	—	`conf`	A Linearity Testing of Cascaded Analog Mixed-Signal Blocks Using SEIR Method. I2MTC Tatsuya Ishikawa, Chia-Wei Pai, Hiroki Ishikuro
2020	—	`conf`	A Wide Input-Range, Low-Power and Highly Flexible 18 Bit Time-to-Digital Converter with Compact Differential Circuit Topology. MWSCAS Peter Toth, Hiroki Ishikuro
2020	C	`conf`	A Wide Range and High Accuracy Sensor Interface with Switching Regulator for Coin-Cell Powered Tiny Wireless Sensor Node. ISCAS Kohei Tatehora, Yohsuke Shiiki, S. Nakagawa, Takahisa Tanaka, Ken Uchida, Hiroki Ishikuro
2019	—	`conf`	A Differential-Ring-Oscillator with up to 35 dBc/Hz Phase Noise Improving Amplitude Feedback Loop for Ultra Low Power Systems. ICECS Peter Toth, Hiroki Ishikuro
2019	—	`conf`	A High Accuracy Opamp-less Interface Circuit for 2-D Cross-Point Resistive Sensor Array with Switch Resistance Calibration. APCCAS Yohsuke Shiiki, Hiroki Ishikuro
2019	J	`jnl`	Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits. IEEE Trans. Very Large Scale Integr. Syst. Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Hiroki Ishikuro, Tetsuro Itakura
2019	—	`conf`	High-Resolution Auto-Balancing Wheatstone-Bridge with Successive Approximation of ΔΣ-Modulated Digitally Controlled Variable Resistor. ICECS Takumi Miyazaki, Shuya Nakagawa, Hiroki Ishikuro
2019	C	`conf`	Interface with Opamp Output-Impedance Calibration Technique for a Large Integrated 2-D Resistive Sensor Array. ISCAS Yohsuke Shiiki, Hiroki Ishikuro
2019	—	`conf`	Low-Power and ppm-Level Detection of Gas Molecules by Integrated Metal Nanosheets. VLSI Circuits Takahisa Tanaka, K. Tabuchi, Kohei Tatehora, Yohsuke Shiiki, S. Nakagawa, Tsunaki Takahashi, R. Shimizu, Hiroki Ishikuro, Tadahiro Kuroda, T. Yanagida, Ken Uchida
2018	J	`jnl`	A 13.56-MHz Wireless Power Transfer System With Enhanced Load-Transient Response and Efficiency by Fully Integrated Wireless Constant-Idle-Time Control for Biomedical Implants. IEEE J. Solid State Circuits Cheng Huang, Toru Kawajiri, Hiroki Ishikuro
2018	—	`conf`	A High-Resolution Time-Based Resistance-to-Digital Converter with TDC and Counter. MWSCAS Shuya Nakagawa, Kaito Horikoshi, Hiroki Ishikuro
2018	—	`conf`	Design of resource sharing reconfigurable ΔΣ SAR-ADC. ASP-DAC Motomi Ishizuka, Kohei Yamada, Hiroki Ishikuro
2017	—	`conf`	Distortion and its suppression in low-power delta-sigma modulator. MWSCAS Hiroki Ishikuro
2016	J	`jnl`	A 12.5Gbps CDR with Differential to Common Converting Edge Detector for the Wired and Wireless Serial Link. IEICE Trans. Electron. Kaoru Kohira, Hiroki Ishikuro
2016	J	`jnl`	A 24 mW 5.7 Gbps Dual Frequency Conversion Demodulator for Impulse Radio with the First Sidelobe. IEICE Trans. Electron. Kaoru Kohira, Naoki Kitazawa, Hiroki Ishikuro
2016	—	`conf`	A 24mW 5.5Gbps dual frequency conversion demodulator for impulse-radio with first sidelobe. RWS Kaoru Kohira, Naoki Kitazawa, Hiroki Ishikuro
2016	J	`jnl`	A 280 Mb/s In-Vehicle LAN System Using Electromagnetic Clip Connector and High-EMC Transceiver. IEEE Trans. Circuits Syst. I Regul. Pap. Atsutake Kosuge, Akira Okada, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda
2016	J	`jnl`	A Near-Optimum 13.56 MHz CMOS Active Rectifier With Circuit-Delay Real-Time Calibrations for High-Current Biomedical Implants. IEEE J. Solid State Circuits Cheng Huang, Toru Kawajiri, Hiroki Ishikuro
2016	—	`conf`	A programmable ΔΣ SAR-ADC with charge shuttling technique. ISOCC Kohei Yamada, Yosuke Toyama, Hiroki Ishikuro
2016	—	`conf`	A wireless power transfer system with enhanced response and efficiency by fully-integrated fast-tracking wireless constant-idle-time control for implants. VLSI Circuits Cheng Huang, Toru Kawajiri, Hiroki Ishikuro
2016	J	`jnl`	An Inductively Powered Wireless Solid-State Drive System With Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories. IEEE J. Solid State Circuits Atsutake Kosuge, Junki Hashiba, Toru Kawajiri, So Hasegawa, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda, Ken Takeuchi
2016	C	`conf`	Low power DT delta-sigma modulator with ring amplifier SC-integrator. ISCAS Takuma Suguro, Hiroki Ishikuro
2015	—	`conf`	A 1.6 GS/s 3.17 mW 6-b passive pipelined binary-search ADC with memory effect canceller and reference voltage calibration. ESSCIRC Koki Tanaka, Ryo Saito, Hiroki Ishikuro
2015	—	`conf`	A low EMI SIDO wireless power transfer system with 10μsec response time. ESSCIRC Toru Kawajiri, Takahiro Moroto, Hiroki Ishikuro
2015	—	`conf`	A near-optimum 13.56 MHz active rectifier with circuit-delay real-time calibrations for high-current biomedical implants. CICC Cheng Huang, Toru Kawajiri, Hiroki Ishikuro
2015	J	`jnl`	An 8 bit 0.3-0.8 V 0.2-40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro
2015	J	`jnl`	Analysis and Design of an 8.5-Gb/s/Link Multi-Drop Bus Using Energy-Equipartitioned Transmission Line Couplers. IEEE Trans. Circuits Syst. I Regul. Pap. Atsutake Kosuge, Shu Ishizuka, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda
2015	—	`conf`	Dual-output wireless power delivery system for small size large volume wireless memory card. ASP-DAC Junki Hashiba, Toru Kawajiri, Yuya Hasegawa, Hiroki Ishikuro
2015	J	`jnl`	Dynamic Architecture and Frequency Scaling in 0.8-1.2 GS/s 7 b Subranging ADC. IEEE J. Solid State Circuits Kentaro Yoshioka, Ryo Saito, Takumi Danjo, Sanroku Tsukamoto, Hiroki Ishikuro
2015	—	`conf`	Fence loaded antenna coupler for high-band UWB with steep cutoff characteristics. RWS Isao Saito, Kaoru Kohira, Hiroki Ishikuro
2015	—	`conf`	I/Q mismatch compensation ΔΣ modulator using ternary capacitor rotation technique. ESSCIRC Masaki Yonekura, Hiroki Ishikuro
2015	—	`conf`	Inductively-powered wireless solid-state drive (SSD) system with merged error correction of high-speed non-contact data links and NAND flash memory. VLSIC Atsutake Kosuge, Junki Hashiba, Toru Kawajiri, So Hasegawa, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda, Ken Takeuchi
2014	—	`conf`	30.6 An electromagnetic clip connector for in-vehicle LAN to reduce wire harness weight by 30%. ISSCC Atsutake Kosuge, Shu Ishizuka, Lechang Liu, Akira Okada, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda
2014	—	`conf`	7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique. VLSIC Kentaro Yoshioka, Ryo Saito, Takumi Danjo, Sanroku Tsukamoto, Hiroki Ishikuro
2014	J	`jnl`	A 0.15-mm-Thick Noncontact Connector for MIPI Using a Vertical Directional Coupler. IEEE J. Solid State Circuits Atsutake Kosuge, Wataru Mizuhara, Tsunaaki Shidei, Tsutomu Takeya, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda
2014	—	`conf`	A 13b SAR ADC with eye-opening VCO based comparator. ESSCIRC Kentaro Yoshioka, Hiroki Ishikuro
2014	—	`conf`	A SAW-less LTE transmitter with high-linearity modulator using BPF-based I/Q summing. ESSCIRC Takahiro Nakamura, Naoki Kitazawa, Kaoru Kohira, Hiroki Ishikuro
2014	—	`conf`	An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique. ASP-DAC Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro
2013	—	`conf`	3D clock distribution using vertically/horizontally-coupled resonators. ISSCC Yasuhiro Take, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2013	—	`conf`	A 0.15mm-thick non-contact connector for MIPI using vertical directional coupler. ISSCC Wataru Mizuhara, Tsunaaki Shidei, Atsutake Kosuge, Tsutomu Takeya, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda
2013	—	`conf`	A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC. ASP-DAC Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro
2013	J	`jnl`	A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS. IEEE J. Solid State Circuits Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro
2013	—	`conf`	A 0.8V 1.1pJ/bit inductive-coupling receiver with pulse extracting clock recovery circuit and intermittently operating LNA. RWS Teruo Jyo, Tadahiro Kuroda, Hiroki Ishikuro
2013	C	`conf`	A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL. ISCAS Yuki Urano, Won-Joo Yun, Tadahiro Kuroda, Hiroki Ishikuro
2013	J	`jnl`	A 12-Gb/s Non-Contact Interface With Coupled Transmission Lines. IEEE J. Solid State Circuits Tsutomu Takeya, Lan Nan, Shinya Nakano, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2013	—	`conf`	A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched Transmission Line Couplers and Dicode partial-response channel transceivers. ASP-DAC Atsutake Kosuge, Wataru Mizuhara, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda
2013	J	`jnl`	A 4-10 bit, 0.4-1 V Power Supply, Power Scalable Asynchronous SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range SAR Controller. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Akira Shikata, Ryota Sekimoto, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro
2013	C	`conf`	A voltage scaling 0.25-1.8 V delta-sigma modulator with inverter-opamp self-configuring amplifier. ISCAS Kentaro Yoshioka, Yosuke Toyama, Teruo Jyo, Hiroki Ishikuro
2013	J	`jnl`	An Adaptive DAC Settling Waiting Time Optimized Ultra Low Voltage Asynchronous SAR ADC in 40 nm CMOS. IEICE Trans. Electron. Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro
2012	—	`conf`	0.6 - 3.6 GHz wideband operation with high phase resolution On-Chip Network Analyzer. APCCAS Abul Hasan Johari, Hiroki Ishikuro
2012	J	`jnl`	1-W 3.3-16.3-V Boosting Wireless Power Transfer Circuits With Vector Summing Power Controller. IEEE J. Solid State Circuits Kazutoshi Tomita, Ryota Shinoda, Tadahiro Kuroda, Hiroki Ishikuro
2012	J	`jnl`	6 W/25 mm IEICE Trans. Electron. Andrzej Radecki, Hayun Chung, Yoichi Yoshida, Noriyuki Miura, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda
2012	J	`jnl`	A 0.025-0.45 W 60%-Efficiency Inductive-Coupling Power Transceiver With 5-Bit Dual-Frequency Feedforward Control for Non-Contact Memory Cards. IEEE J. Solid State Circuits Hayun Chung, Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2012	J	`jnl`	A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS. IEEE J. Solid State Circuits Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro
2012	—	`conf`	A 0.7V 4.1mW 850Mbps/ch inductive-coupling transceiver with adaptive pulse width controller in 65nm CMOS. RWS Takeshi Matsubara, Isamu Hayashi, Abul Hasan Johari, Tadahiro Kuroda, Hiroki Ishikuro
2012	J	`jnl`	A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS. IEEE J. Solid State Circuits Hayun Chung, Hiroki Ishikuro, Tadahiro Kuroda
2012	—	`conf`	A 100Mb/s 13.7pJ/bit DC-960MHz band plesiochronous IR-UWB receiver with costas-loop based synchronization scheme in 65nm CMOS. CICC Lechang Liu, Hiroki Ishikuro, Tadahiro Kuroda
2012	—	`conf`	A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched transmission line couplers and Dicode partial-response channel transceivers. CICC Atsutake Kosuge, Wataru Mizuhara, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda
2012	—	`conf`	A 2Gb/s 150mW UWB direct-conversion coherent transceiver with IQ-switching carrier recovery scheme. ISSCC Takayuki Abe, Yuxiang Yuan, Hiroki Ishikuro, Tadahiro Kuroda
2012	J	`jnl`	A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration. IEEE Trans. Very Large Scale Integr. Syst. Kiichi Niitsu, Shusuke Kawai, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2012	—	`conf`	A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line. ISSCC Won-Joo Yun, Shinya Nakano, Wataru Mizuhara, Atsutake Kosuge, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2012	—	`conf`	An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator. ESSCIRC Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro
2012	J	`jnl`	High-Frequency Precise Characterization of Intrinsic FinFET Channel. IEICE Trans. Electron. Hideo Sakai, Shin-ichi O'Uchi, Takashi Matsukawa, Kazuhiko Endo, Yongxun Liu, Junichi Tsukada, Yuki Ishikawa, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara, Hiroki Ishikuro
2012	J	`jnl`	Rotary Coding for Power Reduction and S/N Improvement in Inductive-Coupling Data Communication. IEEE J. Solid State Circuits Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2012	J	`jnl`	Simultaneous 6-Gb/s Data and 10-mW Power Transmission Using Nested Clover Coils for Noncontact Memory Card. IEEE J. Solid State Circuits Andrzej Radecki, Yuxiang Yuan, Noriyuki Miura, Iori Aikawa, Yasuhiro Take, Hiroki Ishikuro, Tadahiro Kuroda
2012	—	`conf`	Voltage-boosting wireless power delivery system with fast load tracker by ΔΣ-modulated sub-harmonic resonant switching. ISSCC Ryota Shinoda, Kazutoshi Tomita, Yuya Hasegawa, Hiroki Ishikuro
2011	—	`conf`	1W 3.3V-to-16.3V boosting wireless power transfer circuits with vector summing power controller. A-SSCC Kazutoshi Tomita, Ryota Shinoda, Tadahiro Kuroda, Hiroki Ishikuro
2011	—	`conf`	6W/25mm ISSCC Andrzej Radecki, Hayun Chung, Yoichi Yoshida, Noriyuki Miura, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda
2011	—	`conf`	A 0.6V noise rejectable all-digital CDR with free running TDC for a pulse-based inductive-coupling interface. A-SSCC Won-Joo Yun, Hiroki Ishikuro, Tadahiro Kuroda
2011	—	`conf`	A 12Gb/s non-contact interface with coupled transmission lines. ISSCC Tsutomu Takeya, Lan Nan, Shinya Nakano, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2011	J	`jnl`	A 14-GHz AC-Coupled Clock Distribution Scheme With Phase Averaging Technique Using Single LC-VCO and Distributed Phase Interpolators. IEEE Trans. Very Large Scale Integr. Syst. Kiichi Niitsu, Vishwesh V. Kulkarni, Shinmo Kang, Hiroki Ishikuro, Tadahiro Kuroda
2011	—	`conf`	A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator. ESSCIRC Ryota Sekimoto, Akira Shikata, Tadahiro Kuroda, Hiroki Ishikuro
2011	J	`jnl`	Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration. IEEE Trans. Very Large Scale Integr. Syst. Kiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda
2011	—	`conf`	Rotary coding for power reduction and S/N improvement in inductive-coupling data communication. A-SSCC Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2010	—	`conf`	0.5 V multi-phase digital controlled oscillator with smooth phase transition circuit. APCCAS Abul Hasan Johari, Satoshi Kumaki, Takeshi Matsubara, Isamu Hayashi, Hiroki Ishikuro
2010	J	`jnl`	2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. IEEE J. Solid State Circuits Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda
2010	J	`jnl`	47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. IEEE Trans. Circuits Syst. I Regul. Pap. Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2010	—	`conf`	A 0.5V 6-bit scalable phase interpolator. APCCAS Satoshi Kumaki, Abul Hasan Johari, Takeshi Matsubara, Isamu Hayashi, Hiroki Ishikuro
2010	—	`conf`	A 0.5V 65nm-CMOS single phase clocked bootstrapped switch with rise time accelerator. APCCAS Akira Shikata, Ryota Sekimoto, Hiroki Ishikuro
2010	—	`conf`	A 2.5Gb/s/ch 4PAM inductive-coupling transceiver for non-contact memory card. ISSCC Shusuke Kawai, Hiroki Ishikuro, Tadahiro Kuroda
2010	J	`jnl`	A 4-Gbps Quasi-Millimeter-Wave Transmitter in 65 nm CMOS and a Fast Carrier and Symbol Timing Recovery Scheme. IEICE Trans. Electron. Vishal V. Kulkarni, Hiroki Ishikuro, Tadahiro Kuroda
2010	J	`jnl`	Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration. IEEE Trans. Very Large Scale Integr. Syst. Kiichi Niitsu, Yoshinori Kohama, Yasufumi Sugimori, Kazutaka Kasuga, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda
2010	J	`jnl`	Wireless proximity interfaces with a pulse-based inductive coupling technique. IEEE Commun. Mag. Hiroki Ishikuro, Tadahiro Kuroda
2009	—	`conf`	47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking. CICC Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2009	—	`conf`	A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking. ISSCC Yasufumi Sugimori, Yoshinori Kohama, Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda
2009	J	`jnl`	A 750 Mb/s, 12 pJ/b, 6-to-10 GHz CMOS IR-UWB Transmitter With Embedded On-Chip Antenna. IEEE J. Solid State Circuits Vishal V. Kulkarni, Muhammad Muqsith, Kiichi Niitsu, Hiroki Ishikuro, Tadahiro Kuroda
2009	J	`jnl`	A High-Speed Inductive-Coupling Link With Burst Transmission. IEEE J. Solid State Circuits Noriyuki Miura, Yoshinori Kohama, Yasufumi Sugimori, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda
2009	—	`conf`	A wireless real-time on-chip bus trace system. ASP-DAC Shusuke Kawai, Takayuki Ikari, Yutaka Takikawa, Hiroki Ishikuro, Tadahiro Kuroda
2008	J	`jnl`	A 0.14 pJ/b Inductive-Coupling Transceiver With Digitally-Controlled Precise Pulse Shaping. IEEE J. Solid State Circuits Noriyuki Miura, Hiroki Ishikuro, Kiichi Niitsu, Takayasu Sakurai, Tadahiro Kuroda
2008	—	`conf`	An 11Gb/s Inductive-Coupling Link with Burst Transmission. ISSCC Noriyuki Miura, Yoshinori Kohama, Yasufumi Sugimori, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda
2008	J	`jnl`	Constant Magnetic Field Scaling in Inductive-Coupling Data Link. IEICE Trans. Electron. Daisuke Mizoguchi, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2007	—	`conf`	A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping. ISSCC Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda
2007	—	`conf`	A 750Mb/s 12pJ/b 6-to-10GHz Digital UWB Transmitter. CICC Vishal V. Kulkarni, Muhammad Muqsith, Hiroki Ishikuro, Tadahiro Kuroda
2007	—	`conf`	An Attachable Wireless Chip Access Interface for Arbitrary Data Rate Using Pulse-Based lnductive-Coupling through LSI Package. ISSCC Hiroki Ishikuro, Toshihiko Sugahara, Tadahiro Kuroda
2007	J	`jnl`	An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors. IEICE Trans. Electron. Koichi Ishida, Atit Tamtrakarn, Hiroki Ishikuro, Makoto Takamiya, Takayasu Sakurai
2007	—	`conf`	Wideband Inductive-coupling Interface for High-performance Portable System. CICC Hiroki Ishikuro, Noriyuki Miura, Tadahiro Kuroda
2006	—	`conf`	Compact outside-rail circuit structure by single-cascode two-transistor topology. CICC Atit Tamtrakarn, Hiroki Ishikuro, Koichi Ishida, Takayasu Sakurai
2005	—	`conf`	A 1.2-V CMOS complex bandpass filter with a tunable center frequency. ESSCIRC Hideaki Majima, Hiroki Ishikuro, Kenichi Agawa, Mototsugu Hamada
2005	J	`jnl`	A 2.4-GHz Temperature-Compensated CMOS LC-VCO for Low Frequency Drift Low-Power Direct-Modulation GFSK Transmitters. IEICE Trans. Electron. Toru Tanzawa, Kenichi Agawa, Hiroyuki Shibayama, Ryota Terauchi, Katsumi Hisano, Hiroki Ishikuro, Shouhei Kousai, Hiroyuki Kobayashi, Hideaki Majima, Toru Takayama, Masayuki Koizumi, Fumitoshi Hatori
2005	—	`conf`	A phase noise minimization of CMOS VCOs over wide tuning range and large PVT variations. CICC Daisuke Miyashita, Hiroki Ishikuro, Shouhei Kousai, Hiroyuki Kobayashi, Hideaki Majima, Kenichi Agawa, Mototsugu Hamada
2004	—	`conf`	A temperature-compensated CMOS LC-VCO enabling the direct modulation architecture in 2.4GHz GFSK transmitter. CICC Toru Tanzawa, Hiroyuki Shibayama, Ryota Terauchi, Katsumi Hisano, Hiroki Ishikuro, Shouhei Kousai, Hiroyuki Kobayashi, Hideaki Majima, Toru Takayama, Kenichi Agawa, Masayuki Koizumi, Fumitoshi Hatori