Hirofumi Shinohara

71 papers A* 2A 3C 1Journal 31Unranked 34

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	A Sub-Threshold All-NMOS Reconfigurable PUF with Secure Configuration Selection for Stable 6b/Cell. ISSCC Shufan Xu, Kunyang Liu, Lando Chan, Hironori Tagawa, Hirofumi Shinohara, Kiichi Niitsu
2026	J	`jnl`	Entropy Improvement in Latch-Based True Random Number Generator Using Negative Bias Temperature Instability. IEEE Trans. Circuits Syst. I Regul. Pap. Ruilin Zhang, Ye Cao, Haochen Zhang, Quan Cheng, Shinichi Nishizawa, Kiichi Niitsu, Hirofumi Shinohara
2025	—	`conf`	A 22 nm CMOS .000005 \text{mm}^{2} 0.25 \mathrm{V}$ 2.3pW ISFET Front-End Using Low-Gate-Leakage Thick-Gate-Oxide Transistors for Energy-Efficient Small-Formfactor pH Monitoring. NewCAS Hiroaki Kitaike, Ruilin Zhang, Hironori Tagawa, Kento Okamura, Kei Awano, You Wu, Teruaki Ono, Kohei Sakamoto, Jin Nakamura, Masaya Kaneko, Kunyang Liu, Shufan Xu, Hirofumi Shinohara, Kiichi Niitsu
2025	—	`conf`	A 22 nm CMOS 0.034 mm2 0.4 V 1.3 nW Frequency-Recording IC with 400-Bit Data-Storing Shift Registers Using Burst-Pulse Counting and Reference Pulse Generation for Stand-Alone Continuous Glucose Monitoring Contact Lenses. LASCAS Kei Awano, You Wu, Kento Okamura, Teruaki Ono, Kohei Sakamoto, Hiroaki Kitaike, Hironori Tagawa, Jin Nakamura, Masaya Kaneko, Yuta Kimura, Hiroaki Nakamura, Shufan Xu, Ruilin Zhang, Kunyang Liu, Hirofumi Shinohara, Kiichi Niitsu
2025	—	`conf`	A 22nm CMOS 0.017mm ICECS Kento Okamura, Takeshi Fujiyabu, Hisataka Maruyama, Kei Awano, You Wu, Hiroaki Kitaike, Jin Nakamura, Masaya Kaneko, Yuta Kimura, Hiroaki Nakamura, Shufan Xu, Ruilin Zhang, Kunyang Liu, Hirofumi Shinohara, Daisuke Anzai, Natsuko Inagaki, Taichi Ito, Kiichi Niitsu
2025	J	`jnl`	A 65-nm CMOS Downconverter-Less Clock Generator Architecture Using Voltage Stacking of Oscillator and Frequency Dividers for Scaling-Friendly IoTs. IEEE Trans. Very Large Scale Integr. Syst. You Wu, Kei Awano, Kento Okamura, Teruaki Ono, Kohei Sakamoto, Hiroaki Kitaike, Hironori Tagawa, Jin Nakamura, Masaya Kaneko, Yuta Kimura, Hiroaki Nakamura, Shufan Xu, Ruilin Zhang, Kunyang Liu, Hirofumi Shinohara, Kiichi Niitsu
2024	—	`conf`	A 0.00027 mm NorCAS Hiroaki Kitaike, Hironori Tagawa, Masaya Kaneko, Jin Nakamura, Shufan Xu, Ruilin Zhang, Kunyang Liu, Hiroki Wakatsuchi, Kyoya Takano, Hirofumi Shinohara, Kiichi Niitsu
2024	J	`jnl`	A 0.116 pJ/bit Latch-Based True Random Number Generator Featuring Static Inverter Selection and Noise Enhancement. IEEE Trans. Very Large Scale Integr. Syst. Xingyu Wang, Ruilin Zhang, Kunyang Liu, Hirofumi Shinohara
2024	—	`conf`	A 2 Hz, 1.2-2 V, 0.22-9 nW, 0.007 mm NorCAS You Wu, Kei Awano, Kento Okamura, Teruaki Ono, Kohei Sakamoto, Hiroaki Kitaike, Hironori Tagawa, Jin Nakamura, Masaya Kaneko, Yuta Kimura, Hiroaki Nakamura, Shufan Xu, Ruilin Zhang, Kunyang Liu, Hirofumi Shinohara, Kiichi Niitsu
2024	J	`jnl`	A Single-Inverter-Based True Random Number Generator with On-Chip Clock-Tuning-Based Entropy Calibration Circuit. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Xingyu Wang, Ruilin Zhang, Hirofumi Shinohara
2024	—	`conf`	CLAPPER: Clonable LFSR-based Asymmetric PUF-group with Peer-to-peer Equivalent Response. MWSCAS Zhenzhe Chen, Kunyang Liu, Hirofumi Shinohara, Takashi Sato
2024	J	`jnl`	De-Correlation and De-Bias Post-Processing Circuits for True Random Number Generator. IEEE Trans. Circuits Syst. I Regul. Pap. Ruilin Zhang, Haochen Zhang, Xingyu Wang, Ziyang Ye, Kunyang Liu, Shinichi Nishizawa, Kiichi Niitsu, Hirofumi Shinohara
2024	—	`conf`	SpongePUF: A Modeling Attack Resilient Strong PUF with Scalable Challenge Response Pair. HOST Zhenzhe Chen, Takashi Sato, Hirofumi Shinohara
2023	—	`conf`	A 100-Bit-Output Modeling Attack-Resistant SPN Strong PUF with Uniform and High-Randomness Response. CICC Kunyang Liu, Yichen Tang, Shufan Xu, Ruilin Zhang, Hirofumi Shinohara
2023	—	`conf`	Practical Markov Chain and Von Neumann based Post-processing Circuits for True Random Number Generators. MWSCAS Ruilin Zhang, Haochen Zhang, Xingyu Wang, Ziyang Ye, Kunyang Liu, Hirofumi Shinohara
2022	—	`conf`	A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement. VLSI-DAT Xingyu Wang, Ruilin Zhang, Yuxin Wang, Kunyang Liu, Xuanzhen Wang, Hirofumi Shinohara
2022	J	`jnl`	A 0.186-pJ per Bit Latch-Based True Random Number Generator Featuring Mismatch Compensation and Random Noise Enhancement. IEEE J. Solid State Circuits Ruilin Zhang, Xingyu Wang, Kunyang Liu, Hirofumi Shinohara
2022	—	`conf`	A 2.17-pJ/b 5b-Response Attack-Resistant Strong PUF with Enhanced Statistical Performance. ESSCIRC Kunyang Liu, Gen Li, Zihan Fu, Xuanzhen Wang, Hirofumi Shinohara
2021	—	`conf`	36.3 A Modeling Attack Resilient Strong PUF with Feedback-SPN Structure Having <0.73% Bit Error Rate Through In-Cell Hot-Carrier Injection Burn-In. ISSCC Kunyang Liu, Zihan Fu, Gen Li, Hongliang Pu, Zhibo Guan, Xingyu Wang, Xinpeng Chen, Hirofumi Shinohara
2021	—	`conf`	A 0.186-pJ per Bit Latch-Based True Random Number Generator with Mismatch Compensation and Random Noise Enhancement. VLSI Circuits Ruilin Zhang, Xingyu Wang, Luying Wang, Xinpeng Chen, Fan Yang, Kunyang Liu, Hirofumi Shinohara
2021	J	`jnl`	A 0.5-V Hybrid SRAM Physically Unclonable Function Using Hot Carrier Injection Burn-In for Stability Reinforcement. IEEE J. Solid State Circuits Kunyang Liu, Xinpeng Chen, Hongliang Pu, Hirofumi Shinohara
2021	—	`conf`	Session 36 Overview: Hardware Security Digital Architectures and Systems Subcommittee. ISSCC Hirofumi Shinohara, Massimo Alioto, Ingrid Verbauwhede
2020	—	`conf`	A 0.5-V 2.07-fJ/b 497-F CICC Kunyang Liu, Hongliang Pu, Hirofumi Shinohara
2020	J	`jnl`	A 373-F IEEE J. Solid State Circuits Kunyang Liu, Yue Min, Xuan Yang, Hanfeng Sun, Hirofumi Shinohara
2020	—	`conf`	An Inverter-Based True Random Number Generator with 4-bit Von-Neumann Post-Processing Circuit. MWSCAS Xingyu Wang, HongJie Liu, Ruilin Zhang, Kunyang Liu, Hirofumi Shinohara
2019	—	`conf`	A CMOS 0.85-V 15.8-nW Current and Voltage Reference without Resistors. VLSI-DAT Jing Wang, Hirofumi Shinohara
2018	—	`conf`	A 373 F A-SSCC Kunyang Liu, Yue Min, Xuan Yang, Hanfeng Sun, Hirofumi Shinohara
2018	—	`conf`	High-throughput Von Neumann post-processing for random number generator. VLSI-DAT Ruilin Zhang, Sijia Chen, Chao Wan, Hirofumi Shinohara
2017	J	`jnl`	Accurate Nanopower Supply-Insensitive CMOS Unit IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jing Wang, Li Ding, Qiang Li, Hirofumi Shinohara, Yasuaki Inoue
2017	—	`conf`	Analysis and reduction of SRAM PUF Bit Error Rate. VLSI-DAT Hirofumi Shinohara, Baikun Zheng, Yanhao Piao, Bo Liu, Shiyu Liu
2016	J	`jnl`	A 3.5ppm/ IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jing Wang, Qiang Li, Li Ding, Hirofumi Shinohara, Yasuaki Inoue
2016	J	`jnl`	Design of a Sensorless Controller Synthesized by Robust H∞ Control for Boost Converters. IEICE Trans. Commun. Xutao Li, Minjie Chen, Hirofumi Shinohara, Tsutomu Yoshihara
2014	—	`conf`	A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology. COOL Chips Koichiro Ishibashi, Nobuyuki Sugii, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham, Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Hidekazu Oda, Takumi Hasegawa, Shinobu Okanishi, Hiroshi Yanagita, Shiro Kamohara, Masaru Kadoshima, Keiichi Maekawa, Tomohiro Yamashita, Duc-Hung Le, Takumu Yomogita, Masaru Kudo, Kuniaki Kitamori, Shuya Kondo, Yuuki Manzawa
2014	J	`jnl`	Extremely Low Power Digital and Analog Circuits. IEICE Trans. Electron. Hirofumi Shinohara
2013	—	`conf`	A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure. CICC Shusuke Yoshimoto, Shinji Miyano, Makoto Takamiya, Hirofumi Shinohara, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013	J	`jnl`	Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges. IEEE J. Solid State Circuits Shinji Miyano, Shinichi Moriwaki, Yasue Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Hirofumi Shinohara
2013	J	`jnl`	Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits. IEEE J. Solid State Circuits Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2013	J	`jnl`	Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: V IEEE Trans. Very Large Scale Integr. Syst. Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2013	—	`conf`	Variation-aware subthreshold logic circuit design. ASICON Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2012	—	`conf`	13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO. ISSCC Koji Hirairi, Yasuyuki Okuma, Hiroshi Fuketa, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2012	—	`conf`	24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V ISQED Tadashi Yasufuku, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai
2012	—	`conf`	60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations. ESSCIRC Yasue Yamamoto, Atsushi Kawasumi, Shinichi Moriwaki, Toshikazu Suzuki, Shinji Miyano, Hirofumi Shinohara
2012	—	`conf`	A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges. VLSIC Shinichi Moriwaki, Yasuhiro Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Shinji Miyano, Takayasu Sakurai, Hirofumi Shinohara
2012	—	`conf`	Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits. CICC Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2012	J	`jnl`	Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature. IEEE Trans. Circuits Syst. II Express Briefs Ryo Takahashi, Hidehiro Takata, Tadashi Yasufuku, Hiroshi Fuketa, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2011	—	`conf`	12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains. ESSCIRC Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomura, Makoto Takamiya, Hirofumi Shinohara, Takayasu Sakurai
2011	A	`conf`	12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V ISLPED Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2011	A*	`conf`	A closed-form expression for estimating minimum operating voltage (V DAC Hiroshi Fuketa, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2011	J	`jnl`	Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits. IEEE Trans. Circuits Syst. II Express Briefs Yu Pu, Xin Zhang, Katsuyuki Ikeuchi, Atsushi Muramatsu, Atsushi Kawasumi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2010	—	`conf`	0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme. ESSCIRC Toshikazu Suzuki, Shinichi Moriwaki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara
2010	J	`jnl`	Phase-adjustable error detection flip-flops with 2-stage hold-driven optimization, slack-based grouping scheme and slack distribution control for dynamic voltage scaling. ACM Trans. Design Autom. Electr. Syst. Masanori Kurimoto, Hiroaki Suzuki, Rei Akiyama, Tadao Yamanaka, Haruyuki Ohkuma, Hidehiro Takata, Hirofumi Shinohara
2009	J	`jnl`	Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access. IEEE J. Solid State Circuits Koji Nii, Yasumasa Tsukamoto, Makoto Yabuuchi, Yasuhiro Masuda, Susumu Imaoka, Keiichi Usui, Shigeki Ohbayashi, Hiroshi Makino, Hirofumi Shinohara
2008	J	`jnl`	A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues. IEEE J. Solid State Circuits Satoshi Ishikura, Marefusa Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi, Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara, Hironori Akamatsu
2008	J	`jnl`	A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations. IEEE J. Solid State Circuits Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara
2008	J	`jnl`	A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die. IEEE J. Solid State Circuits Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Tsutomu Yoshihara, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
2008	J	`jnl`	A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology. IEICE Trans. Electron. Masako Fujii, Koji Nii, Hiroshi Makino, Shigeki Ohbayashi, Motoshige Igarashi, Takeshi Kawamura, Miho Yokota, Nobuhiro Tsuda, Tomoaki Yoshizawa, Toshikazu Tsutsui, Naohiko Takeshita, Naofumi Murata, Tomohiro Tanaka, Takanari Fujiwara, Kyoko Asahina, Masakazu Okada, Kazuo Tomita, Masahiko Takeuchi, Shigehisa Yamamoto, Hiromitsu Sugimoto, Hirofumi Shinohara
2008	J	`jnl`	Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration. IEICE Trans. Electron. Hirofumi Shinohara, Koji Nii, Hidetoshi Onodera
2008	—	`conf`	On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect. ESSCIRC Masako Fujii, Hiroaki Suzuki, Hiromi Notani, Hiroshi Makino, Hirofumi Shinohara
2008	A*	`conf`	Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling. DAC Masanori Kurimoto, Hiroaki Suzuki, Rei Akiyama, Tadao Yamanaka, Haruyuki Ohkuma, Hidehiro Takata, Hirofumi Shinohara
2008	A	`conf`	Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology. ISLPED Hiroaki Suzuki, Masanori Kurimoto, Tadao Yamanaka, Hidehiro Takata, Hiroshi Makino, Hirofumi Shinohara
2007	—	`conf`	A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations. ISSCC Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara
2007	J	`jnl`	A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits. IEEE J. Solid State Circuits Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
2007	—	`conf`	A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die. ISSCC Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
2005	A	`conf`	Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. ICCAD Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
1996	J	`jnl`	A 64-bit carry look ahead adder using pass transistor BiCMOS gates. IEEE J. Solid State Circuits Kiniio Ueda, Hiroaki Suzuki, Kakutaro Suda, Hirofumi Shinohara, Koichiro Mashiko
1996	J	`jnl`	An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture. IEEE J. Solid State Circuits Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko
1995	J	`jnl`	A BiCMOS wired-OR logic. IEEE J. Solid State Circuits Yasunobu Nakase, Hiroaki Suzuki, Hiroshi Makino, Hirofumi Shinohara, Koichiro Mashiko
1993	C	`conf`	A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture. ICCD Hiroshi Makino, Yasunobu Nakase, Hirofumi Shinohara
1992	J	`jnl`	A refreshable analog VLSI neural network chip with 400 neurons and 40 K synapses. IEEE J. Solid State Circuits Yutaka Arima, Mitsuhiro Murasaki, Tsuyoshi Yamada, Atsushi Maeda, Hirofumi Shinohara
1991	J	`jnl`	A flexible multiport RAM compiler for data path. IEEE J. Solid State Circuits Hirofumi Shinohara, Noriaki Matsumoto, Kumiko Fujimori, Yoshiki Tsujihashi, Hiroomi Nakao, Shuichi Kato, Yasutaka Horiba, Akiharu Tada
1990	J	`jnl`	A 24-b 50-ns digital image signal processor. IEEE J. Solid State Circuits Shin-ichi Nakagawa, Hideyuki Terane, Tetsuya Matsumura, Hiroshi Segawa, Masahiko Yoshimoto, Hirofumi Shinohara, Shuichi Kato, Masahiro Hatanaka, Hideo Ohira, Yoshiaki Kato, Mamoru Iwatsuki, Kinya Tabuchi, Yasutaka Horiba