Hirofumi Nakano

17 papers B 1C 1Journal 8Unranked 7
YearRankTypeTitle / Venue / Authors
2017 J jnl
Theoretical Analysis of Activity Cliffs among Benzofuranone-Class Pim1 Inhibitors Using the Fragment Molecular Orbital Method with Molecular Mechanics Poisson-Boltzmann Surface Area (FMO+MM-PBSA) Approach.
J. Chem. Inf. Model.
Chiduru Watanabe, Hirofumi Watanabe, Kaori Fukuzawa, Lorien J. Parker, Yoshio Okiyama, Hitomi Yuki, Shigeyuki Yokoyama, Hirofumi Nakano, Shigenori Tanaka, Teruki Honma
2014 J jnl
A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation.
IEICE Trans. Electron.
Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto
2014 — conf
A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement.
ISQED
Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012 — conf
A stable chip-ID generating physical uncloneable function using random address errors in SRAM.
SoCC
Hidehiro Fujiwara, Makoto Yabuuchi, Yasumasa Tsukamoto, Hirofumi Nakano, Toru Owada, Hiroyuki Kawai, Koji Nii
2011 J jnl
A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture.
Trans. High Perform. Embed. Archit. Compil.
Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
2010 — conf
Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation.
SoCC
Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Hirofumi Nakano, Kazuya Ishihara, Hiroyuki Kawai, Kazutami Arimoto
2008 C conf
Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API.
ISPA
Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, Masayoshi Mase, Yasutaka Wada, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara
2005 — conf
Multigrain parallel processing on compiler cooperative chip multiprocessor.
Interaction between Compilers and Computer Architectures
Keiji Kimura, Yasutaka Wada, Hirofumi Nakano, Takeshi Kodaka, Jun Shirako, Kazuhisa Ishizaka, Hironori Kasahara
2005 — conf
Performance Evaluation of Compiler Controlled Power Saving Scheme.
ISHPC
Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
2003 J jnl
Static Coarse Grain Task Scheduling with Cache Optimization Using OpenMP.
Int. J. Parallel Program.
Hirofumi Nakano, Kazuhisa Ishizaka, Motoki Obata, Keiji Kimura, Hironori Kasahara
2002 — conf
Multigrain Automatic Parallelization in Japanese Millennium Project IT21 Advanced Parallelizing Compiler.
PARELEC
Hironori Kasahara, Motoki Obata, Kazuhisa Ishizaka, Keiji Kimura, Hiroki Kaminaga, Hirofumi Nakano, Kouhei Nagasawa, Akiko Murai, Hiroki Itagaki, Jun Shirako
2002 — conf
Static Coarse Grain Task Scheduling with Cache Optimization Using OpenMP.
ISHPC
Hirofumi Nakano, Kazuhisa Ishizaka, Motoki Obata, Keiji Kimura, Hironori Kasahara
2001 B conf
Bolt tightening control using neural networks.
SMC
Toru Fujinaka, Hirofumi Nakano, Sigeru Omatu
2000 J jnl
Bolt Tightening Using Impact Wrench Based on Neural Networks.
J. Robotics Mechatronics
Toru Fujinaka, Hirofumi Nakano, Michifumi Yoshioka, Sigeru Omatu
1999 J jnl
A 12-ps-resolution digital variable-delay macro cell on GaAs 100 K-gates gate array using a meshed air bridge structure.
IEEE J. Solid State Circuits
Akira Ohta, Norio Higashisaka, Tetsuya Heima, Takayuki Hisaka, Hirofumi Nakano, Ryuji Ohmura, Tadashi Takagi, Noriyuki Tanino
1994 J jnl
The reversible DNA-alkylating activity of duocarmycin and its analogues.
Nucleic Acids Res.
Akira Asai, Satoru Nagamura, Hiromitsu Saito, Isami Takahashi, Hirofumi Nakano
1991 J jnl
A 5-ns GaAs 16-kb SRAM.
IEEE J. Solid State Circuits
Shuichi Matsue, Hiroshi Makino, Minoru Noda, Hirofumi Nakano, Satoshi Takano, Kazuo Nishitani, Shimpei Kayano