Hiroaki Shikano

11 papers B 1Misc 1Journal 5Unranked 4
YearRankTypeTitle / Venue / Authors
2017 — conf
QoS Analysis on Cable Video Delivery Networks.
DCNET
Hiroaki Shikano, Takeshi Shibata, Qifeng Shen, Miyuki Hanaoka, Mariko Miyaki, Masahide Ban, Prasad Rallapalli, Yukinori Sakashita
2013 Misc conf
Study on supporting technology for operational procedure design of IT systems in cloud-era datacenters.
SAC
Hiroaki Shikano, Machiko Asaie, Junji Yamamoto, Tatsuya Saito, Shunsuke Ota, Keitaro Uehara
2011 J jnl
A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture.
Trans. High Perform. Embed. Archit. Compil.
Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
2008 J jnl
Clock Driver Design for Low-Power High-Speed 90-nm CMOS Register Array.
IEICE Trans. Electron.
Tadayoshi Enomoto, Suguru Nagayama, Hiroaki Shikano, Yousuke Hagiwara
2008 J jnl
Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding.
IEEE J. Solid State Circuits
Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
2008 J jnl
Power-Aware Compiler Controllable Chip Multiprocessor.
IEICE Trans. Electron.
Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
2008 — conf
Software-cooperative power-efficient heterogeneous multi-core for media processing.
ASP-DAC
Hiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka, Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
2007 B conf
Power-Aware Compiler Controllable Chip Multiprocessor.
PACT
Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
2005 — conf
Compiler Control Power Saving Scheme for Multi Core Processors.
LCPC
Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
2005 — conf
Performance Evaluation of Compiler Controlled Power Saving Scheme.
ISHPC
Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
2003 J jnl
A self-controllable voltage level (SVL) circuit and its low-power high-speed CMOS circuit applications.
IEEE J. Solid State Circuits
Tadayoshi Enomoto, Yoshinori Oka, Hiroaki Shikano