Hiok-Tiaq Ng - RankMe

12 papers A 1C 1Journal 7Unranked 3

Year	Rank	Type	Title / Venue / Authors
2012	—	`conf`	A 16-port FCC-compliant 10GBase-T transmitter and hybrid with 76dBc SFDR up to 400MHz scalable to 48 ports. ISSCC Friedel Gerfers, Ramin Farjad-Rad, Michael Brown, Ahmad Tavakoli, David Nguyen, Hiok-Tiaq Ng, Ramin Shirani
2012	J	`jnl`	A 48-Port FCC-Compliant 10GBASE-T Transmitter With Mixed-Mode Adaptive Echo Canceller. IEEE J. Solid State Circuits Ramin Farjad-Rad, Friedel Gerfers, Michael Brown, Ahmad Tavakoli, David Nguyen, Hossein Sedarat, Ramin Shirani, Hiok-Tiaq Ng
2004	J	`jnl`	A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os. IEEE J. Solid State Circuits Ramin Farjad-Rad, Anhtuyet Nguyen, James Tran, Trey Greer, John Poulton, William J. Dally, John H. Edmondson, Ramesh Senthinathan, Rohit Rathi, Ming-Ju Edward Lee, Hiok-Tiaq Ng
2003	—	`conf`	A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os. CICC Hiok-Tiaq Ng, Ming-Ju Edward Lee, Ramin Farjad-Rad, Ramesh Senthinathan, William J. Dally, Anhtuyet Nguyen, Rohit Rathi, Trey Greer, John Poulton, John H. Edmondson, James Tran
2003	J	`jnl`	A second-order semidigital clock recovery circuit based on injection locking. IEEE J. Solid State Circuits Hiok-Tiaq Ng, Ramin Farjad-Rad, Ming-Ju Edward Lee, William J. Dally, Trey Greer, John Poulton, John H. Edmondson, Rohit Rathi, Ramesh Senthinathan
2003	C	`conf`	CMOS High-Speed I/Os - Present and Future. ICCD Ming-Ju Edward Lee, William J. Dally, Ramin Farjad-Rad, Hiok-Tiaq Ng, Ramesh Senthinathan, John H. Edmondson, John W. Poulton
2003	J	`jnl`	Jitter transfer characteristics of delay-locked loops - theories and design techniques. IEEE J. Solid State Circuits Ming-Ju Edward Lee, William J. Dally, Trey Greer, Hiok-Tiaq Ng, Ramin Farjad-Rad, John Poulton, Ramesh Senthinathan
2002	J	`jnl`	A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips. IEEE J. Solid State Circuits Ramin Farjad-Rad, William J. Dally, Hiok-Tiaq Ng, Ramesh Senthinathan, Ming-Ju Edward Lee, Rohit Rathi, John Poulton
1999	J	`jnl`	A multistage amplifier technique with embedded frequency compensation. IEEE J. Solid State Circuits Hiok-Tiaq Ng, Ramsin M. Ziazadeh, David J. Allstot
1998	—	`conf`	A multistage amplifier topology with embedded tracking compensation. CICC Ramsin M. Ziazadeh, Hiok-Tiaq Ng, David J. Allstot
1997	J	`jnl`	CMOS current steering logic for low-voltage mixed-signal integrated circuits. IEEE Trans. Very Large Scale Integr. Syst. Hiok-Tiaq Ng, David J. Allstot
1997	A	`conf`	Charge-pump assisted low-power/low-voltage CMOS opamp design. ISLPED Jianjun Zhou, Ramsin M. Ziazadeh, H.-H. Ng, Hiok-Tiaq Ng, David J. Allstot