Himanshu Thapliyal

238 papers A* 1A 6C 21Misc 9Journal 117Unranked 79
YearRankTypeTitle / Venue / Authors
2025 J jnl
Cognitive and Semantic Computing for Enhanced User Experience.
IEEE Consumer Electron. Mag.
Vinay Chamola, Himanshu Thapliyal, Hassnaa Moustafa, Biplab Sikdar, Amir Hussain
2025 C conf
Crosstalk Attack Resilient RNS Quantum Addition.
ISCAS
Bhaskar Gaur, Himanshu Thapliyal
2025 C conf
Detection of Physiological Data Tampering Attacks with Quantum Machine Learning.
ISCAS
Md. Saif Hassan Onim, Himanshu Thapliyal
2025 J jnl
Detection of Physiological Data Tampering Attacks with Quantum Machine Learning.
CoRR
Md. Saif Hassan Onim, Himanshu Thapliyal
2025 — conf
Emotion Detection in Older Adults Using Physiological Signals from Wearable Sensors.
ACM Great Lakes Symposium on VLSI
Md. Saif Hassan Onim, Andrew Kiselica, Himanshu Thapliyal
2025 J jnl
Emotion Detection in Older Adults Using Physiological Signals from Wearable Sensors.
CoRR
Md. Saif Hassan Onim, Andrew Kiselica, Himanshu Thapliyal
2025 — conf
Emotion Recognition in Older Adults with Quantum Machine Learning and Wearable Sensors.
ISVLSI
Md. Saif Hassan Onim, Travis S. Humble, Himanshu Thapliyal
2025 J jnl
Emotion Recognition in Older Adults with Quantum Machine Learning and Wearable Sensors.
CoRR
Md. Saif Hassan Onim, Travis S. Humble, Himanshu Thapliyal
2025 J jnl
Guest Editorial: Selected Papers From IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2024.
IEEE Trans. Very Large Scale Integr. Syst.
Himanshu Thapliyal, Jürgen Becker, Garrett S. Rose, Tosiron Adegbija, Selçuk Köse
2025 A* conf
Late Breaking Results: Novel Design of MTJ-Based Unified LIF Spiking Neuron and PUF.
DAC
Milad Tanavardi Nasab, Wu Yang, Himanshu Thapliyal
2025 J jnl
MTJ/CMOS-Based CLB Design for Low-Power and CPA-Resistant Secure Nonvolatile FPGA.
IEEE Trans. Very Large Scale Integr. Syst.
Milad Tanavardi Nasab, Himanshu Thapliyal, Garrett S. Rose
2025 C conf
Quantum Hybrid Support Vector Machines for Stress Detection in Older Adults.
ICCE
Md. Saif Hassan Onim, Travis S. Humble, Himanshu Thapliyal
2025 J jnl
Quantum Hybrid Support Vector Machines for Stress Detection in Older Adults.
CoRR
Md. Saif Hassan Onim, Travis S. Humble, Himanshu Thapliyal
2025 — conf
Quantum Properties Trojans (QuPTs) for Attacking Quantum Neural Networks.
ISVLSI
Sounak Bhowmik, Travis S. Humble, Himanshu Thapliyal
2025 J jnl
Quantum Properties Trojans (QuPTs) for Attacking Quantum Neural Networks.
CoRR
Sounak Bhowmik, Travis S. Humble, Himanshu Thapliyal
2025 — conf
Quantum Transfer Learning to Boost Dementia Detection.
ACM Great Lakes Symposium on VLSI
Sounak Bhowmik, Talita Perciano, Himanshu Thapliyal
2025 J jnl
Quantum Transfer Learning to Boost Dementia Detection.
CoRR
Sounak Bhowmik, Talita Perciano, Himanshu Thapliyal
2025 J jnl
Quantum-Hybrid Support Vector Machines for Anomaly Detection in Industrial Control Systems.
CoRR
Tyler Cultice, Md. Saif Hassan Onim, Annarita Giani, Himanshu Thapliyal
2025 J jnl
Residue Number System (RNS) based Distributed Quantum Multiplication.
CoRR
Bhaskar Gaur, Himanshu Thapliyal
2025 J jnl
The 3rd Workshop on Quantum in Consumer Technology at IEEE Quantum Week 2024.
IEEE Consumer Electron. Mag.
Rafael Sotelo, Edoardo Giusto, Yuichi Nakamura, Jingbo Wang, Sreeraman Rajan, Himanshu Thapliyal
2024 J jnl
A Logarithmic Depth Quantum Carry-Lookahead Modulo (2
CoRR
Bhaskar Gaur, Edgard Muñoz-Coreas, Himanshu Thapliyal
2024 J jnl
A Review of Context-Aware Machine Learning for Stress Detection.
IEEE Consumer Electron. Mag.
Md. Saif Hassan Onim, Elizabeth K. Rhodus, Himanshu Thapliyal
2024 — conf
Anomaly Detection for Real-World Cyber-Physical Security Using Quantum Hybrid Support Vector Machines.
ISVLSI
Tyler Cultice, Md. Saif Hassan Onim, Annarita Giani, Himanshu Thapliyal
2024 J jnl
Anomaly Detection for Real-World Cyber-Physical Security using Quantum Hybrid Support Vector Machines.
CoRR
Tyler Cultice, Md. Saif Hassan Onim, Annarita Giani, Himanshu Thapliyal
2024 — conf
Automated Generation of Dual Rail Adiabatic Gates from Binary Decision Diagrams.
ISVLSI
Joseph Clark, Elijah Raffel, Himanshu Thapliyal
2024 J jnl
CAN Bus: The Future of Additive Manufacturing (3D Printing).
IEEE Consumer Electron. Mag.
Jun-Cheng Chin, Himanshu Thapliyal, Tyler Cultice
2024 J jnl
Crosstalk Attack Resilient RNS Quantum Addition.
CoRR
Bhaskar Gaur, Himanshu Thapliyal
2024 — conf
Energy-Efficient Power Analysis Attack Resilient Adiabatic MTJ-Based Nonvolatile CLB.
ISVLSI
Milad Tanavardi Nasab, Wu Yang, Himanshu Thapliyal
2024 J jnl
GTQCP: Greedy Topology-Aware Quantum Circuit Partitioning.
CoRR
Joseph Clark, Travis S. Humble, Himanshu Thapliyal
2024 — conf
Message from the General Chairs; ISVLSI 2024.
ISVLSI
Himanshu Thapliyal, Jürgen Becker
2024 — conf
Message from the Quantum Computing Workshop Chairs; ISVLSI 2024.
ISVLSI
Travis S. Humble, Himanshu Thapliyal
2024 J jnl
Noise-Resilient and Reduced Depth Approximate Adders for NISQ Quantum Computing.
CoRR
Bhaskar Gaur, Travis S. Humble, Himanshu Thapliyal
2024 J jnl
Novel Optimized Designs of Modulo 2
IEEE Trans. Very Large Scale Integr. Syst.
Bhaskar Gaur, Himanshu Thapliyal
2024 J jnl
Novel Optimized Designs of Modulo 2n+1 Adder for Quantum Computing.
CoRR
Bhaskar Gaur, Himanshu Thapliyal
2024 — conf
Peephole Optimization for Quantum Approximate Synthesis.
ISQED
Joseph Clark, Himanshu Thapliyal
2024 J jnl
Peephole Optimization for Quantum Approximate Synthesis.
CoRR
Joseph Clark, Himanshu Thapliyal
2024 — conf
Predicting Stress in Older Adults with RNN and LSTM from Time Series Sensor Data and Cortisol.
ISVLSI
Md. Saif Hassan Onim, Himanshu Thapliyal
2024 — conf
Quantum Machine Learning for Anomaly Detection in Consumer Electronics.
ISVLSI
Sounak Bhowmik, Himanshu Thapliyal
2024 J jnl
Quantum Machine Learning for Anomaly Detection in Consumer Electronics.
CoRR
Sounak Bhowmik, Himanshu Thapliyal
2024 — conf
Residue Number System (RNS) Based Distributed Quantum Addition.
ISVLSI
Bhaskar Gaur, Travis S. Humble, Himanshu Thapliyal
2024 J jnl
Residue Number System (RNS) based Distributed Quantum Addition.
CoRR
Bhaskar Gaur, Travis S. Humble, Himanshu Thapliyal
2024 — conf
Transfer Learning Based Hybrid Quantum Neural Network Model for Surface Anomaly Detection.
ISVLSI
Sounak Bhowmik, Himanshu Thapliyal
2024 J jnl
Utilizing Machine Learning for Context-Aware Digital Biomarker of Stress in Older Adults.
Inf.
Md. Saif Hassan Onim, Himanshu Thapliyal, Elizabeth K. Rhodus
2024 J jnl
Vulnerabilities and Attacks on CAN-Based 3D Printing/Additive Manufacturing.
IEEE Consumer Electron. Mag.
Tyler Cultice, Himanshu Thapliyal
2024 — conf
WAFER: Wearable, Ambient-Aware Adversarial Fall Event Detection System Using a RISC-V SoC Architecture.
ISVLSI
Tamonash Bhattacharyya, Akanksha Lohia, Prasun Ghosal, Himanshu Thapliyal
2023 — conf
A Logarithmic Depth Quantum Carry-Lookahead Modulo (2n - 1) Adder.
ACM Great Lakes Symposium on VLSI
Bhaskar Gaur, Edgard Muñoz-Coreas, Himanshu Thapliyal
2023 J jnl
A Novel Hierarchical Security Solution for Controller-Area-Network-Based 3D Printing in a Post-Quantum World.
Sensors
Tyler Cultice, Joseph Clark, Wu Yang, Himanshu Thapliyal
2023 J jnl
Adiabatic/MTJ-Based Physically Unclonable Function for Consumer Electronics Security.
IEEE Trans. Consumer Electron.
Zachary Kahleifeh, Himanshu Thapliyal, Syed M. Alam
2023 — conf
CASD-OA: Context-Aware Stress Detection for Older Adults with Machine Learning and Cortisol Biomarker.
ACM Great Lakes Symposium on VLSI
Md. Saif Hassan Onim, Himanshu Thapliyal
2023 Misc conf
GTQCP: Greedy Topology-Aware Quantum Circuit Partitioning.
QCE
Joseph Clark, Travis S. Humble, Himanshu Thapliyal
2023 — conf
Lightweight Hierarchical Root-of-Trust Framework for CAN-based 3D Printing Security.
ACM Great Lakes Symposium on VLSI
Tyler Cultice, Joseph Clark, Himanshu Thapliyal
2023 — conf
Noise-Resilient and Reduced Depth Approximate Adders for NISQ Quantum Computing.
ACM Great Lakes Symposium on VLSI
Bhaskar Gaur, Travis S. Humble, Himanshu Thapliyal
2023 J jnl
Personality is to a Conversational Agent What Perfume is to a Flower.
IEEE Consumer Electron. Mag.
Faruk Lawal Ibrahim Dutsinma, Debajyoti Pal, Pranab Roy, Himanshu Thapliyal
2023 — ed.
Proceedings of the Great Lakes Symposium on VLSI 2023, GLSVLSI 2023, Knoxville, TN, USA, June 5-7, 2023
ACM Great Lakes Symposium on VLSI
Himanshu Thapliyal, Ronald F. DeMara, Inna Partin-Vaisband, Srinivas Katkoori
2023 — conf
TDAG: Tree-based Directed Acyclic Graph Partitioning for Quantum Circuits.
ACM Great Lakes Symposium on VLSI
Joseph Clark, Travis S. Humble, Himanshu Thapliyal
2023 J jnl
Vulnerabilities and Attacks on CAN-Based 3D Printing/Additive Manufacturing.
CoRR
Tyler Cultice, Himanshu Thapliyal
2023 J jnl
What affects the usage of artificial conversational agents? An agent personality and love theory perspective.
Comput. Hum. Behav.
Debajyoti Pal, Vajirasak Vanijja, Himanshu Thapliyal, Xiangmin Zhang
2022 J jnl
2-Phase Adiabatic Logic for Low-Energy and CPA-Resistant Implantable Medical Devices.
IEEE Trans. Consumer Electron.
Amit Degada, Himanshu Thapliyal
2022 — conf
A Novel Approach to Quantum Circuit Partitioning.
ISVLSI
Joseph Clark, Himanshu Thapliyal, Travis S. Humble
2022 J jnl
Adiabatic Logic Based Energy-Efficient Security for Smart Consumer Electronics.
IEEE Consumer Electron. Mag.
Zachary Kahleifeh, Himanshu Thapliyal
2022 — conf
Adiabatic Logic-based STT-MRAM Design for IoT.
ISVLSI
Wu Yang, Amit Degada, Himanshu Thapliyal
2022 J jnl
Approximate Adiabatic Logic for Low-Power and Secure Edge Computing.
IEEE Consumer Electron. Mag.
Wu Yang, Himanshu Thapliyal
2022 J jnl
CAN Bus: The Future of Additive Manufacturing (3D Printing).
CoRR
Jun-Cheng Chin, Tyler Cultice, Himanshu Thapliyal
2022 C conf
Edge Device Based Stress Detection For Older Adults With Cortisol Biomarker.
ICCE
Joseph Clark, Himanshu Thapliyal
2022 J jnl
Fortifying Vehicular Security through Low Overhead Physically Unclonable Functions.
ACM J. Emerg. Technol. Comput. Syst.
Carson Labrado, Himanshu Thapliyal, Saraju P. Mohanty
2022 — ed.
GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6 - 8, 2022
ACM Great Lakes Symposium on VLSI
Ioannis Savidis, Avesta Sasan, Himanshu Thapliyal, Ronald F. DeMara
2022 J jnl
Guest Editorial Introduction to the Special Section on Immersive Virtual Reality Simulation for Vehicular Technology.
IEEE Trans. Veh. Technol.
Alberto Cannavò, Fabrizio Lamberti, Himanshu Thapliyal, Ruck Thawonmas
2022 J jnl
Humans in the Loop: Cybersecurity Aspects in the Consumer IoT Context.
IEEE Consumer Electron. Mag.
Rohani Rohan, Suree Funilkul, Debajyoti Pal, Himanshu Thapliyal
2022 J jnl
Machine Learning Based Stress Monitoring in Older Adults Using Wearable Sensors and Cortisol as Stress Biomarker.
J. Signal Process. Syst.
Rajdeep Kumar Nath, Himanshu Thapliyal, Allison Caban-Holt
2022 J jnl
PUF-Based Post-Quantum CAN-FD Framework for Vehicular Security.
Inf.
Tyler Cultice, Himanshu Thapliyal
2021 C conf
2-SPGAL: 2-Phase Symmetric Pass Gate Adiabatic Logic for Energy-Efficient Secure Consumer IoT.
ICCE
Amit Degada, Himanshu Thapliyal
2021 J jnl
A Review of Machine Learning Classification Using Quantum Annealing for Real-World Applications.
SN Comput. Sci.
Rajdeep Kumar Nath, Himanshu Thapliyal, Travis S. Humble
2021 J jnl
A Review of Machine Learning Classification Using Quantum Annealing for Real-world Applications.
CoRR
Rajdeep Kumar Nath, Himanshu Thapliyal, Travis S. Humble
2021 J jnl
An Integrated TRNG-PUF Architecture Based on Photovoltaic Solar Cells.
IEEE Consumer Electron. Mag.
Amit Degada, Himanshu Thapliyal
2021 C conf
Consumer Technologies for Smart Cities to Smart Villages.
ICCE
Saraju P. Mohanty, Himanshu Thapliyal, Rajnish Bajpai
2021 J jnl
Consumer Technology-Based Solutions for COVID-19.
IEEE Consumer Electron. Mag.
Himanshu Thapliyal, Katina Michael, Saraju P. Mohanty, M. B. Srinivas, Madhavi K. Ganapathiraju
2021 J jnl
EE-ACML: Energy-Efficient Adiabatic CMOS/MTJ Logic for CPA-Resistant IoT Devices.
Sensors
Zachary Kahleifeh, Himanshu Thapliyal
2021 J jnl
Exploring the Antecedents of Consumer Electronics IoT Devices Purchase Decision: A Mixed Methods Study.
IEEE Trans. Consumer Electron.
Debajyoti Pal, Vajirasak Vanijja, Xiangmin Zhang, Himanshu Thapliyal
2021 J jnl
Fortifying Vehicular Security Through Low Overhead Physically Unclonable Functions.
CoRR
Carson Labrado, Himanshu Thapliyal, Saraju P. Mohanty
2021 — conf
Low-Energy and CPA-Resistant Adiabatic CMOS/MTJ Logic for IoT Devices.
ISVLSI
Zachary Kahleifeh, Himanshu Thapliyal
2021 J jnl
Low-Energy and CPA-Resistant Adiabatic CMOS/MTJ Logic for IoT Devices.
CoRR
Zachary Kahleifeh, Himanshu Thapliyal
2021 J jnl
Machine Learning Based Anxiety Detection in Older Adults using Wristband Sensors and Context Feature.
CoRR
Rajdeep Kumar Nath, Himanshu Thapliyal
2021 — conf
Machine Learning Based Prediction of Future Stress Events in a Driving Scenario.
WF-IoT
Joseph Clark, Rajdeep Kumar Nath, Himanshu Thapliyal
2021 J jnl
Machine Learning Based Prediction of Future Stress Events in a Driving Scenario.
CoRR
Joseph Clark, Rajdeep Kumar Nath, Himanshu Thapliyal
2021 J jnl
Machine Learning-Based Anxiety Detection in Older Adults Using Wristband Sensors and Context Feature.
SN Comput. Sci.
Rajdeep Kumar Nath, Himanshu Thapliyal
2021 J jnl
Novel Secure MTJ/CMOS Logic (SMCL) for Energy-Efficient and DPA-Resistant Design.
SN Comput. Sci.
S. Dinesh Kumar, Zachary Kahleifeh, Himanshu Thapliyal
2021 J jnl
Physical Unclonable Function (PUF)-Based Sustainable Cybersecurity.
IEEE Consumer Electron. Mag.
Himanshu Thapliyal, Saraju P. Mohanty
2021 — conf
Quantum Annealing for Automated Feature Selection in Stress Detection.
ISVLSI
Rajdeep Kumar Nath, Himanshu Thapliyal, Travis S. Humble
2021 J jnl
Quantum Annealing for Automated Feature Selection in Stress Detection.
CoRR
Rajdeep Kumar Nath, Himanshu Thapliyal, Travis S. Humble
2021 J jnl
Quantum Carry Lookahead Adders for NISQ and Quantum Image Processing.
CoRR
Himanshu Thapliyal, Edgard Muñoz-Coreas, Vladislav Khalus
2021 J jnl
Quantum Circuit Designs of Integer Division Optimizing T-count and T-depth.
IEEE Trans. Emerg. Top. Comput.
Himanshu Thapliyal, Edgard Muñoz-Coreas, T. S. S. Varun, Travis S. Humble
2021 J jnl
Quantum circuit designs of carry lookahead adder optimized for T-count T-depth and qubits.
Sustain. Comput. Informatics Syst.
Himanshu Thapliyal, Edgard Muñoz-Coreas, Vladislav Khalus
2021 — conf
Smart Village: An IoT Based Digital Transformation.
WF-IoT
Amit Degada, Himanshu Thapliyal, Saraju P. Mohanty
2021 J jnl
Smart Village: An IoT Based Digital Transformation.
CoRR
Amit Degada, Himanshu Thapliyal, Saraju P. Mohanty
2021 J jnl
Smart Wristband-Based Stress Detection Framework for Older Adults With Cortisol as Stress Biomarker.
IEEE Trans. Consumer Electron.
Rajdeep Kumar Nath, Himanshu Thapliyal
2021 — conf
Wearable Health Monitoring System for Older Adults in a Smart Home Environment.
ISVLSI
Rajdeep Kumar Nath, Himanshu Thapliyal
2021 J jnl
Wearable Health Monitoring System for Older Adults in a Smart Home Environment.
CoRR
Rajdeep Kumar Nath, Himanshu Thapliyal
2020 — conf
2-Phase Energy-Efficient Secure Positive Feedback Adiabatic Logic for CPA-Resistant IoT Devices.
WF-IoT
Zachary Kahleifeh, Himanshu Thapliyal
2020 — conf
A PUF Based CAN Security Framework.
ISVLSI
Tyler Cultice, Carson Labrado, Himanshu Thapliyal
2020 C conf
Approximate Adder Circuits Using Clocked CMOS Adiabatic Logic (CCAL) for IoT Applications.
ICCE
Cole Terrell, Himanshu Thapliyal
2020 J jnl
Design of Adiabatic Logic-Based Energy-Efficient and Reliable PUF for IoT Devices.
ACM J. Emerg. Technol. Comput. Syst.
S. Dinesh Kumar, Himanshu Thapliyal
2020 J jnl
Exploration of Solar Cell Materials for Developing Novel PUFs in Cyber-Physical Systems.
SN Comput. Sci.
Carson Labrado, S. Dinesh Kumar, Riasad Badhan, Himanshu Thapliyal, Vijay Singh
2020 C conf
Harnessing Uncertainty in Photoresistor Sensor for True Random Number Generation in IoT Devices.
ICCE
Amit Degada, Himanshu Thapliyal
2020 — conf
Low-Power and Energy-Efficient Full Adders With Approximate Adiabatic Logic for Edge Computing.
ISVLSI
Wu Yang, Himanshu Thapliyal
2020 J jnl
Machine Learning Based Solutions for Real-Time Stress Monitoring.
IEEE Consumer Electron. Mag.
Rajdeep Kumar Nath, Himanshu Thapliyal, Allison Caban-Holt, Saraju P. Mohanty
2020 — conf
PPG Based Continuous Blood Pressure Monitoring Framework for Smart Home Environment.
WF-IoT
Rajdeep Kumar Nath, Himanshu Thapliyal
2020 J jnl
Quasi-Adiabatic SRAM Based Silicon Physical Unclonable Function.
SN Comput. Sci.
Yasuhiro Takahashi, Hiroki Koyasu, S. Dinesh Kumar, Himanshu Thapliyal
2020 — conf
Smart Home Sensor Anomaly Detection Using Convolutional Autoencoder Neural Network.
iSES
Tyler Cultice, Dan Ionel, Himanshu Thapliyal
2020 C conf
Special Session: A Novel Low-Power and Energy-Efficient Adiabatic Logic-In-Memory Architecture Using CMOS/MTJ.
ICCD
Himanshu Thapliyal, S. Dinesh Kumar
2020 C conf
Special Session: Quantum Carry Lookahead Adders for NISQ and Quantum Image Processing.
ICCD
Himanshu Thapliyal, Edgard Muñoz-Coreas, Vladislav Khalus
2020 J jnl
T-count and Qubit Optimized Quantum Circuit Designs of Carry Lookahead Adder.
CoRR
Himanshu Thapliyal, Edgard Muñoz-Coreas, Vladislav Khalus
2020 — conf
Technology Innovations for Smart Cities and Smart Villages.
iSES
Himanshu Thapliyal, Saraju P. Mohanty, Rajnish Bajpai
2020 C conf
Validating Physiological Stress Detection Model Using Cortisol as Stress Bio Marker.
ICCE
Rajdeep Kumar Nath, Himanshu Thapliyal, Allison Caban-Holt
2019 — conf
Approximate Energy Recovery 4-2 Compressor for Low-Power Sub-GHz IoT Applications.
ISVLSI
Himanshu Thapliyal, Zachary Kahleifeh
2019 — conf
Design of Quantum Circuits for Cryptanalysis and Image Processing Applications.
ISVLSI
Edgard Muñoz-Coreas, Himanshu Thapliyal
2019 J jnl
Design of Quantum Computing Circuits.
IT Prof.
Himanshu Thapliyal, Edgard Muñoz-Coreas
2019 J jnl
Design of a Piezoelectric-Based Physically Unclonable Function for IoT Security.
IEEE Internet Things J.
Carson Labrado, Himanshu Thapliyal
2019 J jnl
EE-SPFAL: A Novel Energy-Efficient Secure Positive Feedback Adiabatic Logic for DPA Resistant RFID and Smart Card.
IEEE Trans. Emerg. Top. Comput.
S. Dinesh Kumar, Himanshu Thapliyal, Azhar Mohammad
2019 J jnl
Emerging Paradigms in Vehicular Cybersecurity.
IEEE Consumer Electron. Mag.
Himanshu Thapliyal, Saraju P. Mohanty, Stacy J. Prowell
2019 J jnl
Hardware Security Primitives for Vehicles.
IEEE Consumer Electron. Mag.
Carson Labrado, Himanshu Thapliyal
2019 — conf
Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable Function.
ISVLSI
Yasuhiro Takahashi, Hiroki Koyasu, S. Dinesh Kumar, Himanshu Thapliyal
2019 J jnl
Quantum Circuit Design of a T-count Optimized Integer Multiplier.
IEEE Trans. Computers
Edgard Muñoz-Coreas, Himanshu Thapliyal
2019 J jnl
Quantum Computing Circuits and Devices.
IEEE Des. Test
Travis S. Humble, Himanshu Thapliyal, Edgard Muñoz-Coreas, Fahd A. Mohiyaddin, Ryan S. Bennink
2019 — conf
Solving Energy and Cybersecurity Constraints in IoT Devices Using Energy Recovery Computing.
ACM Great Lakes Symposium on VLSI
Himanshu Thapliyal, Zachary Kahleifeh
2019 J jnl
Use of Thermistor Temperature Sensors for Cyber-Physical System Security.
Sensors
Carson Labrado, Himanshu Thapliyal, Stacy J. Prowell, P. Teja Kuruganti
2018 — conf
Amazon Echo Enabled IoT Home Security System for Smart Home Environment.
iSES
Himanshu Thapliyal, Nathan Ratajczak, Ole Wendroth, Carson Labrado
2018 C conf
Energy-recovery based hardware security primitives for low-power embedded devices.
ICCE
Himanshu Thapliyal, S. Dinesh Kumar
2018 J jnl
FinSAL: FinFET-Based Secure Adiabatic Logic for Energy-Efficient and DPA Resistant IoT Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
S. Dinesh Kumar, Himanshu Thapliyal, Azhar Mohammad
2018 — conf
Hardware Trojan Detection in Implantable Medical Devices Using Adiabatic Computing.
ICRC
Zach Kahleifeh, S. Dinesh Kumar, Himanshu Thapliyal
2018 J jnl
Internet of Things-Based Consumer Electronics: Reviewing Existing Consumer Electronic Devices, Systems, and Platforms and Exploring New Research Paradigms.
IEEE Consumer Electron. Mag.
Himanshu Thapliyal
2018 C conf
IoT based indoor location detection system for smart home environment.
ICCE
Rajdeep Kumar Nath, Rajnish Bajpai, Himanshu Thapliyal
2018 C conf
Panel theme: Energy and cybersecurity constraints on consumer electronics.
ICCE
Himanshu Thapliyal
2018 J jnl
Quantum Circuit Designs of Integer Division Optimizing T-count and T-depth.
CoRR
Himanshu Thapliyal, Edgard Muñoz-Coreas, T. S. S. Varun, Travis S. Humble
2018 J jnl
Smart Home Environment for Mild Cognitive Impairment Population: Solutions to Improve Care and Quality of Life.
IEEE Consumer Electron. Mag.
Himanshu Thapliyal, Rajdeep Kumar Nath, Saraju P. Mohanty
2018 — conf
Solar Cell Based Physically Unclonable Function for Cybersecurity in IoT Devices.
ISVLSI
S. Dinesh Kumar, Carson Labrado, Riasad Badhan, Himanshu Thapliyal, Vijay Singh
2018 — conf
T-count Optimized Quantum Circuits for Bilinear Interpolation.
IGSC
Edgard Muñoz-Coreas, Himanshu Thapliyal
2018 J jnl
T-count Optimized Quantum Circuits for Bilinear Interpolation.
CoRR
Edgard Muñoz-Coreas, Himanshu Thapliyal
2018 J jnl
T-count and Qubit Optimized Quantum Circuit Design of the Non-Restoring Square Root Algorithm.
ACM J. Emerg. Technol. Comput. Syst.
Edgard Muñoz-Coreas, Himanshu Thapliyal
2018 — conf
Towards Photoplethysmogram Based Non-Invasive Blood Pressure Classification.
iSES
Rajdeep Kumar Nath, Himanshu Thapliyal, Allison Caban-Holt
2017 — conf
Adiabatic Computing Based Low-Power and DPA-Resistant Lightweight Cryptography for IoT Devices.
ISVLSI
Himanshu Thapliyal, T. S. S. Varun, S. Dinesh Kumar
2017 J jnl
Automatic synthesis of quaternary quantum circuits.
J. Supercomput.
Mozammel H. A. Khan, Himanshu Thapliyal, Edgard Muñoz-Coreas
2017 J jnl
Design exploration of a Symmetric Pass Gate Adiabatic Logic for energy-efficient and secure hardware.
Integr.
S. Dinesh Kumar, Himanshu Thapliyal, Azhar Mohammad, Kalyan S. Perumalla
2017 J jnl
Design of Efficient Reversible Logic Based Binary and BCD Adder Circuits.
CoRR
Himanshu Thapliyal, Nagarajan Ranganathan
2017 — conf
Design of Quantum Circuits for Galois Field Squaring and Exponentiation.
ISVLSI
Edgard Muñoz-Coreas, Himanshu Thapliyal
2017 J jnl
Design of Quantum Circuits for Galois Field Squaring and Exponentiation.
CoRR
Edgard Muñoz-Coreas, Himanshu Thapliyal
2017 C conf
Design of majority logic based approximate arithmetic circuits.
ISCAS
Carson Labrado, Himanshu Thapliyal, Fabrizio Lombardi
2017 J jnl
Efficient Circuit Design of Reversible Square.
Trans. Comput. Sci.
H. V. Jayashree, Himanshu Thapliyal, Vinod Kumar Agrawal
2017 J jnl
Energy-efficient magnetic 4-2 compressor.
Microelectron. J.
Himanshu Thapliyal, Azhar Mohammad, S. Dinesh Kumar, Fazel Sharifi
2017 C conf
Energy-efficient magnetic circuits based on nanoelectronic devices.
ISCAS
Fazel Sharifi, Himanshu Thapliyal
2017 Misc conf
Heuristic Based Majority/Minority Logic Synthesis for Emerging Technologies.
VLSID
Vipul Kumar Mishra, Himanshu Thapliyal
2017 — conf
Low-Power and Secure Lightweight Cryptography Via TFET-Based Energy Recovery Circuits.
ICRC
Himanshu Thapliyal, T. S. S. Varun, S. Dinesh Kumar
2017 — conf
Quantum Circuit Designs of Integer Division Optimizing T-Count and T-Depth.
iNIS
Himanshu Thapliyal, T. S. S. Varun, Edgard Muñoz-Coreas, Keith A. Britt, Travis S. Humble
2017 — conf
Security Evaluation of MTJ/CMOS Circuits Against Power Analysis Attacks.
iNIS
S. Dinesh Kumar, Himanshu Thapliyal
2017 J jnl
Stress Detection and Management: A Survey of Wearable Smart Health Devices.
IEEE Consumer Electron. Mag.
Himanshu Thapliyal, Vladislav Khalus, Carson Labrado
2017 J jnl
T-count Optimized Design of Quantum Integer Multiplication.
CoRR
Edgard Muñoz-Coreas, Himanshu Thapliyal
2017 J jnl
T-count and Qubit Optimized Quantum Circuit Design of the Non-Restoring Square Root Algorithm.
CoRR
Edgard Muñoz-Coreas, Himanshu Thapliyal
2017 — conf
UTB-SOI based adiabatic computing for low-power and secure IoT devices.
CISRC
Himanshu Thapliyal, T. S. S. Varun, S. Dinesh Kumar
2016 J jnl
A Survey of Affective Computing for Stress Detection: Evaluating technologies in stress detection for better health.
IEEE Consumer Electron. Mag.
Shalom Greene, Himanshu Thapliyal, Allison Caban-Holt
2016 J jnl
Ancilla-Input and Garbage-Output Optimized Design of a Reversible Quantum Integer Multiplier.
CoRR
H. V. Jayashree, Himanshu Thapliyal, Hamid R. Arabnia, Vinod Kumar Agrawal
2016 J jnl
Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier.
J. Supercomput.
H. V. Jayashree, Himanshu Thapliyal, Hamid R. Arabnia, Vinod Kumar Agrawal
2016 J jnl
Design Methodologies for Reversible Logic Based Barrel Shifters.
J. Circuits Syst. Comput.
Saurabh Kotiyal, Himanshu Thapliyal
2016 J jnl
Design of quaternary 4-2 and 5-2 compressors for nanotechnology.
Comput. Electr. Eng.
Fazel Sharifi, Atiyeh Panahi, Hojjat Sharifi, Keivan Navi, Nader Bagherzadeh, Himanshu Thapliyal
2016 J jnl
Design procedures and NML cost analysis of reversible barrel shifters optimizing garbage and ancilla lines.
J. Supercomput.
Himanshu Thapliyal, Carson Labrado, Ke Chen
2016 — conf
Energy-Efficient and Secure S-Box Circuit Using Symmetric Pass Gate Adiabatic Logic.
ISVLSI
S. Dinesh Kumar, Himanshu Thapliyal, Azhar Mohammad, Vijay Singh, Kalyan S. Perumalla
2016 J jnl
Erratum to: Design procedures and NML cost analysis of reversible barrel shifters optimizing garbage and ancilla lines.
J. Supercomput.
Himanshu Thapliyal, Carson Labrado, Ke Chen
2016 — conf
Exploring Human Body Communications for IoT Enabled Ambulatory Health Monitoring Systems.
iNIS
Prabha Sundaravadivel, Saraju P. Mohanty, Elias Kougianos, Venkata P. Yanambaka, Himanshu Thapliyal
2016 — conf
FinSAL: A novel FinFET based Secure Adiabatic Logic for energy-efficient and DPA resistant IoT devices.
ICRC
S. Dinesh Kumar, Himanshu Thapliyal, Azhar Mohammad
2016 — conf
IoT-Based Fall Detection for Smart Home Environments.
iNIS
Shalom Greene, Himanshu Thapliyal, David Carpenter
2016 J jnl
Mapping of Subtractor and Adder-Subtractor Circuits on Reversible Quantum Gates.
Trans. Comput. Sci.
Himanshu Thapliyal
2016 — conf
QUALPUF: A Novel Quasi-Adiabatic Logic based Physical Unclonable Function.
CISRC
S. Dinesh Kumar, Himanshu Thapliyal
2015 — conf
Design of Testable Adder Circuits for Spintronics Based Nanomagnetic Computing.
iNIS
Carson Labrado, Himanshu Thapliyal, Ronald F. DeMara
2015 — conf
Reversible Logic Based Mapping of Quaternary Sequential Circuits Using QGFSOP Expression.
ISVLSI
Mozammel H. A. Khan, Himanshu Thapliyal
2015 J jnl
Reversible logic based multiplication computing unit using binary tree data structure.
J. Supercomput.
Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
2014 Misc conf
Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits.
VLSID
Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
2014 Misc conf
Design of Dedicated Reversible Quantum Circuitry for Square Computation.
VLSID
H. V. Jayashree, Himanshu Thapliyal, Vinod Kumar Agrawal
2014 J jnl
Design of Reversible Adder-Subtractor and its Mapping in Optical Computing Domain.
Trans. Comput. Sci.
Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
2014 J jnl
Efficient reversible NOR gates and their mapping in optical computing domain.
Microelectron. J.
Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
2014 — ch.
Reversible Logic Based Design and Test of Field Coupled Nanocomputing Circuits.
Field-Coupled Nanocomputing
Himanshu Thapliyal, Nagarajan Ranganathan, Saurabh Kotiyal
2014 — ed.
Transactions on Computational Science XXIV - Special Issue on Reversible Computing
Trans. Comput. Sci.
Marina L. Gavrilova, C. J. Kenneth Tan, Himanshu Thapliyal, Nagarajan Ranganathan
2013 — conf
A new CRL gate as super class of Fredkin gate to design reversible quantum circuits.
MWSCAS
Himanshu Thapliyal, Apeksha Bhatt, Nagarajan Ranganathan
2013 J jnl
Design of Testable Reversible Sequential Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Himanshu Thapliyal, Nagarajan Ranganathan, Saurabh Kotiyal
2013 J jnl
Design of efficient reversible logic-based binary and BCD adder circuits.
ACM J. Emerg. Technol. Comput. Syst.
Himanshu Thapliyal, Nagarajan Ranganathan
2013 J jnl
Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead Adder.
Trans. Comput. Sci.
Himanshu Thapliyal, H. V. Jayashree, A. N. Nagamani, Hamid R. Arabnia
2012 — conf
Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies.
ISVLSI
Himanshu Thapliyal, Nagarajan Ranganathan
2012 — conf
Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates.
ISVLSI
Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
2012 A conf
Mach-Zehnder interferometer based design of all optical reversible binary adder.
DATE
Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
2012 Misc conf
Tutorial T2: Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future.
VLSI Design
Himanshu Thapliyal, Nagarajan Ranganathan
2011 A conf
A new reversible design of BCD adder.
DATE
Himanshu Thapliyal, N. Ranganathan
2011 — —
Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies.
Himanshu Thapliyal
2011 J jnl
Reversible Logic Based Concurrent Error Detection Methodology For Emerging Nanocircuits
CoRR
Himanshu Thapliyal, Nagarajan Ranganathan
2010 Misc conf
Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs.
VLSI Design
Himanshu Thapliyal, Nagarajan Ranganathan
2010 J jnl
Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs.
ACM J. Emerg. Technol. Comput. Syst.
Himanshu Thapliyal, Nagarajan Ranganathan
2009 C conf
Concurrently Testable FPGA Design for Molecular QCA using Conservative Reversible Logic Gate.
ISCAS
Himanshu Thapliyal, Nagarajan Ranganathan
2009 Misc conf
Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits.
VLSI Design
Himanshu Thapliyal, Nagarajan Ranganathan
2009 — conf
Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate.
ISVLSI
Himanshu Thapliyal, Nagarajan Ranganathan
2009 J jnl
Efficient Reversible Logic Design of BCD Subtractors.
Trans. Comput. Sci.
Himanshu Thapliyal, Hamid R. Arabnia, M. B. Srinivas
2007 J jnl
Combined Integer and Variable Precision (CIVP) Floating Point Multiplication Architecture for FPGAs
CoRR
Himanshu Thapliyal, Hamid R. Arabnia, Rajnish Bajpai, Kamal K. Sharma
2007 Misc conf
Combined Integer and Variable Precision (CIVP) Floating Point Multiplication Architecture for FPGAs.
PDPTA
Himanshu Thapliyal, Hamid R. Arabnia, Rajnish Bajpai, Kamal K. Sharma
2007 C conf
Design of Reversible Sequential Elements With Feasibility of Transistor Implementation.
ISCAS
Himanshu Thapliyal, A. Prasad Vinod
2007 C conf
Designing Efficient Online Testable Reversible Adders With New Reversible Gate.
ISCAS
Himanshu Thapliyal, A. Prasad Vinod
2007 J jnl
Partial Reversible Gates(PRG) for Reversible BCD Arithmetic
CoRR
Himanshu Thapliyal, Hamid R. Arabnia, Rajnish Bajpai, Kamal K. Sharma
2007 — conf
Partial Reversible Gates(PRG) for Reversible BCD Arithmetic.
CDES
Himanshu Thapliyal, Hamid R. Arabnia, Rajnish Bajpai, Kamal K. Sharma
2006 — conf
A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs.
CDES
Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia
2006 J jnl
A New Reversible TSG Gate and Its Application For Designing Efficient Adder Circuits
CoRR
Himanshu Thapliyal, M. B. Srinivas
2006 — conf
A Reversible Programmable Logic Array (RPLA) Using Fredkin and Feynman Gates for Industrial Electronics and Applications.
CDES
Himanshu Thapliyal, Hamid R. Arabnia
2006 J jnl
An Extension to DNA Based Fredkin Gate Circuits: Design of Reversible Sequential Circuits using Fredkin Gates
CoRR
Himanshu Thapliyal, M. B. Srinivas
2006 J jnl
Combined Integer and Floating Point Multiplication Architecture(CIFM) for FPGAs and Its Reversible Logic Implementation
CoRR
Himanshu Thapliyal, Hamid R. Arabnia, A. Prasad Vinod
2006 — conf
Design of Novel Reversible Carry Look-Ahead BCD Subtractor.
ICIT
Himanshu Thapliyal, Sumedha K. Gupta
2006 C conf
Low Power Hierarchical Multiplier and Carry Look-Ahead Architecture.
AICCSA
Himanshu Thapliyal, Neela Gopi, K. K. Pavan Kumar, M. B. Srinivas
2006 — conf
Modified Carry Look Ahead BCD Adder With CMOS and Reversible Logic Implementation.
CDES
Himanshu Thapliyal, Hamid R. Arabnia
2006 — conf
Modified Montgomery Modular Multiplication Using 4: 2 Compressor and CSA Adder.
DELTA
Himanshu Thapliyal, Anvesh Ramasahayam, Vivek Reddy Kotha, Kunul Gottimukkula, M. B. Srinivas
2006 J jnl
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format
CoRR
Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas
2006 Misc conf
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format.
VLSI Design
Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas
2006 — conf
Novel NAND and AND Gate Using DNA Ligation and Two Transistors Implementations.
CDES
Himanshu Thapliyal, A. Rameshwar, Rajnish Bajpai, Hamid R. Arabnia
2006 J jnl
Novel Reversible Multiplier Architecture Using Reversible TSG Gate
CoRR
Himanshu Thapliyal, M. B. Srinivas
2006 C conf
Novel Reversible Multiplier Architecture Using Reversible TSG Gate.
AICCSA
Himanshu Thapliyal, M. B. Srinivas
2006 J jnl
Novel Reversible TSG Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU
CoRR
Himanshu Thapliyal, M. B. Srinivas
2006 A conf
Novel and Efficient 4: 2 and 5: 2 Compressors with Minimum Number of Transistors Designed for Low-Power Operations.
ESA
Pallavi Devi Gopineedi, Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
2006 J jnl
Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format
CoRR
Himanshu Thapliyal, Hamid R. Arabnia, M. B. Srinivas
2006 J jnl
Reversible Logic to Cryptographic Hardware: A New Paradigm
CoRR
Himanshu Thapliyal, Mark Zwolinski
2006 J jnl
Reversible Programmable Logic Array (RPLA) using Fredkin & Feynman Gates for Industrial Electronics and Applications
CoRR
Himanshu Thapliyal, Hamid R. Arabnia
2006 — conf
The New BCD Subtractor and Its Reversible Logic Implementation.
Asia-Pacific Computer Systems Architecture Conference
Himanshu Thapliyal, M. B. Srinivas
2006 — conf
Transistor Realization of Reversible TSG Gate and Reversible Adder Architectures.
APCCAS
Himanshu Thapliyal, A. Prasad Vinod
2006 J jnl
VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics
CoRR
Himanshu Thapliyal, M. B. Srinivas
2005 A conf
A Need of Quantum Computing: Reversible Logic Synthesis of Parallel Binary Adder-Subtractor.
ESA
Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
2005 — conf
A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures.
Asia-Pacific Computer Systems Architecture Conference
Himanshu Thapliyal, M. B. Srinivas
2005 A conf
A Reversible Version of 4 x 4 Bit Array Multiplier With Minimum Gates and Garbage Outputs.
ESA
Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
2005 — conf
Design And Analysis of A VLSI Based High Performance Low Power Parallel Square Architecture.
AMCS
Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
2005 — conf
Design for A Fast And Low Power 2's Complement Multiplier.
CDES
Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
2005 — conf
Faster RSA Encryption/Decryption Architecture Using an Efficient High Speed Overlay Multiplier.
Security and Management
Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
2005 — conf
Implementation of A Fast Square In RSA Encryption/Decryption Architecture.
Security and Management
Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
2005 A conf
Reversible Logic Synthesis of Half, Full and Parallel Subtractors.
ESA
Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
2005 — conf
VLSI Implementation of O(n*n) Sorting Algorithms And Their Hardware Comparison.
CSC
Saurabh Kotiyal, Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
2005 — conf
Verilog Coding Style for Efficient Synthesis In FPGA.
CDES
Himanshu Thapliyal, M. B. Srinivas, Rameshwar Rao, Hamid R. Arabnia
2004 — conf
A Novel Parallel Multiply and Accumulate (V-MAC) Architecture Based on Ancient Indian Vedic Mathematics.
ESA/VLSI
Himanshu Thapliyal, Hamid R. Arabnia
2004 — conf
A Time-Area-Power Efficient Multiplier and Square Architecture Based on Ancient Indian Vedic Mathematics.
ESA/VLSI
Himanshu Thapliyal, Hamid R. Arabnia
2004 — conf
High Speed Efficient N Bit by N Bit Division Algorithm and Architecture Based on Ancient Indian Vedic Mathematics.
ESA/VLSI
Himanshu Thapliyal, Hamid R. Arabnia
2003 — conf
A High Speed Efficient N x N Bit Multiplier Based on Ancient Indian Vedic Mathematics.
VLSI
Vishal Verma, Himanshu Thapliyal