Himanshu Kaul - RankMe

85 papers A* 2A 3C 2Journal 23Unranked 54

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Balancing heterogeneous assembly line with multi-skilled human-robot collaboration via Adaptive cooperative co-evolutionary algorithm. Swarm Evol. Comput. Bo Tian, Himanshu Kaul, Mukund Janardhanan
2021	J	`jnl`	A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS. IEEE J. Solid State Circuits Phil C. Knag, Gregory K. Chen, Huseyin Ekin Sumbul, Raghavan Kumar, Steven K. Hsu, Amit Agarwal, Monodeep Kar, Seongjong Kim, Mark A. Anders, Himanshu Kaul, Ram K. Krishnamurthy
2021	J	`jnl`	A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS. IEEE J. Solid State Circuits Raghavan Kumar, Xiaosen Liu, Vikram B. Suresh, Harish K. Krishnamurthy, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Krishnan Ravichandran, Vivek De, Sanu K. Mathew
2020	—	`conf`	25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS. ISSCC Amit Agarwal, Steven Hsu, Simeon Realov, Mark A. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Himanshu Kaul, Sanu Mathew, Mahesh Kumashikar, Ram Krishnamurthy, Vivek De
2020	—	`conf`	25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range. ISSCC Mark A. Anders, Himanshu Kaul, Seongjong Kim, Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Monodeep Kar, Steven K. Hsu, Amit Agarwal, Vikram B. Suresh, Sanu K. Mathew, Ram K. Krishnamurthy, Vivek De
2020	—	`conf`	A 0.26% BER, 10 VLSI Circuits Vikram B. Suresh, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Vivek De, Sanu Mathew
2020	—	`conf`	A 435MHz, 2.5Mbps/W Side-Channel-Attack Resistant Crypto-Processor for Secure RSA-4K Public-Key Encryption in 14nm CMOS. VLSI Circuits Raghavan Kumar, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Vivek De, Sanu Mathew
2020	J	`jnl`	A 4900- $\mu$ m IEEE J. Solid State Circuits Raghavan Kumar, Vikram B. Suresh, Monodeep Kar, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy, Vivek De, Sanu K. Mathew
2020	—	`conf`	A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS. VLSI Circuits Phil C. Knag, Gregory K. Chen, Huseyin Ekin Sumbul, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Steven K. Hsu, Amit Agarwal, Monodeep Kar, Seongjong Kim, Ram K. Krishnamurthy
2020	—	`conf`	A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications. VLSI Circuits Monodeep Kar, Amit Agarwal, Steven Hsu, David Moloney, Gregory K. Chen, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Mark A. Anders, Himanshu Kaul, Jonathan Byrne, Luca Sarti, Ram Krishnamurthy, Vivek De
2020	—	`conf`	A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures. VLSI Circuits Raghavan Kumar, Xiaosen Liu, Vikram B. Suresh, Harish Krishnamurthy, Mark A. Anders, Himanshu Kaul, Krishnan Ravichandran, Vivek De, Sanu Mathew
2020	—	`conf`	Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS. VLSI Circuits Steven Hsu, Amit Agarwal, Simeon Realov, Mark A. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Himanshu Kaul, Vikram B. Suresh, Sanu Mathew, Iqbal Rajwani, Satish Damaraju, Ram Krishnamurthy, Vivek De
2019	—	`conf`	A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array. VLSI Circuits Sudhir Satpathy, Vikram B. Suresh, Raghavan Kumar, Vinodh Gopal, James Guilford, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De, Sanu Mathew
2019	—	`conf`	A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS. CICC Sudhir Satpathy, Vikram B. Suresh, Raghavan Kumar, Vinodh Gopal, James Guilford, Kirk Yap, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Sanu Mathew
2019	—	`conf`	A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive Platforms in 14nm CMOS. CICC Vikram B. Suresh, Sudhir Satpathy, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Sanu Mathew
2019	—	`conf`	A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking. VLSI Circuits Vikram B. Suresh, Sudhir Satpathy, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De, Sanu Mathew
2019	—	`conf`	A 4900×m VLSI Circuits Raghavan Kumar, Vikram B. Suresh, Monodeep Kar, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy, Vivek De, Sanu Mathew
2019	—	`conf`	A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS. A-SSCC Amit Agarwal, Steven Hsu, Monodeep Kar, Mark A. Anders, Himanshu Kaul, Raghavan Kumar, Vikram B. Suresh, Sanu Mathew, Ram Krishnamurthy, Vivek De
2019	—	`conf`	A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS. VLSI Circuits Steven Hsu, Amit Agarwal, Monodeep Kar, Mark A. Anders, Himanshu Kaul, Raghavan Kumar, Sudhir Satpathy, Vikram B. Suresh, Sanu Mathew, Ram Krishnamurthy, Vivek De
2019	J	`jnl`	An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS. IEEE J. Solid State Circuits Sudhir Satpathy, Sanu K. Mathew, Raghavan Kumar, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram K. Krishnamurthy, Vivek De
2019	C	`conf`	Optimized Fused Floating-Point Many-Term Dot-Product Hardware for Machine Learning Accelerators. ARITH Himanshu Kaul, Mark A. Anders, Sanu Mathew, Seongjong Kim, Ram Krishnamurthy
2018	—	`conf`	2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS. VLSI Circuits Mark A. Anders, Himanshu Kaul, Sanu Mathew, Vikram B. Suresh, Sudhir Satpathy, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
2018	—	`conf`	220MV-900MV 794/584/754 GBPS/W Reconfigurable GF(2 VLSI Circuits Sudhir Satpathy, Vikram B. Suresh, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
2018	—	`conf`	34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms. ESSCIRC Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Vinodh Gopal, James Guilford, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Kam Krisnnamurthy
2018	—	`conf`	A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS. ESSCIRC Vikram B. Suresh, Sudhir Satpathy, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
2018	—	`conf`	A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS. A-SSCC Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Vinodh Gopal, James Guilford, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
2018	—	`conf`	An All-Digital Unified Static/Dynamic Entropy Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving Mutual Authentication in IoT Mote Platforms. VLSI Circuits Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De
2018	J	`jnl`	MetaXplorer: an intelligent and adaptable metasearch engine using a novel ordered weighted averaging operator. Int. J. Syst. Assur. Eng. Manag. Neha Dimri, Himanshu Kaul, Daya Gupta
2018	—	`conf`	Ultra-Lightweight 548-1080 Gate 166Gbps/W-12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS. A-SSCC Himanshu Kaul, Mark A. Anders, Sanu Mathew, Vikram B. Suresh, Sudhir Satpathy, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
2017	J	`jnl`	A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS. IEEE J. Solid State Circuits Sudhir Satpathy, Sanu K. Mathew, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy, Vivek K. De
2016	—	`conf`	14.4 A 21.5M-query-vectors/s 3.37nJ/vector reconfigurable k-nearest-neighbor accelerator with adaptive precision in 14nm tri-gate CMOS. ISSCC Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Gregory K. Chen, Sudhir Satpathy, Steven Hsu, Amit Agarwal, Ram Krishnamurthy
2016	—	`conf`	250mV-950mV 1.1Tbps/W double-affine mapped Sbox based composite-field SMS4 encrypt/decrypt accelerator in 14nm tri-gate CMOS. VLSI Circuits Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy
2016	—	`conf`	A 305mV-850mV 400μW 45GSamples/J reconfigurable compressive sensing engine with early-termination for ultra-low energy target detection in 14nm tri-gate CMOS. A-SSCC Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Mark A. Anders, Gregory K. Chen, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De
2016	—	`conf`	A 350mV-900mV 2.1GHz 0.011mm VLSI Circuits Amit Agarwal, Steven Hsu, Mark A. Anders, Sanu Mathew, Gregory K. Chen, Himanshu Kaul, Sudhir Satpathy, Ram Krishnamurthy
2016	—	`conf`	A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS. VLSI Circuits Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy, Vivek De
2016	J	`jnl`	µRNG: A 300-950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS. IEEE J. Solid State Circuits Sanu K. Mathew, David Johnston, Sudhir Satpathy, Vikram B. Suresh, Paul Newman, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy
2015	J	`jnl`	340 mV-1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy
2015	J	`jnl`	A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Vivek De, Shekhar Borkar
2015	J	`jnl`	Investigating biocomplexity through the agent-based paradigm. Briefings Bioinform. Himanshu Kaul, Yiannis Ventikos
2015	—	`conf`	μRNG: A 300-950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS. ESSCIRC Sanu Mathew, David Johnston, Paul Newman, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Gregory K. Chen, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
2014	—	`conf`	13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22nm tri-gate CMOS. ESSCIRC Sudhir Satpathy, Sanu Mathew, Jiangtao Li, Patrick Koeberl, Mark A. Anders, Himanshu Kaul, Gregory K. Chen, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
2014	—	`conf`	16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS. ISSCC Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven K. Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar, Vivek De
2014	—	`conf`	16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS. ISSCC Sanu K. Mathew, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Steven K. Hsu, Amit Agarwal, Gregory K. Chen, Rachael J. Parker, Ram K. Krishnamurthy, Vivek De
2014	—	`conf`	340mV-1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt GF(2 VLSIC Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Himanshu Kaul, Mark A. Anders, Gregory K. Chen, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
2013	J	`jnl`	A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS. IEEE J. Solid State Circuits Farhana Sheikh, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar
2013	J	`jnl`	A 280 mV-to-1.1 V 256b Reconfigurable SIMD Vector Permutation Engine With 2-Dimensional Shuffle in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits Steven Hsu, Amit Agarwal, Mark A. Anders, Sanu Mathew, Himanshu Kaul, Farhana Sheikh, Ram K. Krishnamurthy
2012	J	`jnl`	2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors. IEEE J. Solid State Circuits Sanu Mathew, Suresh Srinivasan, Mark A. Anders, Himanshu Kaul, Steven Hsu, Farhana Sheikh, Amit Agarwal, Sudhir Satpathy, Ram Krishnamurthy
2012	—	`conf`	A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS. ISSCC Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar
2012	—	`conf`	A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS. ISSCC Farhana Sheikh, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar
2012	—	`conf`	A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS. VLSIC Steven Hsu, Amit Agarwal, Mark A. Anders, Himanshu Kaul, Sanu Mathew, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar
2012	—	`conf`	A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS. ESSCIRC Amit Agarwal, Steven Hsu, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Farhana Sheikh, Ram Krishnamurthy
2012	—	`conf`	A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22nm CMOS. ISSCC Steven Hsu, Amit Agarwal, Mark A. Anders, Sanu Mathew, Himanshu Kaul, Farhana Sheikh, Ram Krishnamurthy
2012	A*	`conf`	Near-threshold voltage (NTV) design: opportunities and challenges. DAC Himanshu Kaul, Mark A. Anders, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar
2011	J	`jnl`	53 Gbps Native GF(2 IEEE J. Solid State Circuits Sanu Mathew, Farhana Sheikh, Michael E. Kounavis, Shay Gueron, Amit Agarwal, Steven Hsu, Himanshu Kaul, Mark A. Anders, Ram Krishnamurthy
2011	—	`conf`	A 128×128b high-speed wide-and match-line content addressable memory in 32nm CMOS. ESSCIRC Amit Agarwal, Steven Hsu, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Farhana Sheikh, Ram Krishnamurthy
2011	J	`jnl`	A Robust Edge Encoding Technique for Energy-Efficient Multi-Cycle Interconnect. IEEE Trans. Very Large Scale Integr. Syst. Jae-sun Seo, Himanshu Kaul, Ram Krishnamurthy, Dennis Sylvester, David T. Blaauw
2011	—	`ch.`	Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections. Low Power Networks-on-Chip Mark A. Anders, Himanshu Kaul, Ram K. Krishnamurthy, Shekhar Y. Borkar
2010	—	`conf`	18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS. ESSCIRC Rajaraman Ramanarayanan, Sanu Mathew, Farhana Sheikh, Suresh Srinivasan, Amit Agarwal, Steven Hsu, Himanshu Kaul, Mark A. Anders, Vasantha Erraguntla, Ram Krishnamurthy
2010	—	`conf`	3GHz, 74mW 2-level Karatsuba 64b Galois field multiplier for public-key encryption acceleration in 45nm CMOS. ESSCIRC Sanu Mathew, Michael E. Kounavis, Farhana Sheikh, Steven Hsu, Amit Agarwal, Himanshu Kaul, Mark A. Anders, Frank L. Berry, Ram Krishnamurthy
2010	J	`jnl`	A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS. IEEE J. Solid State Circuits Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar
2010	—	`conf`	A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS. ISSCC Amit Agarwal, Sanu Mathew, Steven Hsu, Mark A. Anders, Himanshu Kaul, Farhana Sheikh, Rajaraman Ramanarayanan, Suresh Srinivasan, Ram Krishnamurthy, Shekhar Borkar
2010	—	`conf`	A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS. ISSCC Mark A. Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Sanu Mathew, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar
2009	—	`conf`	A 300mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 45nm CMOS. ISSCC Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar
2009	J	`jnl`	A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS. IEEE J. Solid State Circuits Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Steven Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar
2008	—	`conf`	A 2.9Tb/s 8W 64-core circuit-switched network-on-chip in 45nm CMOS. ESSCIRC Mark A. Anders, Himanshu Kaul, Martin Hansson, Ram Krishnamurthy, Shekhar Borkar
2008	—	`conf`	A 320mV 56μW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS. ISSCC Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar
2008	C	`conf`	A robust alternate repeater technique for high performance busses in the multi-core era. ISCAS Himanshu Kaul, Jae-sun Seo, Mark A. Anders, Dennis Sylvester, Ram Krishnamurthy
2007	A	`conf`	A robust edge encoding technique for energy-efficient multi-cycle interconnect. ISLPED Jae-sun Seo, Dennis Sylvester, David T. Blaauw, Himanshu Kaul, Ram Krishnamurthy
2007	J	`jnl`	DVS for On-Chip Bus Designs Based on Timing Error Correction CoRR Himanshu Kaul, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge, Todd M. Austin
2006	—	`conf`	A Low-swing Signaling Circuit Technique for 65nm On-chip Interconnects. SoCC Vishak Venkatraman, Mark A. Anders, Himanshu Kaul, Wayne P. Burleson, Ram Krishnamurthy
2005	—	`conf`	A 2GHz 13.6mW 12 × 9b multiplier for energy efficient FFT accelerators. ESSCIRC Steven Hsu, Vishak Venkatraman, Sanu Mathew, Himanshu Kaul, Mark A. Anders, Saurabh Dighe, Wayne P. Burleson, Ram Krishnamurthy
2005	—	`conf`	A novel buffer circuit for energy efficient signaling in dual-VDD systems. ACM Great Lakes Symposium on VLSI Himanshu Kaul, Dennis Sylvester
2005	A	`conf`	DVS for On-Chip Bus Designs Based on Timing Error Correction. DATE Himanshu Kaul, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge, Todd M. Austin
2005	J	`jnl`	Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses. IEEE Trans. Very Large Scale Integr. Syst. Himanshu Kaul, Dennis Sylvester, Mark A. Anders, Ram Krishnamurthy
2005	—	`conf`	High-Performance On-Chip Interconnect Circuit Technologies for sub-65nm CMOS. SoCC Himanshu Kaul
2005	—	`conf`	Power-aware global signaling strategies. ISCAS (1) Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif
2004	J	`jnl`	Low-power on-chip communication based on transition-aware global signaling (TAGS). IEEE Trans. Very Large Scale Integr. Syst. Himanshu Kaul, Dennis Sylvester
2004	J	`jnl`	Performance optimization of critical nets through active shielding. IEEE Trans. Circuits Syst. I Regul. Pap. Himanshu Kaul, Dennis Sylvester, David T. Blaauw
2004	A	`conf`	Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses. ISLPED Himanshu Kaul, Dennis Sylvester, Mark A. Anders, Ram Krishnamurthy
2003	—	`conf`	Clock net optimization using active shielding. ESSCIRC Himanshu Kaul, Dennis Sylvester, David T. Blaauw
2002	—	`conf`	Active shielding of RLC global interconnects. Timing Issues in the Specification and Synthesis of Digital Systems Himanshu Kaul, Dennis Sylvester, David T. Blaauw
2002	—	`conf`	Active shields: a new approach to shielding global wires. ACM Great Lakes Symposium on VLSI Himanshu Kaul, Dennis Sylvester, David T. Blaauw
2002	—	`conf`	Transition Aware Global Signaling (TAGS). ISQED Himanshu Kaul, Dennis Sylvester
2001	A*	`conf`	Future Performance Challenges in Nanometer Design. DAC Dennis Sylvester, Himanshu Kaul
2001	J	`jnl`	Power-Driven Challenges in Nanometer Design. IEEE Des. Test Comput. Dennis Sylvester, Himanshu Kaul