Himadri Singh Raghav

14 papers C 2Journal 4Unranked 8
YearRankTypeTitle / Venue / Authors
2025 — conf
Dealing with Non-Idealities of Power-Clock Generation for Adiabatic Systems.
ICECS
Himadri Singh Raghav, Sachin Maheshwari, Mike Smart, Themis Prodromakis, Alexander Serb
2025 C conf
Low Offset, High-Resolution Threshold Logic Design in 22nm FDSOI.
ISCAS
Himadri Singh Raghav, Sachin Maheshwari, Mike Smart, Alexander Serb
2025 C conf
The Adiabatic Capacitive Neuron: A Cross CMOS Technology Performance Comparison.
ISCAS
Himadri Singh Raghav, Mike Smart, Sachin Maheshwari, Alexander Serb
2025 J jnl
Weight Mapping Properties of a Dual Tree Single Clock Adiabatic Capacitive Neuron.
CoRR
Mike Smart, Sachin Maheshwari, Himadri Singh Raghav, Alexander Serb
2022 — conf
Fully-Digital Broadband Calibration-Less Impedance Monitor for Probe Insertion Detection against Power Analysis Attacks.
VLSI Technology and Circuits
Viveka Konandur Rajanna, Himadri Singh Raghav, Tianqi Wang, Massimo Alioto
2020 J jnl
Investigating the influence of adiabatic load on the 4-phase adiabatic system design.
Integr.
Himadri Singh Raghav, V. A. Bartlett
2019 J jnl
A balanced power analysis attack resilient adiabatic logic using single charge sharing transistor.
Integr.
Himadri Singh Raghav, Izzet Kale
2018 J jnl
Investigating the effectiveness of Without Charge-Sharing Quasi-Adiabatic Logic for energy efficient and secure cryptographic implementations.
Microelectron. J.
Himadri Singh Raghav, Vivian A. Bartlett, Izzet Kale
2018 — conf
Symmetric Power Analysis Attack Resilient Adiabatic Logic for Smartcard Applications.
PATMOS
Himadri Singh Raghav, Vivian A. Bartlett, Izzet Kale
2017 — conf
A novel power analysis attack resilient adiabatic logic without charge sharing.
ECCTD
Himadri Singh Raghav, Vivian A. Bartlett, Izzet Kale
2017 — conf
Robustness of power analysis attack resilient adiabatic logic: WCS-QuAL under PVT variations.
PATMOS
Himadri Singh Raghav, Vivian A. Bartlett, Izzet Kale
2016 — conf
Energy efficiency of 2-step charging power-clock for adiabatic logic.
PATMOS
Himadri Singh Raghav, Vivian A. Bartlett, Izzet Kale
2013 — conf
Characterization of Logical Effort for Improved Delay.
VDAT
Sachin Maheshwari, Himadri Singh Raghav, Anu Gupta
2013 — conf
Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for Worst-Case-Delay and Power in Sub-micron Technology.
VDAT
Himadri Singh Raghav, Sachin Maheshwari, B. Prasad Singh