Hideyuki Ozaki

16 papers A 1Journal 15

Year	Rank	Type	Title / Venue / Authors
2005	J	`jnl`	A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros. IEICE Trans. Electron. Akira Yamazaki, Fukashi Morishita, Naoya Watanabe, Teruhiko Amano, Masaru Haraguchi, Hideyuki Noda, Atsushi Hachisuka, Katsumi Dosaka, Kazutami Arimoto, Setsuo Wake, Hideyuki Ozaki, Tsutomu Yoshihara
2003	J	`jnl`	A Low Power Embedded DRAM Macro for Battery-Operated LSIs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takeshi Fujino, Akira Yamazaki, Yasuhiko Taito, Mitsuya Kinoshita, Fukashi Morishita, Teruhiko Amano, Masaru Haraguchi, Makoto Hatakenaka, Atsushi Amo, Atsushi Hachisuka, Kazutami Arimoto, Hideyuki Ozaki
2001	J	`jnl`	Design methodology of embedded DRAM with virtual-socket architecture. IEEE J. Solid State Circuits Tadaaki Yamauchi, Mitsuya Kinoshita, Teruhiko Amano, Katsumi Dosaka, Kazutami Arimoto, Hideyuki Ozaki, Michihiro Yamada, Tsutomu Yoshihara
2000	J	`jnl`	A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica. IEEE J. Solid State Circuits Shigehiro Kuge, Tetsuo Kato, Kiyohiro Furutani, Shigeru Kikuda, Katsuyoshi Mitsui, Takeshi Hamamoto, Jun Setogawa, Kei Hamade, Yuichiro Komiya, Satoshi Kawasaki, Takashi Kono, Teruhiko Amano, Takashi Kubo, Masaru Haraguchi, Yoshito Nakaoka, Mihoko Akiyama, Yasuhiro Konishi, Hideyuki Ozaki, Tsutomu Yoshihara
2000	J	`jnl`	A precharged-capacitor-assisted sensing (PCAS) scheme with novel level controllers for low-power DRAMs. IEEE J. Solid State Circuits Takashi Kono, Takeshi Hamamoto, Katsuyoshi Mitsui, Yasuhiro Konishi, Tsutomu Yoshihara, Hideyuki Ozaki
2000	J	`jnl`	High-performance embedded SOI DRAM architecture for the low-power supply. IEEE J. Solid State Circuits Tadaaki Yamauchi, Fukashi Morishita, Shigenobu Maeda, Kazutami Arimoto, Kazuyasu Fujishima, Hideyuki Ozaki, Tsutomu Yoshihara
1998	J	`jnl`	400-MHz random column operating SDRAM techniques with self-skew compensation. IEEE J. Solid State Circuits Takeshi Hamamoto, Masaki Tsukude, Kazutami Arimoto, Yasuhiro Konishi, Takayuki Miyamoto, Hideyuki Ozaki, Michihiro Yamada
1996	J	`jnl`	A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for AS-Memory. IEEE J. Solid State Circuits Tadaaki Yamauchi, Yoshikazu Morooka, Hideyuki Ozaki
1996	J	`jnl`	A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories. IEEE J. Solid State Circuits Tsukasa Ooishi, Yuichiro Komiya, Kei Hamade, Mikio Asakura, Kenichi Yasuda, Kiyohiro Furutani, Tetsuo Kato, Hideto Hidaka, Hideyuki Ozaki
1996	J	`jnl`	Cell-plate-line/bit-line complementary sensing (CBCS) architecture for ultra low-power DRAMs. IEEE J. Solid State Circuits Takeshi Hamamoto, Yoshikazu Maroaka, Mikio Asakura, Hideyuki Ozaki
1995	J	`jnl`	An automatic temperature compensation of internal sense ground for subquarter micron DRAM's. IEEE J. Solid State Circuits Tsukasa Ooishi, Yuichiro Komiya, Kei Hamade, Mho Asakura, Kenichi Yasuda, Kiyohiro Furutani, Hideto Hidaka, Hiroshi Miyamoto, Hideyuki Ozaki
1994	J	`jnl`	An adjustable output driver with a self-recovering Vpp generator for a 4M⨉16 DRAM. IEEE J. Solid State Circuits Kiyohiro Furutani, Hiroshi Miyamoto, Yoshikazu Morooka, Makoto Suwa, Hideyuki Ozaki
1994	J	`jnl`	An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs. IEEE J. Solid State Circuits Yasuhiko Tsukikawa, Takeshi Kajimoto, Yasuhiko Okasaka, Yoshikazu Morooka, Kiyohiro Furutani, Hiroshi Miyamoto, Hideyuki Ozaki
1992	J	`jnl`	A 288-kb fully parallel content addressable memory using a stacked-capacitor cell structure. IEEE J. Solid State Circuits Tadato Yamagata, Masaaki Mihara, Takeshi Hamamoto, Yasumitsu Murai, Toshifumi Kobayashi, Michihiro Yamada, Hideyuki Ozaki
1989	J	`jnl`	A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode. IEEE J. Solid State Circuits Yasumasa Nishimura, Mitsuhiro Hamada, Hideto Hidaka, Hideyuki Ozaki, Kazuyasu Fujishima
1986	A	`conf`	Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode. ITC Yasumasa Nishimura, Mitsuhiro Hamada, Hideto Hidaka, Hideyuki Ozaki, Kazuyasu Fujishima, Y. Hayasaka