Hideyuki Noda

26 papers C 1Journal 18Unranked 7
YearRankTypeTitle / Venue / Authors
2019 J jnl
A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications.
IEICE Trans. Electron.
Masanori Hayashikoshi, Hiroaki Tanizaki, Yasumitsu Murai, Takaharu Tsuji, Kiyoshi Kawabata, Koji Nii, Hideyuki Noda, Hiroyuki Kondo, Yoshio Matsuda, Hideto Hidaka
2018 J jnl
Low-Power Multi-Sensor System with Power Management and Nonvolatile Memory Access Control for IoT Applications.
IEEE Trans. Multi Scale Comput. Syst.
Masanori Hayashikoshi, Hideyuki Noda, Hiroyuki Kawai, Yasumitsu Murai, Sugako Otani, Koji Nii, Yoshio Matsuda, Hiroyuki Kondo
2017 — conf
3.5 A 40nm flash microcontroller with 0.80µs field-oriented-control intelligent motor timer and functional safety system for next-generation EV/HEV.
ISSCC
Hayato Kimura, Hideyuki Noda, Hisaaki Watanabe, Takashi Higuchi, Ryosaku Kobayashi, Masayuki Utsuno, Fumitake Takami, Sugako Otani, Masayuki Ito, Yasuhisa Shimazaki, Naoki Yada, Hiroyuki Kondo
2017 — conf
Low-power multi-sensor system with task scheduling and autonomous standby mode transition control for IoT applications.
COOL Chips
Masanori Hayashikoshi, Hideyuki Noda, Hiroyuki Kawai, Koji Nii, Hiroyuki Kondo
2016 — conf
Low-power multi-sensor system with normally-off sensing technology for IoT applications.
ISOCC
Masanori Hayashikoshi, Hideyuki Noda, Hiroyuki Kawai, Hiroyuki Kondo
2013 J jnl
A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS.
IEEE J. Solid State Circuits
Isamu Hayashi, Teruhiko Amano, Naoya Watanabe, Yuji Yano, Yasuto Kuroda, M. Shirata, Katsumi Dosaka, Koji Nii, Hideyuki Noda, Hiroyuki Kawai
2011 J jnl
A Scalable Massively Parallel Processor for Real-Time Image Processing.
IEEE J. Solid State Circuits
Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Tetsu Nishijima, Tetsushi Tanizaki, Hiroyuki Yamasaki, Takeaki Sugimura, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Kan Murata, Kanako Yoshida, Eisuke Shimomura, Hideyuki Noda, Yoshihiro Okuno, Shunsuke Kamijo, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto
2008 J jnl
Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor.
IEICE Trans. Electron.
Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
2007 J jnl
A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI.
IEICE Trans. Electron.
Fukashi Morishita, Hideyuki Noda, Isamu Hayashi, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto
2007 J jnl
A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory.
IEEE J. Solid State Circuits
Fukashi Morishita, Isamu Hayashi, Takayuki Gyohten, Hideyuki Noda, Takashi Ipposhi, Hiroki Shimano, Katsumi Dosaka, Kazutami Arimoto
2007 J jnl
Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor.
IEICE Trans. Inf. Syst.
Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
2007 C conf
Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine.
ISCAS
Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
2007 J jnl
Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer.
IEICE Trans. Inf. Syst.
Takeshi Kumaki, Yasuto Kuroda, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
2007 J jnl
The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture.
IEEE J. Solid State Circuits
Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten, Katsumi Dosaka, Masami Nakajima, Katsuya Mizumoto, Kanako Yoshida, Takenobu Iwao, Tetsu Nishijima, Yoshihiro Okuno, Kazutami Arimoto
2007 J jnl
The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture.
IEEE J. Solid State Circuits
Hideyuki Noda, Masami Nakajima, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Tetsushi Tanizaki, Takayuki Gyohten, Yoshihiro Okuno, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saito, Toru Shimizu
2006 — conf
A 40GOPS 250mW massively parallel processor based on matrix architecture.
ISSCC
Masami Nakajima, Hideyuki Noda, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saitoh, Toru Shimizu
2006 J jnl
A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC.
IEICE Trans. Electron.
Hideyuki Noda, Katsumi Dosaka, Hans Jürgen Mattausch, Tetsushi Koide, Fukashi Morishita, Kazutami Arimoto
2006 J jnl
An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design.
IEICE Trans. Electron.
Takayuki Gyohten, Fukashi Morishita, Isamu Hayashi, Mako Okamoto, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Yasutaka Horiba
2005 J jnl
A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications.
IEEE J. Solid State Circuits
Fukashi Morishita, Isamu Hayashi, Hideto Matsuoka, Kazuhiro Takahashi, Kuniyasu Shigeta, Takayuki Gyohten, Mitsutaka Niiro, Hideyuki Noda, Mako Okamoto, Atsushi Hachisuka, Atsushi Amo, Hiroki Shinkawata, Tatsuo Kasaoka, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
2005 J jnl
A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features.
IEICE Trans. Electron.
Kazunari Inoue, Hideyuki Noda, Kazutami Arimoto, Hans Jürgen Mattausch, Tetsushi Koide
2005 J jnl
A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros.
IEICE Trans. Electron.
Akira Yamazaki, Fukashi Morishita, Naoya Watanabe, Teruhiko Amano, Masaru Haraguchi, Hideyuki Noda, Atsushi Hachisuka, Katsumi Dosaka, Kazutami Arimoto, Setsuo Wake, Hideyuki Ozaki, Tsutomu Yoshihara
2005 — conf
A capacitorless twin-transistor random access memory (TTRAM) on SOI.
CICC
Fukashi Morishita, Hideyuki Noda, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto
2005 J jnl
A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture.
IEEE J. Solid State Circuits
Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
2005 — conf
A soft-error-immune maintenance-free TCAM architecture with associated embedded DRAM.
CICC
Hideyuki Noda, Katsumi Dosaka, Fukashi Morishita, Kazutami Arimoto
2005 — conf
CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example].
ISCAS (5)
Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
2005 J jnl
Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh.
IEICE Trans. Electron.
Hideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara