Hidetsugu Irie

81 papers A* 3A 3B 4C 13Misc 10Journal 16Unranked 32
YearRankTypeTitle / Venue / Authors
2026 J jnl
Inspex: Speculative Execution of Ready-to-Execute Loads in In-Order Cores.
IEEE Comput. Archit. Lett.
Yotaro Nada, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
2026 B conf
Position Estimation Method Using Compact Magnetic Resonant Coupled Coils for Shape-Changing User Interfaces.
TEI
Kenta Higuchi, Masato Goto, Junichiro Kadomoto, Hidetsugu Irie
2025 B conf
Biotite: A High-Performance Static Binary Translator using Source-Level Information.
CC
Changbin Chen, Shu Sugita, Yotaro Nada, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
2025 — conf
Demonstration of MorphKeys: A Reconfigurable Keyboard System Using Switched NFC Tags.
UIST Adjunct
Koki Yamagami, Masato Goto, Junichiro Kadomoto, Hidetsugu Irie
2025 C conf
Design of an Online Surface Code Decoder Using Union-Find Algorithm.
ICCD
Takuya Kasamura, Junichiro Kadomoto, Hidetsugu Irie
2025 J jnl
Enhancing GPU Performance Through Complexity-Effective Out-of-Order Execution Using Distance-Based ISA.
IEICE Trans. Inf. Syst.
Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
2025 J jnl
Flexible Approximate Computing for Mitigating Branch Divergence in GPUs.
IEEE Micro
Reoma Matsuo, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
2025 A* conf
MorphKeys: A Reconfigurable Keyboard System Using Switched NFC Tags.
UIST
Koki Yamagami, Masato Goto, Junichiro Kadomoto, Hidetsugu Irie
2025 — conf
PixelBricks: Shape-Changing User Interface System with Interconnected Display Cubes.
UIST Adjunct
Koshiro Fujikawa, Junichiro Kadomoto, Hidetsugu Irie
2025 — conf
ReconSkin: Shape-Configurable Robotic Skin Utilizing Wireless Networked Sensor Nodes.
CHI Extended Abstracts
Masato Goto, Ibuki Sugiyama, Junichiro Kadomoto, Hidetsugu Irie, Yoshio Mita
2025 C conf
Register Bridging: A Lightweight Microarchitectural Approach for Skipping Overhead Instructions in Distance-Based ISA Processors.
ICCD
Fan Yang, Toru Koizumi, Jun Li, Shu Sugita, Yuriko Yamauchi, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie
2025 — conf
VisMorph: A Live Programming Environment for Shape-Adaptive Computers.
UIST Adjunct
Yusuke Izawa, Junichiro Kadomoto, Hidetsugu Irie
2024 — conf
A Convenient Approach for Lane-Level Congestion Detection with On-Board Camera Images and Vehicle Data.
ITSC
Hiroki Taniai, Yusuke Yamaura, Shintaro Fukushima, Junichiro Kadomoto, Hidetsugu Irie
2024 — conf
A Dynamic Approximation Processor Based on Out-of-Order RISC-V in 28-nm CMOS.
APCCAS
Tomohiro Yoshita, Junichiro Kadomoto, Hidetsugu Irie
2024 — conf
A Wireless Data and Power Transfer-Enabled MCU for Shape-Configurable Chiplet-Based Computers.
APCCAS
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2024 — conf
Branch Divergence-Aware Flexible Approximating Technique on GPUs.
COOL CHIPS
Reoma Matsuo, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
2024 — conf
CommuTiles: Shape-Changeable Modular Computer System Using Proximity Wireless Communication.
CHI Extended Abstracts
Masato Goto, Ibuki Sugiyama, Kenta Higuchi, Toshiki Goto, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2024 J jnl
Cycle-Oriented Dynamic Approximation: Architectural Framework to Meet Performance Requirements.
IEEE Comput. Archit. Lett.
Yuya Degawa, Shota Suzuki, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2024 — conf
DataPipettor: Touch-Based Information Transfer Interface Using Proximity Wireless Communication.
UIST (Adjunct Volume)
Shoi To, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2024 C conf
Designing a Reactive Programming Language for Shape-Adaptive Computers.
APSEC
Yusuke Izawa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2024 — conf
Multi-Tree Network Protocol Enabling System Partitioning for Shape-Changeable Computer System.
CF
Shun Nagasaki, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2024 Misc conf
Preliminary Design Space Exploration for ASIC Implementation of Control Systems in Fault-Tolerant Quantum Computers.
QCE
Junichiro Kadomoto, Takuya Kasamura, Hidetsugu Irie
2024 J jnl
TURBULENCE: Complexity-Effective Out-of-Order Execution on GPU With Distance-Based ISA.
IEEE Comput. Archit. Lett.
Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
2023 — conf
A Functional Reactive Programming Language for Wirelessly Connected Shape-Changeable Chiplet-Based Computers.
SPLASH Companion
Yusuke Izawa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2023 J jnl
A Principal Factor of Performance in Decoupled Front-End.
IEICE Trans. Inf. Syst.
Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2023 B conf
A Sound and Complete Algorithm for Code Generation in Distance-Based ISA.
CC
Shu Sugita, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
2023 C conf
An Out-of-Order Superscalar Processor Using STRAIGHT Architecture in 28 nm CMOS.
ISCAS
Taichi Amano, Junichiro Kadomoto, Satoshi Mitsuno, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
2023 A* conf
Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors.
MICRO
Toru Koizumi, Ryota Shioya, Shu Sugita, Taichi Amano, Yuya Degawa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2023 J jnl
Dynamically Reconfigurable Network Protocol for Shape-Changeable Computer System.
IEEE Des. Test
Shun Nagasaki, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2023 J jnl
FPGA-based Garbling Accelerator with Parallel Pipeline Processing.
IEICE Trans. Inf. Syst.
Rin Oishi, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2023 Misc conf
Poster Abstract: Investigation of Distance Sensing Method Using Magnetic Resonant Coupled Coils for Deformable User Interfaces.
SenSys
Kenta Higuchi, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2023 Misc conf
Poster Abstract: Towards a Tiny Digital Displacement Sensor Utilizing Bit-Error Characteristics of Inter-Chip Wireless Bus.
SenSys
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2023 A conf
TURBULENCE: Complexity-effective Out-of-order Execution on GPU with Distance-based ISA.
DATE
Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
2023 — conf
iKnowde: Interactive Learning Path Generation System Based on Knowledge Dependency Graphs.
UIST (Adjunct Volume)
Takashi Murayama, Shu Sugita, Hiroyuki Saegusa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2022 — conf
Deformable Chiplet-Based Computer Using Inductively Coupled Wireless Communication.
ASP-DAC
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2022 — conf
Evaluation of Different Microarchitectures for Energy-Efficient RISC-V Cores.
MCSoC
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2022 A conf
T-SKID: Predicting When to Prefetch Separately from Address Prediction.
DATE
Toru Koizumi, Tomoki Nakamura, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
2021 C conf
Accurate and Fast Performance Modeling of Processors with Decoupled Front-end.
ICCD
Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2021 C conf
Compiling and Optimizing Real-world Programs for STRAIGHT ISA.
ICCD
Toru Koizumi, Shu Sugita, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2021 — conf
Multiport Register File Design for High-Performance Embedded Cores.
MCSoC
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2021 C conf
Stochastic Iterative Approximation: Software/hardware techniques for adjusting aggressiveness of approximation.
ICCD
Tomoki Nakamura, Kazutaka Tomida, Shouta Kouno, Hidetsugu Irie, Shuichi Sakai
2021 J jnl
Toward Wirelessly Cooperated Shape-Changing Computing Particles.
IEEE Pervasive Comput.
Junichiro Kadomoto, Takuya Sasatani, Koya Narumi, Naoto Usami, Hidetsugu Irie, Shuichi Sakai, Yoshihiro Kawahara
2020 B conf
A High-Performance Out-of-Order Soft Processor Without Register Renaming.
FPL
Satoshi Mitsuno, Junichiro Kadomoto, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
2020 — conf
A RISC-V Processor with an Inter-Chiplet Wireless Communication Interface for Shape-Changeable Computers.
COOL CHIPS
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2020 — conf
A Self-Sensing Technique Using Inductively-Coupled Coils for Deformable User Interfaces.
AsianCHI@CHI
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2020 — conf
An Inductively Coupled Wireless Bus for Chiplet-Based Systems.
ASP-DAC
Junichiro Kadomoto, Satoshi Mitsuno, Hidetsugu Irie, Shuichi Sakai
2020 C conf
Design of Shape-Changeable Chiplet-Based Computers Using an Inductively Coupled Wireless Bus Interface.
ICCD
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2019 — conf
An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor.
FPT
Susumu Mashimo, Koji Inoue, Ryota Shioya, Akifumi Fujita, Reoma Matsuo, Seiya Akaki, Akifumi Fukuda, Toru Koizumi, Junichiro Kadomoto, Hidetsugu Irie, Masahiro Goshima
2019 C conf
WiXI: An Inter-Chip Wireless Bus Interface for Shape-Changeable Chiplet-Based Computers.
ICCD
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2018 — conf
An Area-Efficient Out-of-Order Soft-Core Processor Without Register Renaming.
FPT
Junichiro Kadomoto, Toru Koizumi, Akifumi Fukuda, Reoma Matsuo, Susumu Mashimo, Akifumi Fujita, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
2018 C conf
Estimating driver's readiness by understanding driving posture.
ICCE
Takahiro Yamada, Hidetsugu Irie, Masahiro Kunitake, Eiji Nagano, Shuichi Sakai
2018 — conf
Reduction of Instruction Increase Overhead by STRAIGHT Compiler.
CANDAR Workshops
Toru Koizumi, Satoshi Nakae, Akifumi Fukuda, Hidetsugu Irie, Shuichi Sakai
2018 A* conf
STRAIGHT: Hazardless Processor Architecture Without Register Renaming.
MICRO
Hidetsugu Irie, Toru Koizumi, Akifumi Fukuda, Seiya Akaki, Satoshi Nakae, Yutaro Bessho, Ryota Shioya, Takahiro Notsu, Katsuhiro Yoda, Teruo Ishihara, Shuichi Sakai
2017 C conf
Accelerating Integrity Verification on Secure Processors by Promissory Hash.
PRDC
Mizuki Miyanaga, Hidetsugu Irie, Shuichi Sakai
2016 C conf
"Stubborn" strategy to mitigate remaining cache misses.
ICCD
Hayato Nomura, Hiroyuki Katchi, Hidetsugu Irie, Shuichi Sakai
2016 — conf
High-Accuracy Joint Position Estimation and Posture Detection System for Driving.
MobiQuitous (Adjunct Proceedings)
Takahiro Yamada, Hidetsugu Irie, Shuichi Sakai
2015 J jnl
Design and Evaluation of a Configurable Query Processing Hardware for Data Streams.
IEICE Trans. Inf. Syst.
Yasin Oge, Masato Yoshimi, Takefumi Miyoshi, Hideyuki Kawashima, Hidetsugu Irie, Tsutomu Yoshinaga
2014 — conf
Accelerating OLAP Workload on Interconnected FPGAs with Flash Storage.
CANDAR
Masato Yoshimi, Ryu Kudo, Yasin Oge, Yuta Terada, Hidetsugu Irie, Tsutomu Yoshinaga
2014 — conf
An FPGA-Based Tightly Coupled Accelerator for Data-Intensive Applications.
MCSoC
Masato Yoshimi, Ryu Kudo, Yasin Oge, Yuta Terada, Hidetsugu Irie, Tsutomu Yoshinaga
2013 J jnl
A Fully Optical Ring Network-on-Chip with Static and Dynamic Wavelength Allocation.
IEICE Trans. Inf. Syst.
Cisse Ahmadou Dit Adi, Michihiro Koibuchi, Masato Yoshimi, Hidetsugu Irie, Tsutomu Yoshinaga
2013 — conf
A real-time gait improvement tool using a smartphone.
AH
Hirotaka Kashihara, Hiroki Shimizu, Hiroyoshi Houchi, Masato Yoshimi, Tsutomu Yoshinaga, Hidetsugu Irie
2013 — conf
An Efficient and Scalable Implementation of Sliding-Window Aggregate Operator on FPGA.
CANDAR
Yasin Oge, Masato Yoshimi, Takefumi Miyoshi, Hideyuki Kawashima, Hidetsugu Irie, Tsutomu Yoshinaga
2013 — conf
Sharing Computing Resources with Virtual Machines by Transparent Data Access.
CANDAR
Takuma Nakajima, Masato Yoshimi, Hidetsugu Irie, Tsutomu Yoshinaga
2012 — conf
FLAT: a GPU programming framework to provide embedded MPI.
GPGPU@ASPLOS
Takefumi Miyoshi, Hidetsugu Irie, Keigo Shima, Hiroki Honda, Masaaki Kondo, Tsutomu Yoshinaga
2012 Misc conf
Parallel Numerical Simulation of Visual Neurons for Analysis of Optical Illusion.
ICNC
Akira Egashira, Shunji Satoh, Hidetsugu Irie, Tsutomu Yoshinaga
2012 Misc conf
STRAIGHT: Realizing a Lightweight Large Instruction Window by Using Eventually Consistent Distributed Registers.
ICNC
Hidetsugu Irie, Daisuke Fujiwara, Kazuki Majima, Tsutomu Yoshinaga
2012 — conf
Throttling Control for Bufferless Routing in On-chip Networks.
MCSoC
Yicheng Guan, Cisse Ahmadou Dit Adi, Takefumi Miyoshi, Michihiro Koibuchi, Hidetsugu Irie, Tsutomu Yoshinaga
2012 J jnl
Using Cacheline Reuse Characteristics for Prefetcher Throttling.
IEICE Trans. Inf. Syst.
Hidetsugu Irie, Takefumi Miyoshi, Goki Honjo, Kei Hiraki, Tsutomu Yoshinaga
2011 J jnl
An Efficient Path Setup for a Hybrid Photonic Network-on-Chip.
Int. J. Netw. Comput.
Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga
2011 Misc conf
CCCPO: Robust Prefetcher Optimization Technique Based on Cache Convection.
ICNC
Hidetsugu Irie, Takefumi Miyoshi, Goki Honjo, Kei Hiraki, Tsutomu Yoshinaga
2011 J jnl
Computation-Communication Overlap of Linpack on a GPU-Accelerated PC Cluster.
IEICE Trans. Inf. Syst.
Junichi Ohmura, Takefumi Miyoshi, Hidetsugu Irie, Tsutomu Yoshinaga
2011 Misc conf
Multi-GPU Acceleration of Optical Flow Computation in Visual Functional Simulation.
ICNC
Junichi Ohmura, Akira Egashira, Shunji Satoh, Takefumi Miyoshi, Hidetsugu Irie, Tsutomu Yoshinaga
2010 Misc conf
An Efficient Path Setup for a Photonic Network-on-Chip.
ICNC
Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga
2010 Misc conf
CODIE: Continuation-Based Overlapping Data-Transfers with Instruction Execution.
ICNC
Takefumi Miyoshi, Kenji Kise, Hidetsugu Irie, Tsutomu Yoshinaga
2010 — conf
OREX - An Optical Ring with Electrical Crossbar Hybrid Photonic Network-on-Chip.
IWIA
Cisse Ahmadou Dit Adi, Ping Qiu, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga
2010 Misc conf
Parallel Matrix-Matrix Multiplication Based on HPL with a GPU-Accelerated PC Cluster.
ICNC
Qin Wang, Junichi Ohmura, Axida Shan, Takefumi Miyoshi, Hidetsugu Irie, Tsutomu Yoshinaga
2008 — conf
Low-Complexity Bypass Network Using Small RAM.
CDES
Shinobu Miwa, Hironori Ichibayashi, Hidetsugu Irie, Masahiro Goshima, Hironori Nakajo, Shinji Tomita
2008 J jnl
Ultra Dependable Processor.
IEICE Trans. Electron.
Shuichi Sakai, Masahiro Goshima, Hidetsugu Irie
2007 J jnl
Preventing timing errors on register writes: mechanisms of detections and recoveries.
SIGARCH Comput. Archit. News
Hidetsugu Irie, Ken Sugimoto, Masahiro Goshima, Shuichi Sakai
2007 A conf
Utilization of SECDED for soft error and variation-induced defect tolerance in caches.
DATE
Luong Dinh Hung, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai
2006 C conf
Base Address Recognition with Data Flow Tracking for Injection Attack Detection.
PRDC
Satoshi Katsunuma, Hiroyuki Kurita, Ryota Shioya, Kazuto Shimizu, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai