Hidetoshi Onodera

221 papers A* 4A 11B 4C 8Journal 83Unranked 111
YearRankTypeTitle / Venue / Authors
2023 J jnl
Approximation-Based System Implementation for Real-Time Minimum Energy Point Tracking over a Wide Operating Performance Region.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera
2022 — conf
Approximation-Based Implementation for a Minimum Energy Point Tracking Algorithm over a Wide Operating Performance Region.
LASCAS
Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera
2022 J jnl
NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, Hidetoshi Onodera
2022 — conf
Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits.
SOCC
Jun Shiomi, Shogo Terada, Tohru Ishihara, Hidetoshi Onodera
2021 J jnl
A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation.
IEICE Trans. Electron.
Kentaro Nagai, Jun Shiomi, Hidetoshi Onodera
2021 J jnl
A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
2021 C conf
CDF Distance Based Statistical Parameter Extraction Using Nonlinear Delay Variation Models.
IOLTS
Kensuke Murakami, Mahfuzul Islam, Hidetoshi Onodera
2021 J jnl
Evaluation Metrics for the Cost of Data Movement in Deep Neural Network Acceleration.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hongjie Xu, Jun Shiomi, Hidetoshi Onodera
2021 J jnl
MOSDA: On-Chip Memory Optimized Sparse Deep Neural Network Accelerator With Efficient Index Matching.
IEEE Open J. Circuits Syst.
Hongjie Xu, Jun Shiomi, Hidetoshi Onodera
2021 J jnl
Supplemental PDK for ASAP7 Using Synopsys Flow.
IPSJ Trans. Syst. LSI Des. Methodol.
Shinichi Nishizawa, Shih-Ting Lin, Yih-Lang Li, Hidetoshi Onodera
2021 J jnl
Supply and Threshold Voltage Scaling for Minimum Energy Operation over a Wide Operating Performance Region.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera
2021 A* conf
Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics.
DAC
Jun Shiomi, Shuya Kotsugi, Boyu Dong, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
2020 — conf
33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications.
ISSCC
Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi
2020 — conf
A DLL-based Body Bias Generator for Minimum Energy Operation with Independent P-well and N-well Bias.
APCCAS
Kentaro Nagai, Jun Shiomi, Hidetoshi Onodera
2020 — conf
A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing.
ISVLSI
Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
2020 — conf
An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics.
ICRC
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
2020 J jnl
Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm
IEICE Trans. Electron.
Akira Tsuchiya, Akitaka Hiratsuka, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera
2020 — conf
Dynamic Supply and Threshold Voltage Scaling towards Runtime Energy Optimization over a Wide Operating Performance Region.
SoCC
Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera
2020 A conf
MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing.
ICCAD
Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hidetoshi Onodera
2020 — conf
On-chip Memory Optimized CNN Accelerator with Efficient Partial-sum Accumulation.
ACM Great Lakes Symposium on VLSI
Hongjie Xu, Jun Shiomi, Hidetoshi Onodera
2019 — conf
A 45 Gb/s, 98 fJ/bit, 0.02 mm
SoCC
Akira Tsuchiya, Akitaka Hiratsuka, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera
2019 J jnl
A Design Method of a Cell-Based Amplifier for Body Bias Generation.
IEICE Trans. Electron.
Takuya Koyanagi, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2019 — conf
Analysis of Random Telegraph Noise (RTN) at Near-Threshold Operation by Measuring 154k Ring Oscillators.
IRPS
A. K. M. Mahfuzul Islam, Ryota Shimizu, Hidetoshi Onodera
2019 J jnl
Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing.
Integr.
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2019 — conf
BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing.
ASP-DAC
Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
2019 J jnl
Circuit Techniques for Device-Circuit Interaction toward Minimum Energy Operation.
IPSJ Trans. Syst. LSI Des. Methodol.
A. K. M. Mahfuzul Islam, Hidetoshi Onodera
2019 J jnl
Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity.
IEICE Trans. Electron.
Akira Tsuchiya, Akitaka Hiratsuka, Toshiyuki Inoue, Keiji Kishine, Hidetoshi Onodera
2019 J jnl
Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
2019 A* conf
NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map.
DAC
Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, Hidetoshi Onodera
2019 J jnl
On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2018 — conf
A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation.
A-SSCC
Akitaka Hiratsuka, Akira Tsuchiya, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera
2018 — conf
An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing.
ICRC
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
2018 J jnl
Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shinichi Nishizawa, Hidetoshi Onodera
2018 C conf
Independent N-Well And P-Well Biasing For Minimum Leakage Energy Operation.
IOLTS
Yosuke Okamura, Tohru Ishihara, Hidetoshi Onodera
2018 — conf
Low-Power and High-Linearity Inductorless Low-Noise Amplifiers with Active-Shunt-Feedback in 65-nm CMOS Technology.
MWSCAS
Toshiyuki Inoue, Ryosuke Noguchi, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera
2018 — conf
Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory Structure.
PATMOS
Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2018 J jnl
Minimum Energy Point Tracking with All-Digital On-Chip Sensors.
J. Low Power Electron.
Jun Shiomi, Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera
2018 — conf
Multi-Level Optimization for Large Fan-In Optical Logic Circuits Using Integrated Nanophotonics.
ICRC
Takumi Egawa, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi
2018 A conf
PVT
ICCAD
A. K. M. Mahfuzul Islam, Hidetoshi Onodera
2018 — conf
Performance Modeling of VIA-Switch FPGA for Device-Circuit-Architecture Co-Optimization.
SoCC
Tatsuhiro Higuchi, Tohru Ishihara, Hidetoshi Onodera
2018 — conf
Process variation aware D-Flip-Flop design using regression analysis.
ISQED
Shinichi Nishizawa, Hidetoshi Onodera
2018 J jnl
Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture.
IEEE Embed. Syst. Lett.
Hiroki Hihara, Akira Iwasaki, Masanori Hashimoto, Hiroyuki Ochi, Yukio Mitsuyama, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, Tadahiko Sugibayashi, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada, Makoto Miyamura, Toshitsugu Sakamoto
2018 J jnl
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars.
IEEE Trans. Very Large Scale Integr. Syst.
Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Jaehoon Yu, Masanori Hashimoto
2018 — conf
Worst-Case Performance Analysis Under Random Telegraph Noise Induced Threshold Voltage Variability.
PATMOS
A. K. M. Mahfuzul Islam, Hidetoshi Onodera
2017 J jnl
A Minimum Energy Point Tracking Algorithm Based on Dynamic Voltage Scaling and Adaptive Body Biasing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera
2017 J jnl
A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2017 — conf
Effect of supply voltage on random telegraph noise of transistors under switching condition.
PATMOS
Islam A. K. M. Mahfuzul, Hidetoshi Onodera
2017 — conf
On-chip temperature and process variation sensing using a reconfigurable Ring Oscillator.
VLSI-DAT
Tadashi Kishimoto, Tohru Ishihara, Hidetoshi Onodera
2017 — conf
Pin accessibility evaluating model for improving routability of VLSI designs.
SoCC
Hong-Yan Su, Shinichi Nishizawa, Yan-Shiun Wu, Jun Shiomi, Yih-Lang Li, Hidetoshi Onodera
2017 — conf
Power-bandwidth trade-off analysis of multi-stage inverter-type transimpedance amplifier for optical communication.
MWSCAS
Akitaka Hiratsuka, Akira Tsuchiya, Hidetoshi Onodera
2016 J jnl
2016 ASP-DAC.
IEEE Des. Test
Hidetoshi Onodera
2016 — conf
A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region.
ASP-DAC
Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2016 B conf
A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch.
FPL
Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto
2016 J jnl
Analytical Stability Modeling for CMOS Latches in Low Voltage Operation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2016 — conf
Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing.
PATMOS
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2016 — conf
Minimum energy point tracking using combined dynamic voltage scaling and adaptive body biasing.
SoCC
Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera
2016 — conf
On-chip monitoring and compensation scheme with fine-grain body biasing for robust and energy-efficient operations.
ASP-DAC
Islam A. K. M. Mahfuzul, Hidetoshi Onodera
2016 — conf
Variability- and correlation-aware logical effort for near-threshold circuit design.
ISQED
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2015 — conf
A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking.
A-SSCC
Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka, Akira Tsuchiya, Hidetoshi Onodera, Shunji Kimura
2015 J jnl
A Forward/Reverse Body Bias Generator with Wide Supply-Range down to Threshold Voltage.
IEICE Trans. Electron.
Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera
2015 J jnl
A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Keiji Kishine, Hiromi Inaba, Hiroshi Inoue, Makoto Nakamura, Akira Tsuchiya, Hiroaki Katsurai, Hidetoshi Onodera
2015 — conf
An energy-efficient on-chip memory structure for variability-aware near-threshold operation.
ISQED
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2015 — conf
An impact of process variation on supply voltage dependence of logic path delay variation.
VLSI-DAT
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
2015 — conf
Energy reduction by built-in body biasing with single supply voltage operation.
ISQED
Norihiro Kamae, Islam A. K. M. Mahfuzul, Akira Tsuchiya, Tohru Ishihara, Hidetoshi Onodera
2015 J jnl
Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets.
IEICE Trans. Electron.
Jun Furuta, Kazutoshi Kobayashi, Hidetoshi Onodera
2015 J jnl
Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell.
IPSJ Trans. Syst. LSI Des. Methodol.
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
2015 — conf
Microarchitectural-level statistical timing models for near-threshold circuit design.
ASP-DAC
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2015 — conf
Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis.
ASP-DAC
Masanori Hashimoto, Dawood Alnajiar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera
2015 — conf
Session 23 - Modeling emerging devices.
CICC
Chenjie Gu, Hidetoshi Onodera
2015 J jnl
Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2015 J jnl
Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring.
IEEE J. Solid State Circuits
Islam A. K. M. Mahfuzul, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2014 C conf
A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops.
ISCAS
Keiji Kishine, Hiroshi Inoue, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya, Hidetoshi Onodera, Hiroaki Katsurai
2014 J jnl
A Body Bias Generator with Low Supply Voltage for Within-Die Variability Compensation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera
2014 — conf
A body bias generator with wide supply-range down to threshold voltage for within-die variability compensation.
A-SSCC
Norihiro Kamae, Islam A. K. M. Mahfuzul, Akira Tsuchiya, Hidetoshi Onodera
2014 J jnl
Analysis of Radiation-Induced Clock-Perturbation in Phase-Locked Loop.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Sinnyoung Kim, Akira Tsuchiya, Hidetoshi Onodera
2014 — conf
Characterization and compensation of performance variability using on-chip monitors.
VLSI-DAT
Islam A. K. M. Mahfuzul, Hidetoshi Onodera
2014 — conf
Computer simulation of radiation-induced clock-perturbation in phase-locked loop with analog behavioral model.
ISQED
Tomohiro Fujita, Sinnyoung Kim, Hidetoshi Onodera
2014 — conf
Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation.
SoCC
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
2014 J jnl
Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs.
IEEE Trans. Very Large Scale Integr. Syst.
Bishnu Prasad Das, Hidetoshi Onodera
2014 — conf
Impact of random telegraph noise on CMOS logic circuit reliability.
CICC
Takashi Matsumoto, Kazutoshi Kobayashi, Hidetoshi Onodera
2014 — conf
Modeling of advanced devices.
CICC
Colin McAndrew, Hidetoshi Onodera
2014 J jnl
On-Chip Measurement of Rise/Fall Gate Delay Using Reconfigurable Ring Oscillator.
IEEE Trans. Circuits Syst. II Express Briefs
Bishnu Prasad Das, Hidetoshi Onodera
2014 J jnl
Radiation-Hardened PLL with a Switchable Dual Modular Redundancy Structure.
IEICE Trans. Electron.
Sinnyoung Kim, Akira Tsuchiya, Hidetoshi Onodera
2014 J jnl
Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, Hidetoshi Onodera
2014 — conf
Variability and Soft-Error Resilience in Dependable VLSI Platform.
ATS
Yukio Mitsuyama, Hidetoshi Onodera
2014 — conf
Variation-aware Flip-Flop energy optimization for ultra low voltage operation.
SoCC
Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
2014 — conf
Wide-supply-range all-digital leakage variation sensor for on-chip process and temperature monitoring.
A-SSCC
Islam A. K. M. Mahfuzul, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2013 — conf
A 25-Gb/s LD driver with area-effective inductor in a 0.18-µm CMOS.
ASP-DAC
Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera
2013 J jnl
A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset by Utilizing the Parasitic Bipolar Effect.
IEICE Trans. Electron.
Kuiyuan Zhang, Jun Furuta, Ryosuke Yamamoto, Kazutoshi Kobayashi, Hidetoshi Onodera
2013 — conf
AMS verification in advanced technologies.
CICC
Hidetoshi Onodera, Yu Kevin Cao
2013 — conf
Analysis and comparison of XOR cell structures for low voltage circuit design.
ISQED
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
2013 — conf
Dependable VLSI Platform using Robust Fabrics.
ASP-DAC
Hidetoshi Onodera
2013 J jnl
On-Chip Detection of Process Shift and Process Spread for Post-Silicon Diagnosis and Model-Hardware Correlation.
IEICE Trans. Inf. Syst.
Islam A. K. M. Mahfuzul, Hidetoshi Onodera
2013 C conf
Perturbation-immune radiation-hardened PLL with a switchable DMR structure.
IOLTS
Sinnyoung Kim, Akira Tsuchiya, Hidetoshi Onodera
2013 J jnl
Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
2012 — conf
A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18µm CMOS.
ASP-DAC
Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera
2012 — conf
A Standard Cell Optimization Method for Near-Threshold Voltage Operations.
PATMOS
Masahiro Kondo, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
2012 C conf
A flexible structure of standard cell and its optimization method for near-threshold voltage operation.
ICCD
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
2012 J jnl
Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera
2012 J jnl
Area-efficient reconfigurable-array-based oscillator for standard cell characterisation.
IET Circuits Devices Syst.
Bishnu Prasad Das, Hidetoshi Onodera
2012 — conf
Modeling & design for variability and reliability.
CICC
Trent McConaghy, Hidetoshi Onodera
2012 — conf
On-Chip Detection of Process Shift and Process Spread for Silicon Debugging and Model-Hardware Correlation.
Asian Test Symposium
Islam A. K. M. Mahfuzul, Hidetoshi Onodera
2011 — conf
A 10.3Gbps translmpedance amplifier with mutually coupled inductors in 0.18-μm CMOS.
ISOCC
Shigekazu Miyawaki, Makoto Nakamura, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera
2011 — conf
A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles.
ASP-DAC
Jun Furuta, Chikara Hamanaka, Kazutoshi Kobayashi, Hidetoshi Onodera
2011 — conf
An area effective forward/reverse body bias generator for within-die variability compensation.
A-SSCC
Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera
2011 — conf
Bandwidth enhancement for high speed amplifier utilizing mutually coupled on-chip inductors.
ISOCC
Akira Tsuchiya, Takeshi Kuboki, Yusuke Ohtomo, Keiji Kishine, Shigekazu Miyawaki, Makoto Nakamura, Hidetoshi Onodera
2011 — conf
Correlations between well potential and SEUs measured by well-potential perturbation detectors in 65nm.
A-SSCC
Jun Furuta, Ryosuke Yamamoto, Kazutoshi Kobayashi, Hidetoshi Onodera
2011 — conf
Dependable VLSI Program in Japan: Program Overview and the Current Status of Dependable VLSI Platform Project.
Asian Test Symposium
Hidetoshi Onodera
2011 J jnl
Message from the Editor-in-Chief.
IPSJ Trans. Syst. LSI Des. Methodol.
Hidetoshi Onodera
2011 — conf
Modeling of Random Telegraph Noise under circuit operation - Simulation and measurement of RTN-induced delay fluctuation.
ISQED
Kyosuke Ito, Takashi Matsumoto, Shinichi Nishizawa, Hiroki Sunagawa, Kazutoshi Kobayashi, Hidetoshi Onodera
2011 J jnl
Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chikara Hamanaka, Ryosuke Yamamoto, Jun Furuta, Kanto Kubota, Kazutoshi Kobayashi, Hidetoshi Onodera
2010 — conf
A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-µm CMOS.
CICC
Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera
2010 — conf
A design procedure of predictive RF MOSFET model for compatibility with ITRS.
SoCC
Sinnyoung Kim, Akira Tsuchiya, Hidetoshi Onodera
2010 J jnl
An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity.
IEICE Trans. Electron.
Jun Furuta, Kazutoshi Kobayashi, Hidetoshi Onodera
2010 J jnl
Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells.
Inf. Media Technol.
Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
2010 J jnl
Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells.
IPSJ Trans. Syst. LSI Des. Methodol.
Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
2010 J jnl
Message from the Editor-in-Chief.
IPSJ Trans. Syst. LSI Des. Methodol.
Hidetoshi Onodera
2010 — conf
Variation-tolerant design of D-flipflops.
SoCC
Hiroki Sunagawa, Hidetoshi Onodera
2010 — conf
Warning Prediction Sequential for Transient Error Prevention.
DFT
Bishnu Prasad Das, Hidetoshi Onodera
2009 — conf
Dependable VLSI: device, design and architecture: how should they cooperate?
ASP-DAC
Shuichi Sakai, Hidetoshi Onodera, Hiroto Yasuura, James C. Hoe
2009 — conf
Erect of regularity-enhanced layout on printability and circuit performance of standard cells.
ISQED
Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
2009 J jnl
Message from the Editor-in-Chief.
IPSJ Trans. Syst. LSI Des. Methodol.
Hidetoshi Onodera
2009 — conf
Modeling of passive elements and reliability.
CICC
Gennady Gildenblat, Hidetoshi Onodera
2009 J jnl
Statistical Gate Delay Model for Multiple Input Switching.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera
2008 B conf
A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS.
FPL
Kazutoshi Kobayashi, Yohei Kume, Cam Lai Ngo, Yuuri Sugihara, Hidetoshi Onodera
2008 J jnl
Accurate Estimation of the Worst-case Delay in Statistical Static Timing Analysis.
Inf. Media Technol.
Haruhiko Terada, Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera
2008 J jnl
Accurate Estimation of the Worst-case Delay in Statistical Static Timing Analysis.
IPSJ Trans. Syst. LSI Des. Methodol.
Haruhiko Terada, Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera
2008 J jnl
Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration.
IEICE Trans. Electron.
Hirofumi Shinohara, Koji Nii, Hidetoshi Onodera
2008 — conf
Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs.
ASP-DAC
Kazutoshi Kobayashi, Hidetoshi Onodera
2008 B conf
Performance optimization by track swapping on critical paths utilizing random variations for FPGAS.
FPL
Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera
2008 — conf
Session 2 - Statistical modeling.
CICC
Hidetoshi Onodera, Hong-Ha Vuong
2008 A conf
Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs.
FPGA
Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera
2008 — conf
Statistical gate delay model for Multiple Input Switching.
ASP-DAC
Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera
2008 J jnl
Timing Analysis Considering Temporal Supply Voltage Fluctuation.
IEICE Trans. Inf. Syst.
Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera
2008 J jnl
Welcome to TSLDM - A New Open-Access Online Journal from IPSJ.
IPSJ Trans. Syst. LSI Des. Methodol.
Hidetoshi Onodera
2007 — conf
A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology.
ASP-DAC
Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera
2007 J jnl
A 90 nm 48 x 48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations.
IEICE Trans. Electron.
Kazutoshi Kobayashi, Kazuya Katsuki, Manabu Kotani, Yuuri Sugihara, Yohei Kume, Hidetoshi Onodera
2007 J jnl
A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations.
IEICE Trans. Electron.
Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera
2007 — conf
A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations.
ASP-DAC
Yuuri Sugihara, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera
2007 J jnl
Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver.
IEICE Trans. Electron.
Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera
2007 J jnl
Manufacturability-Aware Design of Standard Cells.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hirokazu Muta, Hidetoshi Onodera
2007 J jnl
Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling.
IEICE Trans. Electron.
Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
2007 J jnl
Timing Analysis Considering Spatial Power/Ground Level Variation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera
2007 — conf
Worst-case delay analysis considering the variability of transistors and interconnects.
ISPD
Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera
2006 — conf
A Detailed Vth-Variation Analysis for Sub-100-nm Embedded SRAM Design.
SoCC
Masanao Yamaoka, Hidetoshi Onodera
2006 J jnl
A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era.
IEICE Trans. Electron.
Kazutoshi Kobayashi, Akihiko Higuchi, Hidetoshi Onodera
2006 B conf
A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime.
FPL
Kazutoshi Kobayashi, Manabu Kotani, Kazuya Katsuki, Y. Takatsukasa, K. Ogata, Yuuri Sugihara, Hidetoshi Onodera
2006 J jnl
Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect.
IEICE Trans. Electron.
Yoichi Yuyama, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
2006 — conf
Consideration of Transition-Time Variability in Statistical Timing Analysis.
SoCC
Takeshi Kouno, Hidetoshi Onodera
2006 J jnl
Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
2006 — conf
Interconnect RL extraction at a single representative frequency.
ASP-DAC
Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
2006 — conf
Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices.
ASP-DAC
Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera
2006 J jnl
Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto
2006 J jnl
Special Section on VLSI Design and CAD Algorithms.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hidetoshi Onodera
2006 J jnl
Variability: Modeling and Its Impact on Design.
IEICE Trans. Electron.
Hidetoshi Onodera
2005 J jnl
A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and an LC Oscillator Based PLL.
IEICE Trans. Electron.
Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera
2005 J jnl
A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era.
IEICE Trans. Electron.
Kazutoshi Kobayashi, Masao Aramoto, Hidetoshi Onodera
2005 — conf
A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing.
ASP-DAC
Kazutoshi Kobayashi, Masao Aramoto, Yoichi Yuyama, Akihiko Higuchi, Hidetoshi Onodera
2005 — conf
A yield and speed enhancement scheme under within-die variations on 90nm LUT array.
CICC
Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera
2005 — conf
Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18µm CMOS process.
ASP-DAC
Akinori Shinmyo, Masanori Hashimoto, Hidetoshi Onodera
2005 — conf
Design guideline for resistive termination of on-chip high-speed interconnects.
CICC
Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
2005 J jnl
Effects of On-Chip Inductance on Power Distribution Grid.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera
2005 — conf
Effects of on-chip inductance on power distribution grid.
ISPD
Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera
2005 J jnl
Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
2005 — conf
Return path selection for loop RL extraction.
ASP-DAC
Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
2005 — conf
Statistical Analysis of Clock Skew Variation in H-Tree Structure.
ISQED
Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera
2005 J jnl
Statistical Analysis of Clock Skew Variation in H-Tree Structure.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera
2005 — conf
Substrate and phase noise characterization.
CICC
Steffen Rochel, Hidetoshi Onodera
2005 J jnl
Successive Pad Assignment for Minimizing Supply Voltage Drop.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera
2005 — conf
Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion.
ASP-DAC
Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera
2005 — conf
Timing analysis considering temporal supply voltage fluctuation.
ASP-DAC
Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera
2004 J jnl
A Comprehensive Simulation and Test Environment for Prototype VLSI Verification.
IEICE Trans. Inf. Syst.
Kazutoshi Kobayashi, Hidetoshi Onodera
2004 — conf
A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process.
ASP-DAC
Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera
2004 — conf
An SoC architecture and its design methodology using unifunctional heterogeneous processor array.
ASP-DAC
Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera
2004 — conf
Automatic Generation of Standard Cell Library in VDSM Technologies.
ISQED
Masanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera
2004 J jnl
Equivalent waveform propagation for static timing analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera
2004 — conf
Modelling and optimization of on-chip spiral inductor in S-parameter domain.
ISCAS (5)
Ken-ichi Okada, Hiroaki Hoshino, Hidetoshi Onodera
2004 — conf
Performance limitation of on-chip global interconnects for high-speed signaling.
CICC
Akira Tsuchiya, Yuuya Gotoh, Masanori Hashimoto, Hidetoshi Onodera
2004 — conf
RTL/ISS co-modeling methodology for embedded processor using SystemC.
ISCAS (5)
Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera
2004 — conf
Representative frequency for interconnect R(f)L(f)C extraction.
ASP-DAC
Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
2004 A conf
Timing analysis considering spatial power/ground level variation.
ICCAD
Masanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera
2003 A conf
A Statistical Gate-Delay Model Considering Intra-Gate Variability.
ICCAD
Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera
2003 — conf
A statistical gate delay model for intra-chip and inter-chip variabilities.
ASP-DAC
Kenichi Okada, Kento Yamaoka, Hidetoshi Onodera
2003 — conf
Capturing crosstalk-induced waveform for accurate static timing analysis.
ISPD
Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera
2003 J jnl
Crosstalk Noise Estimation for Generic RC Trees.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera
2003 A conf
Equivalent Waveform Propagation for Static Timing Analysis.
ICCAD
Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera
2003 J jnl
Experimental Study on Cell-Base High-Performance Datapath Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masanori Hashimoto, Yoshiteru Hayashi, Hidetoshi Onodera
2003 J jnl
Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kenichi Okada, Hidetoshi Onodera
2003 J jnl
Representative Frequency for Interconnect R(f)L(f)C Extraction.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
2003 — conf
Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 μm technologies.
ASP-DAC
Masanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera
2003 J jnl
Statistical Gate-Delay Modeling with Intra-Gate Variability.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kenichi Okada, Kento Yamaoka, Hidetoshi Onodera
2003 — conf
Statistical modeling of gate-delay variation with consideration of intra-gate variability.
ISCAS (5)
Kenichi Okada, Kento Yamaoka, Hidetoshi Onodera
2002 — conf
Crosstalk noise optimization by post-layout transistor sizing.
ISPD
Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera
2002 — conf
Experimental Study on Cell-Base High-Performance Datapath Design.
IWLS
Masanori Hashimoto, Yashiteru Hayashi, Hidetoshi Onodera
2002 J jnl
Increase in Delay Uncertainty by Performance Optimization.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masanori Hashimoto, Hidetoshi Onodera
2002 — conf
Measurement results of on-chip IR-drop.
CICC
Kazutoshi Kobayashi, Junji Yamaguchi, Hidetoshi Onodera
2001 — conf
A dynamically phase adjusting PLL with a variable delay.
ASP-DAC
Takeo Yasuda, Hiroaki Fujita, Hidetoshi Onodera
2001 — conf
A vector-pipeline DSP for low-rate videophones.
ASP-DAC
Kazutoshi Kobayashi, Makoto Eguchi, Takuya Iwahashi, Takehide Shibayama, Xiang Li, Kousuke Takai, Hidetoshi Onodera
2001 — conf
Beyond the red brick wall (panel): challenges and solutions in 50nm physical design.
ASP-DAC
Hidetoshi Onodera, Andrew B. Kahng, Wayne Wei-Ming Dai, Sani R. Nassif, Juho Kim, Akira Tanabe, Toshihiro Hattori
2001 C conf
Crosstalk Noise Estimation for Generic RC Trees.
ICCD
Masao Takahashi, Masanori Hashimoto, Hidetoshi Onodera
2001 — conf
Post-layout transistor sizing for power reduction in cell-based design.
ASP-DAC
Masanori Hashimoto, Hidetoshi Onodera
2001 — conf
ST: PERL package for simulation and test environment.
ISCAS (5)
Kazutoshi Kobayashi, Hidetoshi Onodera
2000 — conf
A method for linking process-level variability to system performances.
ASP-DAC
Tomohiro Fujita, Ken-ichi Okada, Hiroaki Fujita, Hidetoshi Onodera, Keikichi Tamaru
2000 — conf
A performance optimization method by gate sizing using statistical static timing analysis.
ISPD
Masanori Hashimoto, Hidetoshi Onodera
2000 C conf
Statistical delay calculation with vector synthesis model.
ISCAS
Tomohiro Fujita, Hidetoshi Onodera
2000 C conf
Statistical modeling of device characteristics with systematic fluctuation.
ISCAS
Kenichi Okada, Hidetoshi Onodera
1999 A* conf
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design.
DAC
Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru
1998 A conf
A power optimization method considering glitch reduction by gate sizing.
ISLPED
Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru
1998 J jnl
Model-adaptable MOSFET parameter-extraction method using an intermediate model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru
1998 A conf
Proposal of a timing model for CMOS logic gates driving a CRC load.
ICCAD
Akio Hirata, Hidetoshi Onodera, Keikichi Tamaru
1997 — conf
A current mode cyclic A/D converter with a 0.8 μm CMOS process.
ASP-DAC
Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru
1997 — conf
A functional memory type parallel processor for vector quantization.
ASP-DAC
Kazutoshi Kobayashi, Masayoshi Kinoshita, Masahiro Takeuchi, Hidetoshi Onodera, Keikichi Tamaru
1996 — conf
Timing and Power Optimization by Gate Sizing Considering False Paths.
Great Lakes Symposium on VLSI
Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru
1995 — conf
A model-adaptable MOSFET parameter extraction system.
ASP-DAC
Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru
1995 A conf
An iterative gate sizing approach with accurate delay evaluation.
ICCAD
Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru
1993 A conf
Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's.
ICCAD
Vasily G. Moshnyaga, Hiroshi Mori, Hidetoshi Onodera, Keikichi Tamaru
1991 A* conf
Branch-and-Bound Placement for Building Block Layout.
DAC
Hidetoshi Onodera, Yo Taniguchi, Keikichi Tamaru
1990 J jnl
Operational-amplifier compilation with performance optimization.
IEEE J. Solid State Circuits
Hidetoshi Onodera, Hiroyuki Kanbara, Keikichi Tamaru
1989 A conf
An efficient algorithm for layout compaction problem with symmetry constraints.
ICCAD
R. Okuda, Takashi Sato, Hidetoshi Onodera, K. Tamariu
1988 J jnl
A cyclic A/D converter that does not require ratio-matched components.
IEEE J. Solid State Circuits
Hidetoshi Onodera, Tetsuo Tateishi, Keikichi Tamaru
1987 J jnl
System design of a special-purpose computer for LSI design rule checking.
Syst. Comput. Jpn.
Keikichi Tamaru, Hidetoshi Onodera