Hideto Hidaka

40 papers A 4Journal 25Unranked 8
YearRankTypeTitle / Venue / Authors
2020 J jnl
Essential Roles, Challenges and Development of Embedded MCU Micro-Systems to Innovate Edge Computing for the IoT/AI Age.
IEICE Trans. Electron.
Takashi Kono, Yasuhiko Taito, Hideto Hidaka
2019 J jnl
A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications.
IEICE Trans. Electron.
Masanori Hayashikoshi, Hiroaki Tanizaki, Yasumitsu Murai, Takaharu Tsuji, Kiyoshi Kawabata, Koji Nii, Hideyuki Noda, Hiroyuki Kondo, Yoshio Matsuda, Hideto Hidaka
2019 J jnl
Foreword.
IEICE Trans. Electron.
Hideto Hidaka
2018 — ch.
Applications and Technology Trend in Embedded Flash Memory.
Embedded Flash Memory for Embedded Systems
Hideto Hidaka
2018 — book
Embedded Flash Memory for Embedded Systems: Technology, Design for Sub-systems, and Innovations.
Hideto Hidaka
2018 J jnl
Foreword.
IEICE Trans. Electron.
Hideto Hidaka
2018 — ch.
Introduction.
Embedded Flash Memory for Embedded Systems
Hideto Hidaka
2016 — conf
7.6 A 90nm embedded 1T-MONOS flash macro for automotive applications with 0.07mJ/8kB rewrite energy and endurance over 100M cycles under Tj of 175°C.
ISSCC
Hidenori Mitani, Ken Matsubara, Hiroshi Yoshida, Takashi Hashimoto, Hideaki Yamakoshi, Shinichiro Abe, Takashi Kono, Yasuhiko Taito, Takashi Ito, Takashi Krafuji, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi
2016 J jnl
A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170°C.
IEEE J. Solid State Circuits
Yasuhiko Taito, Takashi Kono, Masaya Nakano, Tomoya Saito, Takashi Ito, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi
2015 — conf
7.3 A 28nm embedded SG-MONOS flash macro for automotive achieving 200MHz read operation and 2.0MB/S write throughput at Ti, of 170°C.
ISSCC
Yasuhiko Taito, Masaya Nakano, Hiromi Okimoto, Daisuke Okada, Takashi Ito, Takashi Kono, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi
2015 — conf
How future mobility meets IT: Cyber-physical system designs revisit semiconductor technology.
A-SSCC
Hideto Hidaka
2014 J jnl
40-nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macros for Automotive With 160-MHz Random Access for Code and Endurance Over 10 M Cycles for Data at the Junction Temperature of 170°C.
IEEE J. Solid State Circuits
Takashi Kono, Takashi Ito, Tamaki Tsuruda, Takayuki Nishiyama, Tsutomu Nagasawa, Tomoya Ogawa, Yoshiyuki Kawashima, Hideto Hidaka, Tadaaki Yamauchi
2013 — conf
40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data.
ISSCC
Takashi Kono, Takashi Ito, Tamaki Tsuruda, Takayuki Nishiyama, Tsutomu Nagasawa, Tomoya Ogawa, Yoshiyuki Kawashima, Hideto Hidaka, Tadaaki Yamauchi
2012 — conf
Session 1 overview: Plenary session.
ISSCC
Anantha P. Chandrakasan, Hideto Hidaka
2010 — conf
Silicon 3D-integration technology and systems.
ISSCC
Pascal Urard, Ken Takeuchi, Kerry Bernstein, Hideto Hidaka, Michael Phan, Joo-Sun Choi, Bob Payne, Vladimir Stojanovic, Kees van Berkel, Takayasu Sakurai
2009 J jnl
Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits
Donhee Ham, Hideto Hidaka, Ron Ho, Ram K. Krishnamurthy
2007 — conf
Non-Volatile Memories.
ISSCC
Hideto Hidaka, Yair Sofer
2002 J jnl
0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability.
IEEE J. Solid State Circuits
Hirohito Kikukawa, Shigeki Tomishima, Takaharu Tsuji, Toshiaki Kawasaki, Shouji Sakamoto, Masatoshi Ishikawa, Wataru Abe, Hiroaki Tanizaki, Hiroshi Kato, Toshitaka Uchikoba, Toshihiro Inokuchi, Manabu Senoh, Yoshifumi Fukushima, Mitsutaka Niiro, Masanao Maruta, Akinori Shibayama, Tsukasa Ooishi, Kazunari Takahashi, Hideto Hidaka
2002 A conf
A Variable Drivability (VD) Output Buffer for the System In a Package (SIP) and High Frequency Wafer Test.
ITC
Shigeki Tomishima, Hiroaki Tanizaki, Mitsutaka Niiro, Masanao Maruta, Hideto Hidaka, T. Tada, Kenji Gamo
2001 J jnl
A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications.
IEEE J. Solid State Circuits
Shigeki Tomishima, Takaharu Tsuji, Toshiaki Kawasaki, Masatoshi Ishikawa, Toshihiro Inokuchi, Hiroshi Kato, Hiroaki Tanizaki, Wataru Abe, Akinori Shibayama, Yoshifumi Fukushima, Mitsutaka Niiro, Masanao Maruta, Toshitaka Uchikoba, Manabu Senoh, Shouji Sakamoto, Tsukasa Ooishi, Hirohito Kikukawa, Hideto Hidaka, Kazunari Takahashi
2001 — conf
A shared built-in self-repair analysis for multiple embedded memories.
CICC
Jun Ohtani, Tukasa Ooishi, Tomoya Kawagoe, Mitsutaka Niiro, Masanao Maruta, Hideto Hidaka
2000 A conf
A built-in self-repair analyzer (CRESTA) for embedded DRAMs.
ITC
Tomoya Kawagoe, Jun Ohtani, Mitsutaka Niiro, Tukasa Ooishi, Mitsuhiro Hamada, Hideto Hidaka
1999 J jnl
A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme.
IEEE J. Solid State Circuits
Hitoshi Tanaka, Masakazu Aoki, Takeshi Sakata, Shin'ichiro Kimura, Narumi Sakashita, Hideto Hidaka, Tadashi Tachibana, Katsutaka Kimura
1996 J jnl
A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories.
IEEE J. Solid State Circuits
Tsukasa Ooishi, Yuichiro Komiya, Kei Hamade, Mikio Asakura, Kenichi Yasuda, Kiyohiro Furutani, Tetsuo Kato, Hideto Hidaka, Hideyuki Ozaki
1995 J jnl
An automatic temperature compensation of internal sense ground for subquarter micron DRAM's.
IEEE J. Solid State Circuits
Tsukasa Ooishi, Yuichiro Komiya, Kei Hamade, Mho Asakura, Kenichi Yasuda, Kiyohiro Furutani, Hideto Hidaka, Hiroshi Miyamoto, Hideyuki Ozaki
1994 J jnl
A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs.
IEEE J. Solid State Circuits
Tsukasa Ooishi, Mikio Asakura, Shigeki Tomishima, Hideto Hidaka, Kazutami Arimoto, Kazuyasu Fujishima
1994 J jnl
An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology.
IEEE J. Solid State Circuits
Katsuhiro Suma, Takahiro Tsuruda, Hideto Hidaka, Takahisa Eimori, Toshiyuki Oashi, Yasuo Yamaguchi, Toshiaki Iwamatsu, Masakazu Hirose, Fukashi Morishita, Kazutarni Arimoto, Kazuyasu Fujishima, Yasuo Inoue, Tadashi Nishimura, Tsutomu Yoshihara
1994 J jnl
An experimental 256-Mb DRAM with boosted sense-ground scheme.
IEEE J. Solid State Circuits
Mikio Asakura, Tsukasa Ooishi, Masaki Tsukude, Shigeki Tomishima, Takahisa Eimori, Hideto Hidaka, Yoshikazu Ohno, Kazutani Arimoto, Kazuyasu Fujishima, Tadashi Nishimura, Tsutomu Yoshihara
1993 J jnl
Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters.
IEEE Des. Test Comput.
Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsuhiro Suma, Kazuyasu Fujishima
1992 J jnl
A 34-ns 16-Mb DRAM with controllable voltage down-converter.
IEEE J. Solid State Circuits
Hideto Hidaka, Kazutami Arimoto, Kazutoshi Hirayama, Masanori Hayashikoshi, Mikio Asakura, Masaki Tsukude, Tsukasa Oishi, Shinji Kawai, Katsuhiro Suma, Yasuhiro Konishi, Koji Tanaka, Wataru Wakamiya, Yoshikazu Ohno, Kazuyasu Fujishima
1992 A conf
A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter.
ITC
Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsunori Suma, Kazuyasu Fujishima
1992 J jnl
A dual-mode sensing scheme of capacitor-coupled EEPROM cell.
IEEE J. Solid State Circuits
Masanori Hayashikoshi, Hideto Hidaka, Kazutami Arimoto, Kazuyasu Fujishima
1992 J jnl
A high-density dual-port memory cell operation and array architecture for ULSI DRAMs.
IEEE J. Solid State Circuits
Hideto Hidaka, Kazutami Arimoto, Kazuyasu Fujishima
1992 J jnl
Cell-plate line connecting complementary bit-line (C
IEEE J. Solid State Circuits
Mikio Asakura, Kazutami Arimoto, Hideto Hidaka, Kazuyasu Fujishima
1991 J jnl
A circuit design of intelligent cache DRAM with automatic write-back capability.
IEEE J. Solid State Circuits
Kazutami Arimoto, Mikio Asakura, Hideto Hidaka, Yoshio Matsuda, Kazuyasu Fujishima
1991 J jnl
A divided/shared bit-line sensing scheme for ULSI DRAM cores.
IEEE J. Solid State Circuits
Hideto Hidaka, Yoshio Matsuda, Kazuyasu Fujishima
1990 J jnl
The cache DRAM architecture: a DRAM with an on-chip cache memory.
IEEE Micro
Hideto Hidaka, Yoshio Matsuda, Mikio Asakura, Kazuyasu Fujishima
1989 J jnl
A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode.
IEEE J. Solid State Circuits
Yasumasa Nishimura, Mitsuhiro Hamada, Hideto Hidaka, Hideyuki Ozaki, Kazuyasu Fujishima
1989 J jnl
Twisted bit-line architectures for multi-megabit DRAMs.
IEEE J. Solid State Circuits
Hideto Hidaka, Kazuyasu Fujishima, Yoshio Matsuda, Mikio Asakura, Tsutomu Yoshihara
1986 A conf
Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode.
ITC
Yasumasa Nishimura, Mitsuhiro Hamada, Hideto Hidaka, Hideyuki Ozaki, Kazuyasu Fujishima, Y. Hayasaka