Hideo Ito

77 papers A 1B 1C 12Misc 1Journal 35Unranked 27
YearRankTypeTitle / Venue / Authors
2016 J jnl
High-Efficiency Milling of Steam Turbine Blade.
Int. J. Autom. Technol.
Xin Yuan, Takanori Yazawa, Hideo Ito, Tatsuki Otsubo, Yukio Maeda, Reiko Yamada
2014 J jnl
Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion.
IEICE Trans. Inf. Syst.
Wenpo Zhang, Kazuteru Namba, Hideo Ito
2014 J jnl
Scan Shift Time Reduction Using Test Compaction for On-Chip Delay Measurement.
IEICE Trans. Inf. Syst.
Wenpo Zhang, Kazuteru Namba, Hideo Ito
2013 J jnl
Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA.
IEICE Trans. Inf. Syst.
Kazuteru Namba, Nobuhide Takashina, Hideo Ito
2013 J jnl
Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF.
IEICE Trans. Inf. Syst.
Wenpo Zhang, Kazuteru Namba, Hideo Ito
2013 J jnl
Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop.
J. Electron. Test.
Kazuteru Namba, Takashi Katagiri, Hideo Ito
2012 J jnl
An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection.
IEEE Trans. Very Large Scale Integr. Syst.
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
2012 — conf
Dual-edge-triggered FF with timing error detection capability.
DFT
Kazuteru Namba, Takashi Katagiri, Hideo Ito
2012 — conf
Improving small-delay fault coverage for on-chip delay measurement.
DFT
Wenpo Zhang, Kazuteru Namba, Hideo Ito
2011 J jnl
Construction of BILBO FF with Soft-Error-Tolerant Capability.
IEICE Trans. Inf. Syst.
Kazuteru Namba, Hideo Ito
2011 J jnl
Scan FF Reordering for Test Volume Reduction in Chiba-scan Architecture.
IPSJ Trans. Syst. LSI Des. Methodol.
Kiyonori Matsumoto, Kazuteru Namba, Hideo Ito
2011 J jnl
Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits.
IEEE Trans. Computers
Kazuteru Namba, Hideo Ito
2010 — conf
A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit.
Asian Test Symposium
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
2010 J jnl
Chiba Scan Delay Fault Testing with Short Test Application Time.
J. Electron. Test.
Kazuteru Namba, Hideo Ito
2010 J jnl
Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing.
IEEE Trans. Very Large Scale Integr. Syst.
Kazuteru Namba, Takashi Ikeda, Hideo Ito
2010 C conf
Quantitative Evaluation of Integrity for Remote System Using the Internet.
PRDC
Masato Kitakami, Hiroshi Konno, Kazuteru Namba, Hideo Ito
2010 — conf
Single Event Induced Double Node Upset Tolerant Latch.
DFT
Kazuteru Namba, Masatoshi Sakata, Hideo Ito
2010 J jnl
Single-Event-Upset Tolerant RS Flip-Flop with Small Area.
IEICE Trans. Inf. Syst.
Kazuteru Namba, Kengo Nakashima, Hideo Ito
2010 — conf
Soft Error Tolerant BILBO FF.
DFT
Kazuteru Namba, Hideo Ito
2009 — conf
A Delay Measurement Technique Using Signature Registers.
Asian Test Symposium
Kentaroh Katoh, Toru Tanabe, Haque Md Zahidul, Kazuteru Namba, Hideo Ito
2009 J jnl
Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kazuteru Namba, Hideo Ito
2009 J jnl
Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability.
IEICE Trans. Inf. Syst.
Shuangyu Ruan, Kazuteru Namba, Hideo Ito
2009 C conf
Dependability Evaluation for Internet-Based Remote Systems.
PRDC
Masato Kitakami, Akihiro Katada, Kazuteru Namba, Hideo Ito
2009 J jnl
Design for Delay Fault Testability of 2-Rail Logic Circuits.
IEICE Trans. Inf. Syst.
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
2009 J jnl
Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths.
IEICE Trans. Inf. Syst.
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
2009 J jnl
Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding.
J. Electron. Test.
Kazuteru Namba, Yoshikazu Matsui, Hideo Ito
2009 J jnl
Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding.
IEICE Trans. Inf. Syst.
Kazuteru Namba, Hideo Ito
2009 — conf
Testing of Switch Blocks in Three-Dimensional FPGA.
DFT
Takumi Hoshi, Kazuteru Namba, Hideo Ito
2008 J jnl
A Checkpointing Method with Small Checkpoint Latency.
IEICE Trans. Inf. Syst.
Masato Kitakami, Bochuan Cai, Hideo Ito
2008 J jnl
Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger.
J. Electron. Test.
Yoichi Sasaki, Kazuteru Namba, Hideo Ito
2008 J jnl
Connectivity of Generalized Hierarchical Completely-Connected Networks.
J. Interconnect. Networks
Toshinori Takabatake, Tomoki Nakamigawa, Hideo Ito
2008 — conf
Delay Fault Testability on Two-Rail Logic Circuits.
DFT
Kazuteru Namba, Hideo Ito
2008 C conf
Path Delay Fault Test Set for Two-Rail Logic Circuits.
PRDC
Kazuteru Namba, Hideo Ito
2008 — conf
Soft Error Hardened FF Capable of Detecting Wide Error Pulse.
DFT
Shuangyu Ruan, Kazuteru Namba, Hideo Ito
2008 J jnl
Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability.
Inf. Media Technol.
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
2008 J jnl
Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability.
IPSJ Trans. Syst. LSI Des. Methodol.
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
2007 — conf
Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability.
DFT
Abderrahim Doumar, Kentaroh Katoh, Hideo Ito
2007 J jnl
Low-Cost IP Core Test Using Tri-Template-Based Codes.
IEICE Trans. Inf. Syst.
Gang Zeng, Hideo Ito
2007 — conf
Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing.
DFT
Takashi Ikeda, Kazuteru Namba, Hideo Ito
2006 B conf
Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices.
ETS
Kentaroh Katoh, Hideo Ito
2006 J jnl
Concurrent Core Testing for SOC Using Merged Test Set and Scan Tree.
IEICE Trans. Inf. Syst.
Gang Zeng, Hideo Ito
2006 A conf
Concurrent core test for SOC using shared test set and scan chain disable.
DATE
Gang Zeng, Hideo Ito
2006 — conf
Interleaving of Delay Fault Tes Data for Efficient Test Compression with Statistical Coding.
ATS
Kazuteru Namba, Hideo Ito
2006 — conf
Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters.
DFT
Gang Zeng, Youhua Shi, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito
2006 J jnl
Proposal of Testable Multi-Context FPGA Architecture.
IEICE Trans. Inf. Syst.
Kazuteru Namba, Hideo Ito
2006 J jnl
Redundant Design for Wallace Multiplier.
IEICE Trans. Inf. Syst.
Kazuteru Namba, Hideo Ito
2006 — conf
Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit.
DFT
Yoichi Sasaki, Kazuteru Namba, Hideo Ito
2005 C conf
Concurrent Core Test for Test Cost Reduction Using Merged Test Set and Scan Tree.
ICCD
Gang Zeng, Hideo Ito
2005 C conf
Design of Defect Tolerant Wallace Multiplier.
PRDC
Kazuteru Namba, Hideo Ito
2005 C conf
Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift.
IOLTS
Kentaroh Katoh, Abderrahim Doumar, Hideo Ito
2005 J jnl
Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation.
IEICE Trans. Inf. Syst.
Kazuteru Namba, Hideo Ito
2005 J jnl
Hybrid Pattern BIST for Low-Cost Core Testing Using Embedded FPGA Core.
IEICE Trans. Inf. Syst.
Gang Zeng, Hideo Ito
2005 J jnl
Scan Design for Two-Pattern Test without Extra Latches.
IEICE Trans. Inf. Syst.
Kazuteru Namba, Hideo Ito
2005 J jnl
X-Tolerant Test Data Compression for SOC with Enhanced Diagnosis Capability.
IEICE Trans. Inf. Syst.
Gang Zeng, Hideo Ito
2004 C conf
Fault-Tolerant Message Switching Based on Wormhole Switching and Backtracking.
PRDC
Manabu Sueishi, Masato Kitakami, Hideo Ito
2004 Misc conf
Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core.
VTS
Gang Zeng, Hideo Ito
2004 — conf
Non-Intrusive Test Compression for SOC Using Embedded FPGA Core.
DFT
Gang Zeng, Hideo Ito
2003 J jnl
Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey.
IEEE Trans. Very Large Scale Integr. Syst.
Abderrahim Doumar, Hideo Ito
2003 — conf
Efficient Test Data Decompression for System-on-a-Chip Using an Embedded FPGA Core.
DFT
Gang Zeng, Hideo Ito
2002 — conf
A Fault-tolerant Routing Strategy for Generalized Hierarchical Completely-connected Networks.
IASTED PDCS
Toshinori Takabatake, Masato Kitakami, Hideo Ito
2002 C conf
Fault-Tolerant Properties of Generalized Hierarchical Completely-Connected Networks.
PRDC
Toshinori Takabatake, Masato Kitakami, Hideo Ito
2002 — conf
Optimal Seed Generation for Delay Fault Detection BIST.
Asian Test Symposium
Lihong Tong, Kazuki Suzuki, Hideo Ito
2001 C conf
Escape and Restoration Routing: Suspensive Deadlock Recovery in Interconnection Networks.
PRDC
Toshinori Takabatake, Masato Kitakami, Hideo Ito
2001 C conf
Fault-Tolerance of Functional Programs Based on the Parallel Graph Reduction.
PRDC
Masato Kitakami, Shunji Kubota, Hideo Ito
2000 — conf
Design of Switching Blocks Tolerating Defects/Faults in FPGA Interconnection Resources.
DFT
Abderrahim Doumar, Hideo Ito
2000 — conf
Testing approach within FPGA-based fault tolerant systems.
Asian Test Symposium
Abderrahim Doumar, Hideo Ito
1999 C conf
An Automatic Testing and Diagnosis for FPGAs.
PRDC
Abderrahim Doumar, Hideo Ito
1999 — conf
Defect and Fault Tolerance FPGAs by Shifting the Configuration Data.
DFT
Abderrahim Doumar, Satoshi Kaneko, Hideo Ito
1999 — conf
Design of an automatic testing for FPGAs.
ETW
Abderrahim Doumar, Toshiaki Ohmameuda, Hideo Ito
1999 — conf
Fault-Tolerant Routing Algorithms for Hypercube Networks.
IPPS/SPDP
Keiichi Kaneko, Hideo Ito
1999 — conf
Generalized Hierarchical Completely-Connected Networks.
ISPAN
Toshinori Takabatake, Keiichi Kaneko, Hideo Ito
1999 C conf
LLT and LTn Schemes: Error Recovery Schemes in Mobile Environments.
PRDC
Mikio Yagi, Keiichi Kaneko, Hideo Ito
1999 — conf
Testing the Logic Cells and Interconnect Resources for FPGAs.
Asian Test Symposium
Abderrahim Doumar, Hideo Ito
1998 J jnl
Improving the Performance of Feedforward Neural Networks by Noise Injection into Hidden Neurons.
J. Intell. Robotic Syst.
Hammadi Nait-Charif, Hideo Ito
1994 — conf
Fault Tolerant Design Using Error Correcting Code for Multilayer Neural Networks.
DFT
Hideo Ito, Takashi Yagi
1993 — conf
A Defect-Tolerant Design for WSI Interconnection Networks and Its Application to Hypercube.
DFT
Hideo Ito
1991 J jnl
A hypercube design on wafer-scale integration.
Syst. Comput. Jpn.
Hideo Ito, Nobuyuki Suzuki