Hideo Fujiwara

262 papers A* 4A 23B 13C 11Misc 15Journal 105Unranked 91
YearRankTypeTitle / Venue / Authors
2020 J jnl
Universal Testing for Linear Feed-Forward/Feedback Shift Registers.
IEICE Trans. Inf. Syst.
Hideo Fujiwara, Katsuya Fujiwara, Toshinori Hosokawa
2019 C conf
A Test Generation Method Based on k-Cycle Testing for Finite State Machines.
IOLTS
Yuya Kinoshita, Toshinori Hosokawa, Hideo Fujiwara
2018 J jnl
Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip Testing.
ACM Trans. Design Autom. Electr. Syst.
Dong Xiang, Krishnendu Chakrabarty, Hideo Fujiwara
2017 J jnl
Synthesis and Enumeration of Generalized Shift Registers for Strongly Secure SR-Equivalents.
IEICE Trans. Inf. Syst.
Hideo Fujiwara, Katsuya Fujiwara
2016 B conf
A scheduling method for hierarchical testability based on test environment generation results.
ETS
Jun Nishimaki, Toshinori Hosokawa, Hideo Fujiwara
2016 A conf
A unified test and fault-tolerant multicast solution for network-on-chip designs.
ITC
Dong Xiang, Krishnendu Chakrabarty, Hideo Fujiwara
2016 J jnl
Multicast-Based Testing and Thermal-Aware Test Scheduling for 3D ICs with a Stacked Network-on-Chip.
IEEE Trans. Computers
Dong Xiang, Krishnendu Chakrabarty, Hideo Fujiwara
2016 J jnl
Properties of Generalized Feedback Shift Registers for Secure Scan Design.
IEICE Trans. Inf. Syst.
Hideo Fujiwara, Katsuya Fujiwara
2016 J jnl
Realization of SR-Equivalents Using Generalized Shift Registers for Secure Scan Design.
IEICE Trans. Inf. Syst.
Hideo Fujiwara, Katsuya Fujiwara
2015 — conf
A Test Generation Method for Data Paths Using Easily Testable Functional Time Expansion Models and Controller Augmentation.
ATS
Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa, Hideo Fujiwara
2015 J jnl
One More Class of Sequential Circuits having Combinational Test Generation Complexity.
J. Electron. Test.
Debesh Kumar Das, Hideo Fujiwara
2015 J jnl
Strongly Secure Scan Design Using Generalized Feed Forward Shift Registers.
IEICE Trans. Inf. Syst.
Hideo Fujiwara, Katsuya Fujiwara
2013 J jnl
Generalized Feed Forward Shift Registers and Their Application to Secure Scan Design.
IEICE Trans. Inf. Syst.
Katsuya Fujiwara, Hideo Fujiwara
2013 J jnl
Secure and Testable Scan Design Utilizing Shift Register Quasi-equivalents.
IPSJ Trans. Syst. LSI Des. Methodol.
Katsuya Fujiwara, Hideo Fujiwara, Hideo Tamamoto
2013 C conf
Thermal-aware test scheduling for NOC-based 3D integrated circuits.
VLSI-SoC
Dong Xiang, Gang Liu, Krishnendu Chakrabarty, Hideo Fujiwara
2012 J jnl
A Failure Prediction Strategy for Transistor Aging.
IEEE Trans. Very Large Scale Integr. Syst.
Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara
2012 J jnl
Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints.
J. Electron. Test.
Taavi Viilukas, Anton Karputkin, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Hideo Fujiwara
2012 J jnl
Test Pattern Ordering and Selection for High Quality Test Set under Constraints.
IEICE Trans. Inf. Syst.
Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hideo Fujiwara
2011 J jnl
A New Design-for-Testability Method Based on Thru-Testability.
J. Electron. Test.
Chia Yee Ooi, Hideo Fujiwara
2011 J jnl
Balanced Secure Scan: Partial Scan Approach for Secret Information Protection.
J. Electron. Test.
Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara
2011 B conf
Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits.
ETS
Jaan Raik, Anna Rannaste, Maksim Jenihhin, Taavi Viilukas, Raimund Ubar, Hideo Fujiwara
2011 J jnl
Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design.
IEICE Trans. Inf. Syst.
Katsuya Fujiwara, Hideo Fujiwara, Hideo Tamamoto
2011 B conf
F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG.
ETS
Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara
2011 J jnl
F-Scan: A DFT Method for Functional Scan at RTL.
IEICE Trans. Inf. Syst.
Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara
2011 A conf
Faster-than-at-speed test for increased test quality and in-field reliability.
ITC
Tomokazu Yoneda, Keigo Hori, Michiko Inoue, Hideo Fujiwara
2011 — conf
Secure scan design using shift register equivalents against differential behavior attack.
ASP-DAC
Hideo Fujiwara, Katsuya Fujiwara, Hideo Tamamoto
2011 B conf
Temperature-Variation-Aware Test Pattern Optimization.
ETS
Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato, Hideo Fujiwara
2010 J jnl
A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint.
IEICE Trans. Inf. Syst.
Ryoichi Inoue, Toshinori Hosokawa, Hideo Fujiwara
2010 J jnl
A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification.
IEICE Trans. Inf. Syst.
Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara
2010 C conf
A synthesis method to propagate false path information from RTL to gate level.
DDECS
Satoshi Ohtake, Hiroshi Iwata, Hideo Fujiwara
2010 C conf
Aging test strategy and adaptive test scheduling for SoC failure prediction.
IOLTS
Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara
2010 — conf
Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits.
Asian Test Symposium
Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
2010 — conf
Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power.
Asian Test Symposium
Zhiqiang You, Jiedi Huang, Michiko Inoue, Jishun Kuang, Hideo Fujiwara
2010 A conf
Constrained ATPG for functional RTL circuits using F-Scan.
ITC
Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara
2010 J jnl
Design and Optimization of Transparency-Based TAM for SoC Test.
IEICE Trans. Inf. Syst.
Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara
2010 — conf
Enabling False Path Identification from RTL for Reducing Design and Test Futileness.
DELTA
Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara
2010 — conf
Graph theoretic approach for scan cell reordering to minimize peak shift power.
ACM Great Lakes Symposium on VLSI
Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara
2010 Misc conf
On Minimization of Test Application Time for RAS.
VLSI Design
Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh
2010 A conf
RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage.
ITC
Alodeep Sanyal, Krishnendu Chakrabarty, Mahmut Yilmaz, Hideo Fujiwara
2010 J jnl
RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences.
J. Electron. Test.
Hongxia Fang, Krishnendu Chakrabarty, Hideo Fujiwara
2010 — conf
RedSOCs-3D: Thermal-safe test scheduling for 3D-stacked SOC.
APCCAS
Fawnizu Azmadi Hussin, Thomas Edison Yu, Tomokazu Yoneda, Hideo Fujiwara
2010 C conf
SREEP: Shift Register Equivalents Enumeration and Synthesis Program for secure scan design.
DDECS
Katsuya Fujiwara, Hideo Fujiwara, Marie Engelene J. Obien, Hideo Tamamoto
2010 B conf
Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach.
ETS
Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara
2010 — conf
Secure and testable scan design using extended de Bruijn graphs.
ASP-DAC
Hideo Fujiwara, Marie Engelene J. Obien
2010 — conf
Seed Ordering and Selection for High Quality Delay Test.
Asian Test Symposium
Tomokazu Yoneda, Michiko Inoue, Akira Taketani, Hideo Fujiwara
2010 B conf
Test pattern selection to optimize delay test quality with a limited size of test set.
ETS
Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara
2010 Misc conf
Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing.
VTS
Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Hideo Fujiwara
2009 Misc conf
A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification.
VTS
Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara
2009 A conf
Brief Announcement: Acceleration by Contention for Shared Memory Mutual Exclusion Algorithms.
DISC
Michiko Inoue, Tsuyoshi Suzuki, Hideo Fujiwara
2009 — conf
Fast false path identification based on functional unsensitizability using RTL information.
ASP-DAC
Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara
2009 B conf
Partial Scan Approach for Secret Information Protection.
ETS
Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara
2009 — conf
RTL DFT techniques to enhance defect coverage for functional test sequences.
HLDVT
Hongxia Fang, Krishnendu Chakrabarty, Hideo Fujiwara
2009 — conf
Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints.
ASP-DAC
Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara
2008 J jnl
A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi
2008 J jnl
A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dong Xiang, Yang Zhao, Krishnendu Chakrabarty, Hideo Fujiwara
2008 — conf
A Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint.
ATS
Ryoichi Inoue, Toshinori Hosokawa, Hideo Fujiwara
2008 J jnl
Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors.
IEICE Trans. Inf. Syst.
Masato Nakasato, Michiko Inoue, Satoshi Ohtake, Hideo Fujiwara
2008 J jnl
Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints.
IEICE Trans. Inf. Syst.
Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara
2008 — conf
Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths.
ATS
Thomas Edison Yu, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara
2008 — conf
Localized random access scan: Towards low area and routing overhead.
ASP-DAC
Yu Hu, Xiang Fu, Xiaoxin Fan, Hideo Fujiwara
2008 J jnl
NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints.
IEICE Trans. Inf. Syst.
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara
2008 J jnl
On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time.
IEICE Trans. Inf. Syst.
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara
2008 J jnl
Scheduling Power-Constrained Tests through the SoC Functional Bus.
IEICE Trans. Inf. Syst.
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara
2008 J jnl
Test Scheduling for Multi-Clock Domain SoCs under Power Constraint.
IEICE Trans. Inf. Syst.
Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara
2008 J jnl
Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips.
IEICE Trans. Inf. Syst.
Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara
2008 — conf
Untestable Fault Identification in Sequential Circuits Using Model-Checking.
ATS
Jaan Raik, Hideo Fujiwara, Raimund Ubar, Anna Krivenko
2008 A conf
Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects.
DATE
Tomokazu Yoneda, Hideo Fujiwara
2007 A* conf
A DFT Method for Time Expansion Model at Register Transfer Level.
DAC
Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara
2007 J jnl
Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability.
IEICE Trans. Inf. Syst.
Masato Nakasato, Satoshi Ohtake, Kewal K. Saluja, Hideo Fujiwara
2007 J jnl
Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on tau
IEICE Trans. Inf. Syst.
Chia Yee Ooi, Thomas Clouqueur, Hideo Fujiwara
2007 — conf
Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing.
ATS
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara
2007 J jnl
Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture.
IEEE Trans. Circuits Syst. II Express Briefs
Dong Xiang, Kaiwei Li, Hideo Fujiwara, Krishnaiyan Thulasiraman, Jiaguang Sun
2007 — conf
Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses.
ASP-DAC
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara
2007 J jnl
Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester.
IEEE Trans. Very Large Scale Integr. Syst.
Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara
2007 A conf
Efficient path delay test generation based on stuck-at test generation using checker circuitry.
ICCAD
Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara
2007 — conf
False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults.
ATS
Yuki Yoshikawa, Satoshi Ohtake, Hideo Fujiwara
2007 A conf
Fast and effective fault simulation for path delay faults based on selected testable paths.
ITC
Dong Xiang, Yang Zhao, Kaiwei Li, Hideo Fujiwara
2007 — conf
Fault-dependent/independent Test Generation Methods for State Observable FSMs.
ATS
Toshinori Hosokawa, Ryoichi Inoue, Hideo Fujiwara
2007 J jnl
Functional Constraints vs. Test Compression in Scan-Based Delay Testing.
J. Electron. Test.
Ilia Polian, Hideo Fujiwara
2007 A conf
Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers.
DATE
Tomokazu Yoneda, Masahiro Imanishi, Hideo Fujiwara
2007 — conf
Multi-Frequency Modular Testing of SoCs by Dynamically Reconfiguring Multi-Port ATE.
ATS
Dan Zhao, Ronghua Huang, Hideo Fujiwara
2007 B conf
Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints.
ETS
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara
2007 C conf
Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing.
ISCAS
Dan Zhao, Ronghua Huang, Tomokazu Yoneda, Hideo Fujiwara
2007 J jnl
Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction.
IEEE Trans. Computers
Dong Xiang, Kaiwei Li, Jiaguang Sun, Hideo Fujiwara
2007 — conf
Scan Testing for Complete Coverage of Path Delay Faults with Reduced Test Data Volume, Test Application Time, and Hardware Cost.
ATS
Dong Xiang, Krishnendu Chakrabarty, Dianwei Hu, Hideo Fujiwara
2007 — conf
Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores.
ASP-DAC
Dan Zhao, Unni Chandran, Hideo Fujiwara
2007 Misc conf
TAM Design and Optimization for Transparency-Based SoC Test.
VTS
Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara
2007 — conf
Test Scheduling for Memory Cores with Built-In Self-Repair.
ATS
Tomokazu Yoneda, Yuusuke Fukuda, Hideo Fujiwara
2007 — conf
Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip.
ATS
Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara
2007 Misc conf
Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints.
VTS
Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara
2007 J jnl
Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST.
IEEE Trans. Computers
Dong Xiang, Mingjing Chen, Hideo Fujiwara
2006 J jnl
A Low Power Deterministic Test Using Scan Chain Disable Technique.
IEICE Trans. Inf. Syst.
Zhiqiang You, Tsuyoshi Iwagaki, Michiko Inoue, Hideo Fujiwara
2006 J jnl
A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips.
IEICE Trans. Inf. Syst.
Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara
2006 C conf
A New Class of Sequential Circuits with Acyclic Test Generation Complexity.
ICCD
Chia Yee Ooi, Hideo Fujiwara
2006 — conf
A New Scan Design Technique Based on Pre-Synthesis Thru Functions.
ATS
Chia Yee Ooi, Hideo Fujiwara
2006 C conf
A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits.
VLSI-SoC
Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
2006 — conf
A memory grouping method for sharing memory BIST logic.
ASP-DAC
Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara
2006 Misc conf
BIST Pretest of ICs: Risks and Benefits.
VTS
Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara
2006 — conf
Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation.
VLSI-SoC (Selected Papers)
Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
2006 — conf
Compressing Test Data for Deterministic BIST Using a Reconfigurable Scan Arhcitecture.
ATS
Hideo Fujiwara, Jiaguang Sun, Krishnendu Chakrabarty, Yang Zhao, Dong Xiang
2006 — conf
Design for Testability of Software-Based Self-Test for Processors.
ATS
Masato Nakazato, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
2006 J jnl
Design for consecutive transparency method of RTL circuits.
Syst. Comput. Jpn.
Tomokazu Yoneda, Hideo Fujiwara
2006 — conf
Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester.
ATS
Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara
2006 J jnl
Effect of BIST Pretest on IC Defect Level.
IEICE Trans. Inf. Syst.
Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara
2006 — conf
Electrical Behavior of GOS Fault affected Domino Logic Cell.
DELTA
Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell
2006 J jnl
Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch.
IEICE Trans. Inf. Syst.
Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara
2006 A conf
Functional constraints vs. test compression in scan-based delay testing.
DATE
Ilia Polian, Hideo Fujiwara
2006 C conf
Generating Compact Robust and Non-Robust Tests for Complete Coverage of Path Delay Faults Based on Stuck-at Tests.
ICCD
Dong Xiang, Kaiwei Li, Hideo Fujiwara, Jiaguang Sun
2006 J jnl
Instruction-Based Self-Testing of Delay Faults in Pipelined Processors.
IEEE Trans. Very Large Scale Integr. Syst.
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
2006 — conf
Low-Cost Hardening of Image Processing Applications Against Soft Errors.
DFT
Ilia Polian, Bernd Becker, Masato Nakasato, Satoshi Ohtake, Hideo Fujiwara
2006 C conf
Power-Constrained SOC Test Schedules through Utilization of Functional Buses.
ICCD
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara
2006 A conf
Power-constrained test scheduling for multi-clock domain SoCs.
DATE
Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara
2006 J jnl
System-on-chip test scheduling with reconfigurable core wrappers.
IEEE Trans. Very Large Scale Integr. Syst.
Erik Larsson, Hideo Fujiwara
2005 — conf
A Class of Linear Space Compactors for Enhanced Diagnostic.
Asian Test Symposium
Thomas Clouqueur, Hideo Fujiwara, Kewal K. Saluja
2005 — conf
A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency.
Asian Test Symposium
Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara
2005 B conf
Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation.
ETS
Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
2005 — conf
An Effective Design for Hierarchical Test Generation Based on Strong Testability.
Asian Test Symposium
Hideyuki Ichihara, Tomoo Inoue, Naoki Okamoto, Toshinori Hosokawa, Hideo Fujiwara
2005 J jnl
Classification of Sequential Circuits Based on tau
IEICE Trans. Inf. Syst.
Chia Yee Ooi, Thomas Clouqueur, Hideo Fujiwara
2005 J jnl
Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST.
IEICE Trans. Inf. Syst.
Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara
2005 J jnl
Delay Fault Testing of Processor Cores in Functional Mode.
IEICE Trans. Inf. Syst.
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
2005 A conf
Design and analysis of multiple weight linear compactors of responses containing unknown values.
ITC
Thomas Clouqueur, Kamran Zarrineh, Kewal K. Saluja, Hideo Fujiwara
2005 — conf
Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops.
Asian Test Symposium
Dong Xiang, Kaiwei Li, Hideo Fujiwara
2005 — conf
Design for Testability Based on Single-Port-Change Delay Testing for Data Paths.
Asian Test Symposium
Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
2005 — conf
Efficient Constraint Extraction for Template-Based Processor Self-Test Generation.
Asian Test Symposium
Kazuko Kambe, Michiko Inoue, Hideo Fujiwara, Tsuyoshi Iwagaki
2005 J jnl
Improving test effectiveness of scan-based BIST by scan chain partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara
2005 — conf
Instruction-based delay fault self-testing of pipelined processor cores.
ISCAS (6)
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
2005 — conf
Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability.
Asian Test Symposium
Tomokazu Yoneda, Hisakazu Takakuwa, Hideo Fujiwara
2005 J jnl
Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths.
IEICE Trans. Inf. Syst.
Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara
2005 B conf
Testing Superscalar Processors in Functional Mode.
FPL
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
2005 — conf
Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BIST.
Asian Test Symposium
Dong Xiang, Ming-Jing Chen, Hideo Fujiwara
2004 J jnl
A DFT Selection Method for Reducing Test Application Time of System-on-Chips.
IEICE Trans. Inf. Syst.
Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara
2004 B conf
A design methodology to realize delay testable controllers using state transition information.
ETS
Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
2004 B conf
An efficient scan tree design for test time reduction.
ETS
Yannick Bonhomme, Tomokazu Yoneda, Hideo Fujiwara, Patrick Girard
2004 — conf
Classification of Sequential Circuits Based on ?k Notation.
Asian Test Symposium
Chia Yee Ooi, Hideo Fujiwara
2004 J jnl
Design & Test Education in Asia.
IEEE Des. Test Comput.
Debesh K. Das, Hideo Fujiwara, Yungang Li, Yinghua Min, Shiyi Xu, Yervant Zorian
2004 — conf
Efficient Template Generation for Instruction-Based Self-Test of Processor Cores.
Asian Test Symposium
Kazuko Kambe, Michiko Inoue, Hideo Fujiwara
2004 J jnl
Efficient test solutions for core-based designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng
2004 Misc conf
Instruction-Based Delay Fault Self-Testing of Processor Cores.
VLSI Design
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
2004 — conf
Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity.
Asian Test Symposium
Debesh Kumar Das, Tomoo Inoue, Susanta Chakraborty, Hideo Fujiwara
2004 J jnl
New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency.
J. Electron. Test.
Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara
2004 — conf
Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths.
Asian Test Symposium
Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara
2004 J jnl
Preemptive System-on-Chip Test Scheduling.
IEICE Trans. Inf. Syst.
Erik Larsson, Hideo Fujiwara
2003 — conf
A DFT Selection Method for Reducing Test Application Time of System-on-Chips.
Asian Test Symposium
Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara
2003 A conf
A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms.
DATE
Satoshi Ohtake, Kouhei Ohtani, Hideo Fujiwara
2003 — conf
A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint.
Asian Test Symposium
Toshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, Hideo Fujiwara
2003 A conf
Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability.
ITC
Tomokazu Yoneda, Tetsuo Uchiyama, Hideo Fujiwara
2003 Misc conf
Design for Consecutive Transparency of Cores in System-on-a-Chip.
VTS
Tomokazu Yoneda, Hideo Fujiwara
2003 — conf
Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning.
Asian Test Symposium
Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara
2003 — conf
Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict Analysis.
Asian Test Symposium
Dong Xiang, Shan Gu, Hideo Fujiwara
2003 J jnl
Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution.
IEEE Trans. Computers
Dong Xiang, Yi Xu, Hideo Fujiwara
2003 — conf
Optimal System-on-Chip Test Scheduling.
Asian Test Symposium
Erik Larsson, Hideo Fujiwara
2003 — conf
Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models.
Asian Test Symposium
Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
2003 — conf
Software-Based Delay Fault Testing of Processor Cores.
Asian Test Symposium
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
2003 Misc conf
Test Resource Partitioning and Optimization for SOC Designs.
VTS
Erik Larsson, Hideo Fujiwara
2003 — conf
Test Synthesis for Datapaths Using Datapath-Controller Functions.
Asian Test Symposium
Michiko Inoue, Kazuhiro Suzuki, Hiroyuki Okamoto, Hideo Fujiwara
2002 J jnl
A Latency Optimal Superstabilizing Mutual Exclusion Protocol in Unidirectional Rings.
J. Parallel Distributed Comput.
Yoshiaki Katayama, Eiichiro Ueda, Hideo Fujiwara, Toshimitsu Masuzawa
2002 Misc conf
A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits.
VTS
Satoshi Ohtake, Hideo Fujiwara, Shunjiro Miwa
2002 — conf
A Scheduling Method in High-Level Synthesis for Acyclic Partial Scan Design.
Asian Test Symposium
Tomoo Inoue, Tomokazu Miura, Akio Tamura, Hideo Fujiwara
2002 J jnl
A layout adjustment problem for disjoint rectangles preserving orthogonal order.
Syst. Comput. Jpn.
Kunihiko Hayashi, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
2002 J jnl
A nonscan DFT method for controllers to provide complete fault efficiency.
Syst. Comput. Jpn.
Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara
2002 C conf
An Extended Class of Sequential Circuits with Combinational Test Generation Complexity.
ICCD
Michiko Inoue, Chikateru Jinno, Hideo Fujiwara
2002 J jnl
Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores.
J. Electron. Test.
Tomokazu Yoneda, Hideo Fujiwara
2002 — conf
Design for Two-Pattern Testability of Controller-Data Path Circuits.
Asian Test Symposium
Atlaf Ul Amin, Satoshi Ohtake, Hideo Fujiwara
2002 — conf
Fault Set Partition for Efficient Width Compression.
Asian Test Symposium
Emil Gizdarski, Hideo Fujiwara
2002 J jnl
Handling the pin overhead problem of DFTs for high-quality and at-speed tests.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dong Xiang, Hideo Fujiwara
2002 — conf
Integrated Test Scheduling, Test Parallelization and TAMDesign.
Asian Test Symposium
Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng
2002 — conf
Non-Scan Design for Testability Based on Fault Oriented Conflict Analysis.
Asian Test Symposium
Dong Xiang, Shan Gu, Hideo Fujiwara
2002 J jnl
Parallel algorithms for selection on the BSP and BSP* models.
Syst. Comput. Jpn.
Takashi Ishimizu, Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
2002 — conf
Power constrained preemptive TAM scheduling.
ETW
Erik Larsson, Hideo Fujiwara
2002 J jnl
SPIRIT: a highly robust combinational test generation algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Emil Gizdarski, Hideo Fujiwara
2002 J jnl
Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption.
J. Electron. Test.
Michiko Inoue, Emil Gizdarski, Hideo Fujiwara
2002 J jnl
Test sequence compaction methods for acyclic sequential circuits using a time expansion model.
Syst. Comput. Jpn.
Toshinori Hosokawa, Tomoo Inoue, Toshihiro Hiraoka, Hideo Fujiwara
2001 — conf
A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability.
Asian Test Symposium
Tomokazu Yoneda, Hideo Fujiwara
2001 — conf
A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability.
ASP-DAC
Satoshi Ohtake, Shintaro Nagai, Hiroki Wada, Hideo Fujiwara
2001 A* conf
A Framework for Low Complexity Static Learning.
DAC
Emil Gizdarski, Hideo Fujiwara
2001 J jnl
A causal broadcast protocol for distributed mobile systems.
Syst. Comput. Jpn.
Chikara Ohori, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
2001 A conf
Adaptive Long-Lived O(k
DISC
Michiko Inoue, Shinya Umetani, Toshimitsu Masuzawa, Hideo Fujiwara
2001 — conf
BIST Method Based on Concurrent Single-Control Testability of RTL Data Paths.
Asian Test Symposium
Ken-ichi Yamaguchi, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara
2001 — conf
Design for Hierarchical Two-Pattern Testability of Data Paths.
Asian Test Symposium
Md. Altaf-Ul-Amin, Satoshi Ohtake, Hideo Fujiwara
2001 Misc conf
SPIRIT: A Highly Robust Combinational Test Generation Algorithm.
VTS
Emil Gizdarski, Hideo Fujiwara
2001 Misc conf
Testable Design of Sequential Circuits with Improved Fault Efficiency.
VLSI Design
Debesh Kumar Das, Bhargab B. Bhattacharya, Satoshi Ohtake, Hideo Fujiwara
2000 J jnl
A New Class of Sequential Circuits with Combinational Test Generation Complexity.
IEEE Trans. Computers
Hideo Fujiwara
2000 Misc conf
A New Definition and a New Class of Sequential Circuits with Combinational Test Generation Complexity.
VLSI Design
Hideo Fujiwara
2000 J jnl
A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency.
J. Electron. Test.
Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara
2000 — conf
A class of sequential circuits with combinational test generation complexity under single-fault assumption.
Asian Test Symposium
Michiko Inoue, Emil Gizdarski, Hideo Fujiwara
2000 — conf
A non-scan DFT method at register-transfer level to achieve complete fault efficiency.
ASP-DAC
Satoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara
2000 Misc conf
Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency.
VLSI Design
Hiroki Wada, Toshimitsu Masuzawa, Kewal K. Saluja, Hideo Fujiwara
2000 J jnl
LFSR-Based Deterministic TPG for Two-Pattern Testing.
J. Electron. Test.
Xiaowei Li, Paul Y. S. Cheung, Hideo Fujiwara
2000 A conf
Non-scan design for testability for synchronous sequential circuits based on conflict analysis.
ITC
Dong Xiang, Yi Xu, Hideo Fujiwara
2000 — conf
Single-control testability of RTL data paths for BIST.
Asian Test Symposium
Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara
2000 — conf
Spirit: satisfiability problem implementation for redundancy identification and test generation.
Asian Test Symposium
Emil Gizdarski, Hideo Fujiwara
2000 — conf
Strong self-testability for data paths high-level synthesis.
Asian Test Symposium
Xiaowei Li, Toshimitsu Masuzawa, Hideo Fujiwara
2000 A conf
Test Generation for Acyclic Sequential Circuits with Hold Registers.
ICCAD
Tomoo Inoue, Debesh Kumar Das, Chiiho Sano, Takahiro Mihara, Hideo Fujiwara
1999 — conf
A High-Level Synthesis Approach to Partial Scan Design Based on Acyclic Structure.
Asian Test Symposium
Tomoya Takasaki, Hideo Fujiwara, Tomoo Inoue
1999 — conf
A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description.
Asian Test Symposium
Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
1999 J jnl
A cost optimal parallel algorithm for weighted distance transforms.
Parallel Comput.
Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
1999 — conf
New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency.
Asian Test Symposium
Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara
1999 — conf
Parallel Algorithms for All Nearest Neighbors of Binary Images on the BSP Model.
ISPAN
Takashi Ishimizu, Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
1999 — conf
Static and Dynamic Test Sequence Compaction Methods for Acyclic Sequential Circuits Using a Time Expansion Model.
Asian Test Symposium
Toshinori Hosokawa, Toshihiro Hiraoka, Tomoo Inoue, Hideo Fujiwara
1998 — conf
A High-Level Synthesis Method for Weakly Testable Data Paths.
Asian Test Symposium
Michiko Inoue, Takeshi Higashimura, Kenji Noda, Toshimitsu Masuzawa, Hideo Fujiwara
1998 A conf
A Layout Adjustment Problem for Disjoint Rectangles Preserving Orthogonal Order.
GD
Kunihiko Hayashi, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
1998 — conf
A Non-Scan DFT Method for Controllers to Achieve Complete Fault Efficiency.
Asian Test Symposium
Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara
1998 — conf
An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits.
Asian Test Symposium
Tomoo Inoue, Toshinori Hosokawa, Takahiro Mihara, Hideo Fujiwara
1998 J jnl
An approach to test synthesis from higher level.
Integr.
Michiko Inoue, Hideo Fujiwara
1998 J jnl
Needed: Third-generation ATPG Benchmarks.
IEEE Des. Test Comput.
Hideo Fujiwara
1998 J jnl
On the synthesis of synchronizable finite state machines with partial scan.
Syst. Comput. Jpn.
Hiroshi Youra, Tomoo Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
1998 — conf
Partial Scan Design Methods Based on Internally Balanced Structure.
ASP-DAC
Tomoya Takasaki, Tomoo Inoue, Hideo Fujiwara
1998 J jnl
Partial scan design methods based on internally balanced structure.
Syst. Comput. Jpn.
Tomoya Takasaki, Tomoo Inoue, Hideo Fujiwara
1998 B conf
SelfStabilizing WaitFree Clock Synchronization with Bounded Space.
OPODIS
Sen Moriya, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
1998 J jnl
Universal Fault Diagnosis for Lookup Table FPGAs.
IEEE Des. Test Comput.
Tomoo Inoue, Satoshi Miyazaki, Hideo Fujiwara
1997 — conf
A Parallel Algorithm for Weighted Distance Transforms.
IPPS
Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
1997 — conf
A latency-optimal superstabilizing mutual exclusion protocol.
WSS
Eiichiro Ueda, Yoshiaki Katayama, Toshimitsu Masuzawa, Hideo Fujiwara
1997 J jnl
A sequential circuit structure with combinational test generation complexity and its application.
Syst. Comput. Jpn.
Hideo Fujiwara, Satoshi Ohtake, Tomoya Takasaki
1997 J jnl
Fault-tolerant distributed algorithms for autonomous mobile robots with crash faults.
Syst. Comput. Jpn.
Daisuke Yoshida, Toshimitsu Masuzawa, Hideo Fujiwara
1997 — conf
Non-scan design for testable data paths using thru operation.
ASP-DAC
Katsuyuki Takabatake, Toshimitsu Masuzawa, Michiko Inoue, Hideo Fujiwara
1997 J jnl
Non-scan design for testable data paths using thru operation.
Syst. Comput. Jpn.
Katsuyuki Takabatake, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
1997 — conf
On the Complexity of Universal Fault Diagnosis for Look-up Table FPGAs.
Asian Test Symposium
Tomoo Inoue, Satoshi Miyazaki, Hideo Fujiwara
1997 — conf
Optimal Wait-Free Clock Synchronisation Protocol on a Shared-Memory Multi-processor System.
WDAG
Michiko Inoue, Sen Moriya, Toshimitsu Masuzawa, Hideo Fujiwara
1997 J jnl
Parallel algorithms for connected-component problems of gray-scale images.
Syst. Comput. Jpn.
Akihiro Fujiwara, Toshimitsu Masuzawa, Hideo Fujiwara
1997 — conf
Sequential Test Generation Based on Circuit Pseudo-Transformation.
Asian Test Symposium
Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara
1997 — conf
Testing for the programming circuit of LUT-based FPGAs.
Asian Test Symposium
Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara
1996 A conf
A Snapshot Algorithm for Distributed Mobile Systems.
ICDCS
Yasuo Sato, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
1996 — conf
A Test Methodology for Interconnect Structures of LUT-based FPGAs.
Asian Test Symposium
Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara
1996 — conf
An Approach To The Synthesis Of Synchronizable Finite State Machines With Partial Scan.
Asian Test Symposium
Tomoo Inoue, Toshimitsu Masuzawa, Hiroshi Youra, Hideo Fujiwara
1995 Misc conf
A scheduling problem in test generation.
VTS
Tomoo Inoue, Hironori Maeda, Hideo Fujiwara
1995 J jnl
An Optimal Parallel Algorithm for the Euclidean Distance Maps of 2-D Binary Images.
Inf. Process. Lett.
Akihiro Fujiwara, Toshimitsu Masuzawa, Hideo Fujiwara
1995 J jnl
Foreword.
IEICE Trans. Inf. Syst.
Hideo Fujiwara
1995 J jnl
Optimal Granularity and Scheme of Parallel Test Generation in a Distributed System.
IEEE Trans. Parallel Distributed Syst.
Hideo Fujiwara, Tomoo Inoue
1995 — conf
Universal test complexity of field-programmable gate arrays.
Asian Test Symposium
Tomoo Inoue, Hideo Fujiwara, Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto
1994 J jnl
A method of search space pruning based on search state dominance.
Syst. Comput. Jpn.
Takayuki Fujino, Hideo Fujiwara
1993 J jnl
A Search Space Pruning Method for Test Pattern Generation using Search State Dominance.
J. Circuits Syst. Comput.
Takayuki Fujino, Hideo Fujiwara
1993 J jnl
Parity-scan design to reduce the cost of test application.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hideo Fujiwara, Akihiro Yamamoto
1992 — conf
An Efficient Test Generation Algorithm Based on Search State Dominance.
FTCS
Takayuki Fujino, Hideo Fujiwara
1992 A conf
Parity-Scan Design to Reduce the Cost of Test Application.
ITC
Hideo Fujiwara, Akihiro Yamamoto
1990 J jnl
Computational Complexity of Controllability/Observability Problems for Combinational Circuits.
IEEE Trans. Computers
Hideo Fujiwara
1990 J jnl
Optimal granularity of test generation in a distributed system.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hideo Fujiwara, Tomoo Inoue
1990 — conf
Three-valued neural networks for test generation.
FTCS
Hideo Fujiwara
1989 J jnl
Enhancing random-pattern coverage of programmable logic arrays via masking technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hideo Fujiwara
1989 A conf
Optimal granularity of test generation in a distributed system.
ICCAD
Hideo Fujiwara, Tomoo Inoue
1988 J jnl
A design of programmable logic arrays with random pattern-testability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hideo Fujiwara
1988 — conf
Computational complexity of controllability/observability problems for combinational circuits.
FTCS
Hideo Fujiwara
1988 A conf
Enhancing Random-Pattern Coverage of Programmable Logic Arrays via Masking Technique.
ITC
Hideo Fujiwara, Osamu Fujisawa, Kazunori Hikone
1988 J jnl
Test research in Japan.
IEEE Des. Test
Hideo Fujiwara, Yuzo Takamatsu, Takashi Nanya, Teruhiko Yamada, Hideo Tamamoto, Kiyoshi Furuya
1987 J jnl
A New Built-In Self-Test Design for PLA's with High Fault Coverage and Low Overhead.
IEEE Trans. Computers
Robert P. Treuer, Vinod K. Agarwal, Hideo Fujiwara
1987 J jnl
A random-pattern testable design for programmable logic arrays.
Syst. Comput. Jpn.
Hideo Fujiwara
1986 J jnl
Design for testability and built-in self-test for VLSI circuits.
Microprocess. Microsystems
Hideo Fujiwara
1985 A conf
A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead.
ITC
Hideo Fujiwara, Kewal K. Saluja, Kozo Kinoshita
1985 J jnl
Implementing a Built-In Self-Test PLA Design.
IEEE Des. Test
Robert P. Treuer, Hideo Fujiwara, Vinod K. Agarwal
1984 J jnl
A New PLA Design for Universal Testability.
IEEE Trans. Computers
Hideo Fujiwara
1984 J jnl
Design for Testability for Complete Test Coverage.
IEEE Des. Test
Akira Motohara, Hideo Fujiwara
1983 J jnl
An Easily Testable Design of Programmable Logic Arrays for Multiple Faults.
IEEE Trans. Computers
Kewal K. Saluja, Kozo Kinoshita, Hideo Fujiwara
1983 J jnl
On the Acceleration of Test Generation Algorithms.
IEEE Trans. Computers
Hideo Fujiwara, Takeshi Shimono
1983 A* conf
Test generation for scan design circuits with tri-state modules and bidirectional terminals.
DAC
Takuji Ogihara, Shinichi Murai, Yuzo Takamatsu, Kozo Kinoshita, Hideo Fujiwara
1982 J jnl
The Complexity of Fault Detection Problems for Combinational Logic Circuits.
IEEE Trans. Computers
Hideo Fujiwara, Shunichi Toida
1981 J jnl
A Design of Programmable Logic Arrays with Universal Tests.
IEEE Trans. Computers
Hideo Fujiwara, Kozo Kinoshita
1981 J jnl
On Closedness and Test Complexity of Logic Circuits.
IEEE Trans. Computers
Hideo Fujiwara
1978 J jnl
Connection Assignments for Probabilistically Diagnosable Systems.
IEEE Trans. Computers
Hideo Fujiwara, Kozo Kinoshita
1978 A* conf
LORES - Logic Reorganization System.
DAC
Shunichiro Nakamura, Shinichi Murai, Chiyoji Tanaka, Masayuki Terai, Hideo Fujiwara, Kozo Kinoshita
1978 J jnl
On the Computational Complexity of System Diagnosis.
IEEE Trans. Computers
Hideo Fujiwara, Kozo Kinoshita
1978 J jnl
Some Existence Theorems for Probabilistically Diagnosable Systems.
IEEE Trans. Computers
Hideo Fujiwara, Kozo Kinoshita
1975 J jnl
Easily Testable Sequential Machines with Extra Inputs.
IEEE Trans. Computers
Hideo Fujiwara, Yoich Nagao, Tsutomu Sasao, Kozo Kinoshita
1974 J jnl
Design of Diagnosable Sequential Machines Utilizing Extra Outputs.
IEEE Trans. Computers
Hideo Fujiwara, Kozo Kinoshita