Hideki Asai - RankMe

90 papers A* 3A 3B 6C 11Journal 27Unranked 40

Year	Rank	Type	Title / Venue / Authors
2022	A*	`conf`	A Stochastic Momentum Accelerated Quasi-Newton Method for Neural Networks (Student Abstract). AAAI S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai
2022	J	`jnl`	Accelerating Symmetric Rank-1 Quasi-Newton Method with Nesterov's Gradient for Training Neural Networks. Algorithms S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai
2022	A*	`conf`	On the Practical Robustness of the Nesterov's Accelerated Quasi-Newton Method. AAAI S. Indrapriyadarsini, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai
2021	J	`jnl`	A modified limited memory Nesterov's accelerated quasi-Newton. CoRR S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai
2020	J	`jnl`	A Nesterov's Accelerated quasi-Newton method for Global Routing using Deep Reinforcement Learning. CoRR S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai
2020	C	`conf`	A Neural Network Approach to Analog Circuit Design Optimization using Nesterov's Accelerated Quasi-Newton Method. ISCAS S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai
2019	—	`conf`	A Stochastic Quasi-Newton Method with Nesterov's Accelerated Gradient. ECML/PKDD (1) S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Hideki Asai
2019	J	`jnl`	A Stochastic Quasi-Newton Method with Nesterov's Accelerated Gradient. CoRR S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Hideki Asai
2019	C	`conf`	A Stochastic Variance Reduced Nesterov's Accelerated Quasi-Newton Method. ICMLA Sota Yasuda, Shahrzad Mahboubi, S. Indrapriyadarsini, Hiroshi Ninomiya, Hideki Asai
2019	J	`jnl`	A Stochastic Variance Reduced Nesterov's Accelerated Quasi-Newton Method. CoRR Sota Yasuda, Shahrzad Mahboubi, S. Indrapriyadarsini, Hiroshi Ninomiya, Hideki Asai
2019	J	`jnl`	An Adaptive Stochastic Nesterov Accelerated Quasi Newton Method for Training RNNs. CoRR S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Hideki Asai
2019	J	`jnl`	Implementation of a modified Nesterov's Accelerated quasi-Newton Method on Tensorflow. CoRR S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Hideki Asai
2019	—	`conf`	Momentum Acceleration of Quasi-Newton Training for Neural Networks. PRICAI (2) Shahrzad Mahboubi, S. Indrapriyadarsini, Hiroshi Ninomiya, Hideki Asai
2018	C	`conf`	Implementation of a Modified Nesterov's Accelerated Quasi-Newton Method on Tensorflow. ICMLA S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Hideki Asai
2017	—	`conf`	SI/PI/EMI simulation techniques and application to automotive electronic design issues. MIXDES Hideki Asai
2014	J	`jnl`	Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hideki Asai
2014	—	`conf`	HIE-block latency insertion method for fast transient simulation of nonuniform multiconductor transmission lines. ASP-DAC Takahiro Takasaki, Tadatoshi Sekine, Hideki Asai
2013	—	`conf`	Unconditionally stable explicit method for the fast 3-D simulation of on-chip power distribution network with through silicon via. ASP-DAC Tadatoshi Sekine, Hideki Asai
2012	—	`conf`	Predictor-corrector latency insertion method for fast transient analysis of ill-constructed circuits. ASP-DAC Hiroki Kurobe, Tadatoshi Sekine, Hideki Asai
2010	—	`conf`	A novel FDTD algorithm based on alternating-direction explicit method with PML absorbing boundary condition. ASP-DAC Shuichi Aono, Masaki Unno, Hideki Asai
2010	J	`jnl`	An Approach for Practical Use of Common-Mode Noise Reduction Technique for In-Vehicle Electronic Equipment. IEICE Trans. Commun. Takanori Uno, Kouji Ichikawa, Yuichi Mabuchi, Atsushi Nakamura, Yuji Okazaki, Hideki Asai
2010	J	`jnl`	An Optimization System with Parallel Processing for Reducing Common-Mode Current on Electronic Control Unit. IEICE Trans. Electron. Yuji Okazaki, Takanori Uno, Hideki Asai
2010	A	`conf`	Equivalent circuit modeling of multilayered power/ground planes for fast transient simulation. DATE Takayuki Watanabe, Hideki Asai
2009	J	`jnl`	CMOS Circuit Simulation Using Latency Insertion Method. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tadatoshi Sekine, Hideki Asai
2008	J	`jnl`	Acceleration of ADI-FDTD Method by Gauss-Seidel Relaxation Approach. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yuya Nakazono, Hideki Asai
2008	J	`jnl`	Fast Simulation Technique of Plane Circuits via Two-Layer CNN-Based Modeling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yuichi Tanji, Hideki Asai, Masayoshi Oda, Yoshifumi Nishio, Akio Ushida
2008	—	`conf`	Generating stable and sparse reluctance/inductance matrix under insufficient conditions. ASP-DAC Yuichi Tanji, Takayuki Watanabe, Hideki Asai
2008	J	`jnl`	Matrix Order Reduction by Nodal Analysis Formulation and Relaxation-Based Fast Simulation for Power/Ground Plane. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tadatoshi Sekine, Yuichi Tanji, Hideki Asai
2007	—	`conf`	A fast transient simulation based on Model Order Reduction and RLCG-MNA formulation. ECCTD Akira Tsuzaki, Toshio Unno, Yuichi Tanji, Hideki Asai
2007	C	`conf`	Application of Relaxation-Based Technique to ADI-FDTD Method and Its Estimation. ISCAS Yuya Nakazono, Hideki Asai
2007	J	`jnl`	Fast Transient Simulation of Power Distribution Networks Containing Dispersion Based on Parallel-Distributed Leapfrog Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takayuki Watanabe, Yuichi Tanji, Hidemasa Kubota, Hideki Asai
2006	J	`jnl`	An Enhanced Time-Domain Circuit Simulation Technique Based on LIM. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hidemasa Kubota, Yuichi Tanji, Takayuki Watanabe, Hideki Asai
2006	—	`conf`	Concurrent Design of Delta-Sigma Modulator Using Behavioral Modeling and Simulation with the Verilog-A. CICC Takafumi Yamamoto, Tsutomu Suzuki, Hideki Asai
2006	C	`conf`	Fast timing analysis of plane circuits via two-layer CNN-based modeling. ISCAS Yuichi Tanji, Hideki Asai, Masayoshi Oda, Yoshifumi Nishio, Akio Ushida
2006	A	`conf`	Large scale RLC circuit analysis using RLCG-MNA formulation. DATE Yuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai
2006	—	`conf`	Parallel-distributed time-domain circuit simulation of power distribution networks with frequency-dependent parameters. ASP-DAC Takayuki Watanabe, Yuichi Tanji, Hidemasa Kubota, Hideki Asai
2006	—	`conf`	Quasi-One-Step Gauss-Jacobi Method for Large-Scale Interconnect Analysis via RLCG-MNA Formulation. ISQED Yuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai
2006	B	`conf`	Two-staged Tabu Search for Floorplan Problem Using O-Tree Representation. IEEE Congress on Evolutionary Computation Hiroshi Ninomiya, Kimihiko Numayama, Hideki Asai
2005	B	`conf`	An efficient learning algorithm for finding multiple solutions based on fixed-point homotopy method. IJCNN Hiroshi Ninomiya, Chikahiro Tomita, Hideki Asai
2005	—	`conf`	Generalized method of the time-domain circuit simulation based on LIM with MNA formulation. CICC Hidemasa Kubota, Yuichi Tanji, Takayuki Watanabe, Hideki Asai
2005	—	`conf`	Interconnect simulation using FDTD method with variable mesh size technique. ECCTD Hirofumi Suzuki, Hidemasa Kubota, Takayuki Watanabe, Hideki Asai
2005	—	`conf`	Modeling of power distribution networks with signal lines for SPICE simulators. ISCAS (6) Takayuki Watanabe, Hideki Asai
2005	—	`conf`	Modified hybrid reduction technique for the simulation of linear/nonlinear mixed circuits. ISCAS (5) Takashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
2005	J	`jnl`	New Criteria of Selective Orthogonal Matrix Least-Squares Method for Macromodeling Multiport Networks Characterized by Sampled Data. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yuichi Tanji, Masaya Suzuki, Takayuki Watanabe, Hideki Asai
2005	—	`conf`	Optimization procedure of class E amplifiers using SPICE. ECCTD Yuichi Tanji, Hiroo Sekiya, Hideki Asai
2005	B	`conf`	Three dimensional module packing by simulated annealing. Congress on Evolutionary Computation Hirokazu Yamagishi, Hiroshi Ninomiya, Hideki Asai
2004	A*	`conf`	Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects. DAC Yuichi Tanji, Hideki Asai
2004	A	`conf`	Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits. DATE Takashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
2003	J	`jnl`	A Framework for Macromodeling and Mixed-Mode Simulation of Circuits/Interconnects and Electromagnetic Radiations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takayuki Watanabe, Hideki Asai
2003	J	`jnl`	A Low Voltage Floating Resistor Circuit Having Both Positive and Negative Resistance Values. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shashidhar Tantry, Yasuyuki Hiraku, Takao Oura, Teru Yoneyama, Hideki Asai
2003	B	`conf`	An efficient learning algorithm with second-order convergence for multilayer neural networks. IJCNN Hiroshi Ninomiya, Chikahiro Tomita, Hideki Asai
2003	—	`conf`	Analysis of PCB interconnects using electromagnetic reduction technique. ISCAS (3) Takayuki Watanabe, Hideki Asai
2003	—	`conf`	Behavioral modeling of EM devices by selective orthogonal matrix least-squares method. ASP-DAC Yuichi Tanji, Masaya Suzuki, Takayuki Watanabe, Hideki Asai
2003	J	`jnl`	Face Image Recognition by 2-Dimensional Discrete Walsh Transform and Multi-Layer Neural Network. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masahiro Yoshida, Takeshi Kamio, Hideki Asai
2002	J	`jnl`	A CMOS Floating Resistor Circuit Having Both Positive and Negative Resistance Values. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takao Oura, Teru Yoneyama, Shashidhar Tantry, Hideki Asai
2002	J	`jnl`	A Novel Application of Verilog-A to Modeling and Simulation of High-Speed Interconnects in Time/Frequency Transform-Domain. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kenichi Suzuki, Mitsuhiro Takeda, Atsushi Kamo, Hideki Asai
2002	—	`conf`	A low voltage floating resistor having positive and negative resistance values. APCCAS (1) Shashidhar Tantry, Takao Oura, Teru Yoneyama, Hideki Asai
2002	—	`conf`	A threshold voltage independent floating resistor circuit exhibiting both positive and negative resistance values. ISCAS (3) Takao Oura, Teru Yoneyama, Shashidhar Tantry, Hideki Asai
2002	J	`jnl`	An Efficient Simulator for Multiport Interconnects with Model Order Reduction Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
2002	J	`jnl`	Design and Simulation of 4Q-Multiplier Using Linear and Saturation Regions of MOSFET Complementally. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tsutomu Suzuki, Takao Oura, Teru Yoneyama, Hideki Asai
2002	—	`conf`	Noise analysis of power/ground planes on PCB by SPICE-like simulator with model order reduction technique. ISCAS (5) Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
2002	—	`conf`	Optimal placement of decoupling capacitors on PCB using Poynting vectors obtained by FDTD method. ISCAS (5) I. Hattori, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
2001	J	`jnl`	A Neuro-Based Optimization Algorithm for Tiling Problems with Rotation. Neural Process. Lett. Shinsuke Manabe, Hideki Asai
2001	—	`conf`	High-speed interconnect simulation using MIMO type of adaptive least square method. ISCAS (5) Masaya Suzuki, Hirofumi Miyashita, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
2001	—	`conf`	Simulation for the optimal placement of decoupling capacitors on printed circuit board. ISCAS (3) Atsushi Kamo, Takayuki Watanabe, Hideki Asai
2001	—	`conf`	Two floating resistor circuits and their applications to synaptic weights in analog neural networks. ISCAS (1) Shashidhar Tantry, Teru Yoneyama, Hideki Asai
2000	—	`conf`	Design Method of Limit Cycle Generator by Hysteresis Neural Networks. IJCNN (3) Teru Yoneyama, Hideki Asai, Hiroshi Ninomiya
2000	—	`conf`	Neuro-Based Human-Face Recognition with 2-Dimensional Discrete Walsh Transform. IJCNN (3) Masahiro Yoshida, Hideki Asai, Takeshi Kamio
1999	B	`conf`	A neuro-based optimization algorithm for tiling problems with rotation. IJCNN Shinsuke Manabe, Hideki Asai
1999	B	`conf`	Design method of neural networks for limit cycle generator. IJCNN Teru Yoneyama, Hiroshi Ninomiya, Hideki Asai
1999	—	`conf`	Efficient synthesis technique of time-domain models for interconnects having 3-D structures based on FDTD method. ISCAS (6) Takayuki Watanabe, Hideki Asai
1999	—	`conf`	Expanded GMC for transient analysis of transmission line networks. ISCAS (6) Atsushi Kamo, Takayuki Watanabe, Hideki Asai
1998	—	`conf`	Neural network simulator for spatiotemporal pattern analysis. ICECS Atsushi Kamo, Hiroshi Ninomiya, Teru Yoneyama, Hideki Asai
1998	—	`conf`	SPADE : analog/digital mixed signal simulator with analog hardware description language. ICECS Hiroshi Sagesaka, Hisashi Irii, Hideki Asai
1998	—	`conf`	Transient analysis for high-speed interconnect networks based on AWE and delay evaluation technique. ICECS Takayuki Watanabe, Hideki Asai
1997	—	`conf`	Application of neuro-based optimization algorithm to three dimensional cylindric puzzles. ICNN Hiroyuki Yamamoto, Takeshi Nakayama, Hiroshi Ninomiya, Hideki Asai
1996	—	`conf`	DESIRE3T+: waveform relaxation-based simulator for coupled lossy transmission lines circuits. ICECS Takayuki Watanabe, Hideki Asai
1996	—	`conf`	Design and implementation of neural network logic circuits with global convergence. ICNN Hiroshi Ninomtya, Kunitaka Egawa, Takeshi Kamio, Hideki Asai
1996	—	`conf`	Design and implementation of neuro-based discrete Walsh transform processor. ICNN Takeshi Kamio, Hiroshi Ninomiya, Hideki Asai
1996	—	`conf`	Tiling algorithm with fitting violation function for analog neural array. ICNN Hideki Asai, Takeshi Nakayama, Hiroshi Ninomiya
1995	—	`conf`	A study of Hopfield neural networks with external noises. ICNN Hideki Asai, Katsuaki Onodera, Takeshi Kamio, Hiroshi Ninomiya
1995	C	`conf`	Convergence of Hopfield Neural Network for Orthogonal Transformation. ISCAS Takeshi Kamio, Hiroshi Ninomiya, Hideki Asai
1995	—	`conf`	Neural network approach to traveling salesman problem based on hierarchical city adjacency. ICNN Hiroshi Ninomiya, Kazumichi Sato, Takeshi Nakayama, Hideki Asai
1995	C	`conf`	Orthogonalized Steepest Descent Method for Solving Nonlinear Equations. ISCAS Hiroshi Ninomiya, Hideki Asai
1994	C	`conf`	Iterated Timing Analysis with Dynamic Partitioning Technique for Bipolar Transistor Circuits. ISCAS Masaki Ishida, Koichi Hayashi, Masakatsu Nishigaki, Hideki Asai
1994	C	`conf`	Mixed Mode Circuit Simulator SPLIT2.1 using Dynamic Network Separation and Selective Trace. ISCAS Masakatsu Nishigaki, Nobuyuki Tanaka, Hideki Asai
1994	C	`conf`	Relaxation-Based Steady-State Analysis of Single- and Multi-Conductor Transmission Lines in Frequency Domain. ISCAS Takeshi Senoo, Hiroaki Makino, Hideki Asai
1994	C	`conf`	Transient Simulation of Coupled Lossy Interconnects by Window Partitioning Technique. ISCAS Vijaya Gopal Bandi, Hideki Asai
1987	J	`jnl`	Special parallel processor for lu decomposition of a large-scale sparse matrix. Syst. Comput. Jpn. Hideki Asai, Mitsuo Asai, Mamoru Tanaka
1985	J	`jnl`	Network analysis by hierarchical tearing method. Syst. Comput. Jpn. Hideki Asai, Shinsaku Mori