Hideki Ando

35 papers A* 7A 2C 6Journal 17Unranked 3
YearRankTypeTitle / Venue / Authors
2024 A* conf
Localizing the Tag Comparisons in the Wakeup Logic to Reduce Energy Consumption of the Issue Queue.
MICRO
Kenichiro Mori, Sota Kosugi, Hiroto Yoshida, Hajime Shimada, Hideki Ando
2022 J jnl
Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag Comparison.
IEICE Trans. Inf. Syst.
Yasutaka Matsuda, Ryota Shioya, Hideki Ando
2022 C conf
Segmenting Age Matrices to Improve Instruction Scheduling without Increasing Delay and Area.
ICCD
Hideki Ando
2019 J jnl
Improving the Instruction Fetch Throughput with Dynamically Configuring the Fetch Pipeline.
IEEE Comput. Archit. Lett.
Reoma Matsuo, Ryota Shioya, Hideki Ando
2019 A* conf
SWQUE: A Mode Switching Issue Queue with Priority-Correcting Circular Queue.
MICRO
Hideki Ando
2018 — conf
A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode.
ARCS
Yasumasa Chidai, Kojiro Izuoka, Ryota Shioya, Masahiro Goshima, Hideki Ando
2018 J jnl
Performance Improvement Techniques in Tightly Coupled Multicore Architectures for Single-Thread Applications.
J. Inf. Process.
Keita Doi, Ryota Shioya, Hideki Ando
2018 A* conf
Performance Improvement by Prioritizing the Issue of the Instructions in Unconfident Branch Slices.
MICRO
Hideki Ando
2018 C conf
Rearranging Random Issue Queue with High IPC and Short Delay.
ICCD
Shinji Sakai, Taishi Suenaga, Ryota Shioya, Hideki Ando
2016 J jnl
FXA: Executing Instructions in Front-End for Energy Efficiency.
IEICE Trans. Inf. Syst.
Ryota Shioya, Ryo Takami, Masahiro Goshima, Hideki Ando
2016 J jnl
Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency.
IEICE Trans. Inf. Syst.
Ryota Shioya, Hideki Ando
2016 J jnl
Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control.
IEICE Trans. Inf. Syst.
Hideki Ando, Ryota Shioya
2014 A* conf
A Front-End Execution Architecture for High Energy Efficiency.
MICRO
Ryota Shioya, Masahiro Goshima, Hideki Ando
2014 C conf
Energy efficiency improvement of renamed trace cache through the reduction of dependent path length.
ICCD
Ryota Shioya, Hideki Ando
2014 J jnl
MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism.
IEICE Trans. Inf. Syst.
Yuya Kora, Kyohei Yamaguchi, Hideki Ando
2013 A* conf
MLP-aware dynamic instruction window resizing for adaptively exploiting both ILP and MLP.
MICRO
Yuya Kora, Kyohei Yamaguchi, Hideki Ando
2012 J jnl
Delay Evaluation of Issue Queue in Superscalar Processors with Banking Tag RAM and Correct Critical Path Identification.
IEICE Trans. Inf. Syst.
Kyohei Yamaguchi, Yuya Kora, Hideki Ando
2011 C conf
Evaluation of issue queue delay: Banking tag RAM and identifying correct critical path.
ICCD
Kyohei Yamaguchi, Yuya Kora, Hideki Ando
2010 J jnl
Register File Size Reduction through Instruction Pre-Execution Incorporating Value Prediction.
IEICE Trans. Inf. Syst.
Yusuke Tanaka, Hideki Ando
2009 J jnl
Energy-Efficient Pre-Execution Techniques in Two-Step Physical Register Deallocation.
IEICE Trans. Inf. Syst.
Kazunaga Hyodo, Kengo Iwamoto, Hideki Ando
2009 C conf
Reducing register file size through instruction pre-execution enhanced by value prediction.
ICCD
Yusuke Tanaka, Hideki Ando
2008 J jnl
Two-Step Physical Register Deallocation for Data Prefetching and Address Pre-Calculation.
Inf. Media Technol.
Akihiro Yamamoto, Yusuke Tanaka, Hideki Ando, Toshio Shimada
2007 — conf
Data prefetching and address pre-calculation through instruction pre-execution with two-step physical register deallocation.
MEDEA@PACT
Akihiro Yamamoto, Yusuke Tanaka, Hideki Ando, Toshio Shimada
2006 J jnl
Limits of Thread-Level Parallelism in Non-numerical Programs.
Inf. Media Technol.
Akio Nakajima, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada
2003 A conf
Pipeline stage unification: a low-energy consumption technique for future mobile processors.
ISLPED
Hajime Shimada, Hideki Ando, Toshio Shimada
2002 A conf
A preactivating mechanism for a VT-CMOS cache using address prediction.
ISLPED
Ryo Fujioka, Kiyokazu Katayama, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada
1999 — conf
An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism.
EUROMICRO
Ryotaro Kobayashi, Yukihiro Ogawa, Hideki Ando, Toshio Shimada, Mitsuaki Iwata
1999 J jnl
Distributed memoryless point convergence algorithm for mobile robots with limited visibility.
IEEE Trans. Robotics Autom.
Hideki Ando, Yoshinobu Oasa, Ichiro Suzuki, Masafumi Yamashita
1998 J jnl
Software pipelining with path selection.
Syst. Comput. Jpn.
Chikako Nakanishi, Hideki Ando, Tetsuya Hara, Masao Nakaya
1996 A* conf
Performance Comparison of ILP Machines with Cycle Time Evaluation.
ISCA
Tetsuya Hara, Hideki Ando, Chikako Nakanishi, Masao Nakaya
1995 J jnl
Code scheduling on a superscalar processor: SARCH.
Syst. Comput. Jpn.
Chikako Nakanishi, Hideki Ando, Hirohisa Machida, Masao Nakaya
1995 A* conf
Unconstrained Speculative Execution with Predicated State Buffering.
ISCA
Hideki Ando, Chikako Nakanishi, Tetsuya Hara, Masao Nakaya
1993 J jnl
A VLSI chip set for a large-scale parallel inference machine: PIM/m.
IEEE J. Solid State Circuits
Hirohisa Machida, Hideki Ando, Kenichi Yasuda, Kiyohiro Furutani, Yukihiro Yamashita, Hiroshi Nakashima, Yasutaka Takeda, Katsuto Nakajima, Masayoshi Sakao, Masao Nakaya
1993 C conf
Speculative Execution and Reducing Branch Penalty in a Parallel Issue Machine.
ICCD
Hideki Ando, Chikako Nakanishi, Hirohisa Machida, Tetsuya Hara, Satoru Kishida, Masao Nakaya
1988 J jnl
A DSP line equalizer VLSI for TCM digital subscriber-line transmission.
IEEE J. Solid State Circuits
Hideki Ando, Masao Nakaya, Hiroki Hona, Ihuo Iizuka, Yasutaka Horiba