Hidekazu Terai

27 papers A* 7B 1C 4Misc 4Journal 5Unranked 6
YearRankTypeTitle / Venue / Authors
2009 — conf
Car Navigation System Based on Hybrid Genetic Algorithm.
CSIE (5)
Masaya Yoshikawa, Hidekazu Terai
2009 — conf
Dedicated Hardware for Ant Colony Optimization Using Distributed Memory.
ITNG
Masaya Yoshikawa, Hidekazu Terai
2009 — conf
OX Hardware Engine for High Speed Character Inheritance.
GEM
Masaya Yoshikawa, Hidekazu Terai
2008 — conf
Hardware Architecture of Pheromone-Balance Aware Ant Colony Optimization.
GEM
Masaya Yoshikawa, Hidekazu Terai
2008 J jnl
Hybrid Architecture of Genetic Algorithm and Simulated Annealing.
Eng. Lett.
Masaya Yoshikawa, Hironori Yamauchi, Hidekazu Terai
2008 Misc conf
Route selection algorithm based on integer operation Ant Colony Optimization.
IRI
Masaya Yoshikawa, Hidekazu Terai
2007 Misc conf
Architecture for high-speed Ant Colony Optimization.
IRI
Masaya Yoshikawa, Hidekazu Terai
2007 J jnl
Hierarchical Parallel Placement Using a Genetic Algorithm for Realizing Low Power Consumption.
J. Adv. Comput. Intell. Intell. Informatics
Masaya Yoshikawa, Hidekazu Terai
2007 J jnl
The new DFM approach based on a genetic algorithm.
Artif. Life Robotics
Masaya Yoshikawa, Hidekazu Terai
2006 C conf
Apriori, Association Rules, Data Mining, Frequent Itemsets Mining (FIM), Parallel Computing.
SERA
Masaya Yoshikawa, Hidekazu Terai
2006 C conf
Co-evolutionary robotics using two kinds of neural networks.
CAINE
Masaya Yoshikawa, Hidekazu Terai
2006 J jnl
Dedicated Floorplanning Engine Architecture Based on Genetic Algorithm and Evaluation.
J. Adv. Comput. Intell. Intell. Informatics
Masaya Yoshikawa, Hidekazu Terai
2006 Misc conf
Immune Algorithm Processor.
CATA
Masaya Yoshikawa, Masahiro Fukui, Hidekazu Terai
2005 C conf
A Hierarchical Parallel Placement Technique based on Genetic Algorithm.
ISDA
Masaya Yoshikawa, Hidekazu Terai
2005 C conf
Asynchronous Parallel Genetic Algorithm for Congestion-Driven Placement Technique.
SERA
Masaya Yoshikawa, Hidekazu Terai
2005 — conf
Hybrid genetic algorithm engine for high-speed floorplanning.
ECCTD
Masaya Yoshikawa, Hidekazu Terai
2005 B conf
Performance driven placement technique based on collaboration of software and hardware.
Congress on Evolutionary Computation
Masaya Yoshikawa, Hidekazu Terai
2004 — conf
VLSI processor architecture for real-time GA processing and PE-VLSI design.
ISCAS (3)
Tetsuya Imai, Masaya Yoshikawa, Hidekazu Terai, Hironori Yamauchi
2002 Misc conf
Scalable GA processor architecture and its implementation of processor-element.
ICASSP
Tetsuya Imai, Masaya Yoshikawa, Hidekazu Terai, Hironori Yamauchi
1994 A* conf
Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC Processor HARP-1.
DAC
Hidekazu Terai, Kazutoshi Gemma, Yohsuke Nagao, Yasuo Satoh, Yasuhiro Ohno
1991 A* conf
Basic Concepts of Timing-oriented Design Automation for High-performance Mainframe Computers.
DAC
Hidekazu Terai, Fumio Goto, Katsuro Wakai, Tokinori Kozawa, Mitsugu Edagawa, Satoshi Hososaka, Masahiro Hashimoto
1988 A* conf
Automatic Layout Procedures for Serial Routing Devices.
DAC
Yasushi Ogawa, Hidekazu Terai, Tokinori Kozawa
1986 A* conf
Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs.
DAC
Yasushi Ogawa, Tatsuki Ishii, Yoichi Shiraishi, Hidekazu Terai, Tokinori Kozawa, Kyoji Yuyama, Kyoji Chiba
1985 A* conf
A routing procedure for mixed array of custom macros and standard cells.
DAC
Hidekazu Terai, Michiyoshi Hayase, Tokinori Kozawa
1985 J jnl
Research in Design Automation for VLSI Layout.
IEEE Des. Test
Tokinori Kozawa, Hidekazu Terai
1984 A* conf
Combine and top down block placement algorithm for hierarchical logic VLSI layout.
DAC
Tokinori Kozawa, Chihei Miura, Hidekazu Terai
1983 A* conf
Automatic placement algorithms for high packing density V L S I.
DAC
Tokinori Kozawa, Hidekazu Terai, Tatsuki Ishii, Michiyoshi Hayase, Chihei Miura, Yasushi Ogawa, Kuniaki Kishida, Norio Yamada, Yasuhiro Ohno