Hidehiro Toyoda

14 papers Journal 6Unranked 8
YearRankTypeTitle / Venue / Authors
2015 — conf
Adaptive FEC control in downstream collaborating with traffic control in OLT for WDM/TDM-PON.
ECOC
Jun Sugawa, Koji Wakayama, Hidehiro Toyoda
2015 — conf
Simultaneous multi-ONU wavelength switching method for coexistence of different λ-tuning times in WDM/TDM-PON.
OFC
Jun Sugawa, Koji Wakayama, Hidehiro Toyoda
2014 J jnl
A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion.
IEEE J. Solid State Circuits
Takashi Takemoto, Hiroki Yamashita, Fumio Yuki, Noboru Masuda, Hidehiro Toyoda, Norio Chujo, Yong Lee, Shinji Tsuji, Shinji Nishimura
2014 — conf
Wavelength switching method combined with downstream queue monitoring per ONU for λ-tunable WDM/TDM-PON.
ECOC
Jun Sugawa, Toshiyuki Odaka, Hidehiro Toyoda
2012 — conf
A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS.
VLSIC
Takashi Takemoto, Hiroki Yamashita, Takehito Kamimura, Fumio Yuki, Noboru Masuda, Hidehiro Toyoda, Norio Chujo, Kenji Kogo, Yong Lee, Shinji Tsuji, Shinji Nishimura
2012 J jnl
A Novel 400-Gb/s (100-Gb/s×4) Physical-Layer Architecture Using Low-Power Technology.
IEICE Trans. Commun.
Masashi Kono, Akihiro Kambe, Hidehiro Toyoda, Shinji Nishimura
2011 — conf
10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link.
ISSCC
Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Akihiro Kambe, Tatsuya Saito, Shinji Nishimura
2011 J jnl
A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link.
IEEE J. Solid State Circuits
Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Masashi Kono, Akihiro Kambe, Seiichi Umai, Tatsuya Saito, Shinji Nishimura
2011 — conf
A 400-Gb/s and Low-Power Physical-Layer Architecture for Next-Generation Ethernet.
ICC
Masashi Kono, Akihiro Kambe, Hidehiro Toyoda
2010 J jnl
100GbE PHY and MAC layer implementations.
IEEE Commun. Mag.
Hidehiro Toyoda, Goichi Ono, Shinji Nishimura
2008 — conf
A 100 Gb/s and High-Reliable Physical-Layer Architecture for VSR and Backplane Ethernet.
ICC
Hidehiro Toyoda, Michitaka Okuno, Shinji Nishimura, Matsuaki Terada
2007 J jnl
A 100-Gb/s-Physical-Layer Architecture for Higher-Speed Ethernet for VSR and Backplane Applications.
IEICE Trans. Electron.
Hidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Matsuaki Terada
2006 J jnl
100-Gb/s Physical-Layer Architecture for Next-Generation Ethernet.
IEICE Trans. Commun.
Hidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Kouji Fukuda, Kouji Nakahara, Hiroaki Nishi
2005 — conf
A 100-Gb-Ethernet subsystem for next-generation metro-area network.
ICC
Hidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Ryouji Yamaoka, Hiroaki Nishi