Hidehiro Takata

25 papers A* 1A 2C 2Journal 16Unranked 4
YearRankTypeTitle / Venue / Authors
2015 J jnl
An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference.
IEEE Trans. Very Large Scale Integr. Syst.
Takuya Sawada, Kumpei Yoshikawa, Hidehiro Takata, Koji Nii, Makoto Nagata
2012 J jnl
Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation.
IEICE Trans. Electron.
Takuya Sawada, Taku Toshikawa, Kumpei Yoshikawa, Hidehiro Takata, Koji Nii, Makoto Nagata
2012 J jnl
Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature.
IEEE Trans. Circuits Syst. II Express Briefs
Ryo Takahashi, Hidehiro Takata, Tadashi Yasufuku, Hiroshi Fuketa, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2012 J jnl
On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction.
IEICE Trans. Electron.
Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
2011 C conf
Decoupling capacitance boosting for on-chip resonant supply noise reduction.
DDECS
Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
2011 J jnl
On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch.
IEICE Trans. Electron.
Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
2011 — conf
On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure.
ESSCIRC
Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
2010 A conf
Misleading energy and performance claims in sub/near threshold digital systems.
ICCAD
Yu Pu, Xin Zhang, Jim Huang, Atsushi Muramatsu, Masahiro Nomura, Koji Hirairi, Hidehiro Takata, Taro Sakurabayashi, Shinji Miyano, Makoto Takamiya, Takayasu Sakurai
2010 J jnl
Phase-adjustable error detection flip-flops with 2-stage hold-driven optimization, slack-based grouping scheme and slack distribution control for dynamic voltage scaling.
ACM Trans. Design Autom. Electr. Syst.
Masanori Kurimoto, Hiroaki Suzuki, Rei Akiyama, Tadao Yamanaka, Haruyuki Ohkuma, Hidehiro Takata, Hirofumi Shinohara
2009 J jnl
Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations.
IEICE Trans. Electron.
Mitsuya Fukazawa, Masanori Kurimoto, Rei Akiyama, Hidehiro Takata, Makoto Nagata
2008 A* conf
Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling.
DAC
Masanori Kurimoto, Hiroaki Suzuki, Rei Akiyama, Tadao Yamanaka, Haruyuki Ohkuma, Hidehiro Takata, Hirofumi Shinohara
2008 A conf
Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology.
ISLPED
Hiroaki Suzuki, Masanori Kurimoto, Tadao Yamanaka, Hidehiro Takata, Hiroshi Makino, Hirofumi Shinohara
2007 J jnl
Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS.
IEICE Trans. Electron.
Kazutami Arimoto, Toshihiro Hattori, Hidehiro Takata, Atsushi Hasegawa, Toru Shimizu
2007 — conf
Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCs.
ISSCC
Mitsuya Fukazawa, Tetsuro Matsuno, Toshifumi Uemura, Rei Akiyama, Tetsuya Kagemoto, Hiroshi Makino, Hidehiro Takata, Makoto Nagata
2005 — conf
A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure.
ISCAS (1)
Niichi Itoh, Yasumasa Tsukamoto, Takeshi Shibagaki, Koji Nii, Hidehiro Takata, Hiroshi Makino
2002 J jnl
A 99-mm
IEEE J. Solid State Circuits
Satoshi Kumaki, Hidehiro Takata, Yoshihide Ajioka, Tsukasa Ooishi, Kazuya Ishihara, Atsuo Hanami, Takaharu Tsuji, Tetsuya Watanabe, Chikayoshi Morishima, Tomoaki Yoshizawa, Hidenori Sato, Shin-ichi Hattori, Atsushi Koshio, Kazuhiro Tsukamoto, Tetsuya Matsumura
2001 — conf
A 99-mm
CICC
Satoshi Kumaki, Hidehiro Takata, Yoshihide Ajioka, Tsukasa Ooishi, Kazuya Ishihara, Atsuo Hanami, Takaharu Tsuji, Yusuke Kanehira, Tetsuya Watanabe, Chikayoshi Morishima, Tomoaki Yoshizawa, Hidenori Sato, Shin-ichi Hattori, Atsushi Koshio, Kazuhiro Tsukamoto, Tetsuva Matsumura
1999 J jnl
A real-time digital VCR encode/decode and MPEG-2 decode LSI implemented on a dual-issue RISC processor.
IEEE J. Solid State Circuits
Atsushi Mohri, Akira Yamada, Y. Yoshida, Hisakazu Sato, Hidehiro Takata, K. Nakakimura, M. Hashizume, Y. Shimotsuma, K. Tsuchihashi
1999 J jnl
The D30V/MPEG multimedia processor.
IEEE Micro
Hidehiro Takata, Tetsuya Watanabe, Tetsuo Nakajima, Takashi Takagaki, Hisakazu Sato, Atsushi Mohri, Akira Yamada, Toshiki Kanamoto, Yoshio Matsuda, Shuhei Iwade, Yasutaka Horiba
1991 C conf
A Data-Driven Architecture for Distributed Parallel Processing.
ICCD
Toshiyuki Tamura, Shinji Komori, Fumiyasu Asai, Hirono Tsubota, Hisakazu Sato, Hidehiro Takata, Yoshihiro Seguchi, Takeshi Tokuda, Hiroaki Terada
1990 J jnl
A 100-mega-access per second matching memory for a data-driven microprocessor.
IEEE J. Solid State Circuits
Hidehiro Takata, Shinji Komori, Toshiyuki Tamura, Fumiyasu Asai, Hisakazu Sato, Takio Ohno, Takeshi Tokuda, Hiroki Nishikawa, Hirofumi Terada
1990 J jnl
Design of 4-kbit*4-layer optically coupled three-dimensional common memory for parallel processor system.
IEEE J. Solid State Circuits
Mitsumasa Koyanagi, Hidehiro Takata, Hiroki Mori, Junichiro Iba
1989 J jnl
A 40-MFLOPS 32-bit floating-point processor with elastic pipeline scheme.
IEEE J. Solid State Circuits
Shinji Komori, Hidehiro Takata, Todhixuki Tamura, Fumixsdu Asai, Takio Ohno, Osamu Tomisawa, Tetsuo Yamasaki, Kenji Shima, Hiroaki Nishikawa, Hiroaki Terada
1989 J jnl
VLSI implementation of a variable-length pipeline scheme for data-driven processors.
IEEE J. Solid State Circuits
Tetsuo Yamasaki, Kenji Shima, Shinji Komori, Hidehiro Takata, Toshiyuki Tamura, Fumiyasu Asai, Takio Ohno, Osamu Tomisawa, Hiroaki Terada
1988 J jnl
An elastic pipeline mechanism by self-timed circuits.
IEEE J. Solid State Circuits
Shinji Komori, Hidehiro Takata, Toshiyuki Tamura, Fumiyasu Asai, Takio Ohno, Osamu Tomisawa, Tetsuo Yamasaki, Kenji Shima, Katsuhiko Asada, Hiroaki Terada