Hideharu Amano

531 papers A* 8A 15B 64C 22Misc 21Journal 128Unranked 266
YearRankTypeTitle / Venue / Authors
2025 — conf
A High Level Synthesis Tool for Multiple FPGAs.
MCSoC
Kazutoshi Wakabayashi, Wataru Takahashi, Hideharu Amano
2025 J jnl
Agile-X: A Structured-ASIC Created With a Mask-Less Lithography System Enabling Low-Cost and Agile Chip Fabrication.
IEEE Trans. Very Large Scale Integr. Syst.
Atsutake Kosuge, Hirofumi Sumi, Naonobu Shimamoto, Yukinori Ochiai, Yurie Inoue, Hideharu Amano, Tohru Mogami, Yoshio Mita, Makoto Ikeda, Tadahiro Kuroda
2025 J jnl
An Efficient GPU-based Implementation for Noise Robust Sound Source Localization.
CoRR
Zirui Lin, Masayuki Takigahira, Naoya Terakado, Haris Gulzar, Monikka Roslianna Busto, Takeharu Eda, Katsutoshi Itoyama, Kazuhiro Nakadai, Hideharu Amano
2025 C conf
An SoC Design and Fabrication Hands-On Educational Course within One Week Using Structured ASIC.
ISCAS
Hideharu Amano, Atsutake Kosuge, Hirofumi Sumi, Naonobu Shimamoto, Yukinori Ochiai, Yurie Inoue, Tohru Mogami, Yoshio Mita, Makoto Ikeda
2025 — conf
Can the Agile-Chip Platform Carve Out a Niche Between ASICs and FPGAs?
COOL CHIPS
Hideharu Amano, Atsutake Kosuge, Hirofumi Sumi, Naonobu Shimamoto, Yukinori Ochiai, Yurie Inoue, Tohru Mogami, Yoshio Mita, Makoto Ikeda
2025 — conf
FP-FBEMS: FPGA-Based Optimization of Forward/Backward EMS Decoding for CV-QKD.
MCSoC
Kaijie Wei, Devanshu Garg, Ryutaro Nagai, Takao Tomono, Hideharu Amano
2025 — conf
FPT-EMS: An FPGA Implementation Using NB-LDPC Code for Continuous-Variable Quantum Key Distribution.
HEART
Kaijie Wei, Devanshu Garg, Ryutaro Nagai, Takao Tomono, Hideharu Amano
2025 J jnl
Qu-Trefoil: Large-Scale Quantum Circuit Simulator Working on FPGA With SATA Storages.
IEEE Trans. Computers
Kaijie Wei, Hideharu Amano, Ryohei Niwase, Yoshiki Yamaguchi, Takefumi Miyoshi
2024 — conf
A data compressor for FPGA-based state vector quantum simulators.
HEART
Kaijie Wei, Hideharu Amano, Ryohei Niwase, Yoshiki Yamaguchi
2024 J jnl
Applying Run-Length Compression to the Configuration Data of SLM Fine-Grained Reconfigurable Logic.
IEICE Trans. Inf. Syst.
Souhei Takagi, Takuya Kojima, Hideharu Amano, Morihiro Kuga, Masahiro Iida
2024 — conf
FPGA-based Low Power Acceleration of HARK Sound Source Localization.
COOL CHIPS
Zirui Lin, Katsutoshi Itoyama, Kazuhiro Nakadai, Hideharu Amano
2024 J jnl
Optimized Two-Step Store Control for MTJ-Based Nonvolatile Flip-Flops to Minimize Store Energy Under Process and Temperature Variations.
IEEE Trans. Very Large Scale Integr. Syst.
Kimiyoshi Usami, Daiki Yokoyama, Aika Kamei, Hideharu Amano, Kenta Suzuki, Keizo Hiraga, Kazuhiro Bessho
2024 J jnl
Power Optimized Design Framework for FPGA Clusters.
IPSJ Trans. Syst. LSI Des. Methodol.
Kensuke Iizuka, Kohei Ito, Ryota Yasudo, Hideharu Amano
2024 C conf
Power analysis of an optical interconnected FPGA cluster for roadside units.
ICCE
Hideharu Amano, Kensuke Iizuka
2024 — conf
SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks.
COOL CHIPS
Takuya Kojima, Yosuke Yanai, Hayate Okuhara, Hideharu Amano, Morihiro Kuga, Masahiro Iida
2024 — conf
The Case for Coherence Directories in Memory Cubes.
MCSoC
Yuki Kameyama, Naoya Niwa, Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2023 J jnl
A Compression Router for Low-Latency Network-on-Chip.
IEICE Trans. Inf. Syst.
Naoya Niwa, Yoshiya Shikama, Hideharu Amano, Michihiro Koibuchi
2023 J jnl
A Multi-FPGA Implementation of FM-Index Based Genomic Pattern Search.
IEICE Trans. Inf. Syst.
M. M. Imdad Ullah, Akram Ben Ahmed, Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano
2023 J jnl
A Scalable Body Bias Optimization Method Toward Low-Power CGRAs.
IEEE Micro
Takuya Kojima, Hayate Okuhara, Masaaki Kondo, Hideharu Amano
2023 J jnl
A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops.
IEEE Trans. Very Large Scale Integr. Syst.
Aika Kamei, Hideharu Amano, Takuya Kojima, Daiki Yokoyama, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho
2023 — conf
A cost/power efficient storage system with directly connected FPGA and SATA disks.
MCSoC
Ryohei Niwase, Hikaru Harasawa, Yoshiki Yamaguchi, Kaijie Wei, Hideharu Amano
2023 — conf
A state vector quantum simulator working on FPGAs with extensible SATA storage.
ICFPT
Kaijie Wei, Ryohei Niwase, Hideharu Amano, Yoshiki Yamaguchi, Takefumi Miyoshi
2023 — conf
Board Allocation Algorithm for the Resource Management System of FiC.
MCSoC
Takumi Inage, Kensuke Iizuka, Hideharu Amano
2023 J jnl
Designing low-diameter interconnection networks with multi-ported host-switch graphs.
Concurr. Comput. Pract. Exp.
Ryota Yasudo, Koji Nakano, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano
2023 — conf
Efficient FPGA Implementation of Amoeba-inspired SAT Solver with Feedback and Bounceback Control: Harnessing Variable-Level Parallelism for Large-Scale Problem Solving in Edge Computing.
HEART
Hideharu Amano
2023 — conf
Enormous-Scale Quantum State Vector Calculation with FPGA-accelerated SATA storages.
ICFPT
Ryohei Niwase, Hikaru Harasawa, Yoshiki Yamaguchi, Kaijie Wei, Hideharu Amano, Takefumi Miyoshi
2023 — conf
FPGA based Power-Efficient Edge Server to Accelerate Speech Interface for Socially Assistive Robotics.
SII
Haris Gulzar, Muhammad Shakeel, Katsutoshi Itoyama, Kazuhiro Nakadai, Kenji Nishida, Hideharu Amano, Takeharu Eda
2023 — conf
Low power implementation of Geometric High-order Decorrelation-based Source Separation on an FPGA board.
COOL CHIPS
Ziquan Qin, Kaijie Wei, Hideharu Amano, Kazuhiro Nakadai
2023 J jnl
Parallel Implementation of CNN on Multi-FPGA Cluster.
IEICE Trans. Inf. Syst.
Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano
2023 — conf
Parallel Implementation of Vision Transformer on a Multi-FPGA Cluster.
candar
Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano
2023 J jnl
Power Analysis and Power Modeling of Directly-Connected FPGA Clusters.
IEICE Trans. Inf. Syst.
Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano
2023 J jnl
RT-libSGM: FPGA-Oriented Real-Time Stereo Matching System with High Scalability.
IEICE Trans. Inf. Syst.
Kaijie Wei, Yuki Kuno, Masatoshi Arai, Hideharu Amano
2022 C conf
A Hardware Trojan Exploiting Coherence Protocol on NoCs.
PDCAT
Yoshiya Shikama, Michihiro Koibuchi, Hideharu Amano
2022 — conf
A Message Passing Interface Library for High-Level Synthesis on Multi-FPGA Systems.
MCSoC
Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano
2022 J jnl
A traffic-aware memory-cube network using bypassing.
Microprocess. Microsystems
Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi
2022 — conf
An FPGA off-loading of HARK sound source localization.
CANDARW
Zhongyang Hou, Kaijie Wei, Hideharu Amano, Kazuhiro Nakadai
2022 — conf
An Implementation of a 3D Image Filter for Motion Vector Generation on an FPGA Board.
CANDAR
Yuchen Chen, Kaijie Wei, Hiroaki Nishi, Hideharu Amano
2022 C conf
An efficient compilation of coarse-grained reconfigurable architectures utilizing pre-optimized sub-graph mappings.
PDP
Ayaka Ohwada, Takuya Kojima, Hideharu Amano
2022 — conf
Body Bias Control on a CGRA based on Convex Optimization.
COOL CHIPS
Takuya Kojima, Hayate Okuhara, Masaaki Kondo, Hideharu Amano
2022 J jnl
Boosting the Performance of Interconnection Networks by Selective Data Compression.
IEICE Trans. Inf. Syst.
Naoya Niwa, Hideharu Amano, Michihiro Koibuchi
2022 — conf
Distance Aware Compression for Low Latency High Bandwidth Interconnection Network.
MCSoC
Zhou Yuqing, Naoya Niwa, Hideharu Amano
2022 — conf
Dynamic Routing Reconfiguration for Low-Latency and Deadlock-Free Interconnection Networks.
CANDAR
Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2022 B conf
FPL Demo: An FPGA-IP Prototype Chip for MEC devices.
FPL
Morihiro Kuga, Masahiro Iida, Hideharu Amano
2022 J jnl
Mapping-Aware Kernel Partitioning Method for CGRAs Assisted by Deep Learning.
IEEE Trans. Parallel Distributed Syst.
Takuya Kojima, Ayaka Ohwada, Hideharu Amano
2022 — conf
Multi-board FPGA Implementation to Solve the Satisfiability Problem for Multi-Agent Path Finding in Smart Factory.
CANDARW
Pengyu Huang, Kaijie Wei, Hideharu Amano, Kaori Ohkoda, Masashi Aono
2022 — conf
Optimal switching time to minimize store energy in MTJ-based flip-flops under process and temperature variations.
NorCAS
Kimiyoshi Usami, Daiki Yokoyama, Aika Kamei, Hideharu Amano
2022 B conf
Optimizing Application Mapping for Multi-FPGA Systems with Multi-ejection STDM Switches.
FPL
Kohei Ito, Ryota Yasudo, Hideharu Amano
2022 — conf
Power Analysis of Directly-connected FPGA Clusters.
COOL CHIPS
Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano
2022 — conf
RT-libSGM: An Implementation of a Real-time Stereo Matching System on FPGA.
HEART
Kaijie Wei, Yuki Kuno, Masatoshi Arai, Hideharu Amano
2022 — conf
Reconfiguration Cost for Reconfigurable Computing Architectures.
SNPD-Summer
Shigeyuki Takano, Hideharu Amano
2022 J jnl
The Implementation of a Hybrid Router and Dynamic Switching Algorithm on a Multi-FPGA System.
IEICE Trans. Inf. Syst.
Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano
2022 — conf
Toward a training of CNNs on a multi-FPGA system.
CANDARW
Aoi Hiruma, Kensuke Iizuka, Hideharu Amano
2022 J jnl
Weighted Least Square Filter for Improving the Quality of Depth Map on FPGA.
Int. J. Netw. Comput.
Renzhi Mao, Kaijie Wei, Hideharu Amano, Yuki Kuno, Masatoshi Arai
2021 C conf
A Case for Low-Latency Network-on-Chip using Compression Routers.
PDP
Naoya Niwa, Yoshiya Shikama, Hideharu Amano, Michihiro Koibuchi
2021 J jnl
A Multi-Tenant Resource Management System for Multi-FPGA Systems.
IEICE Trans. Inf. Syst.
Miho Yamakura, Ryousei Takano, Akram Ben Ahmed, Midori Sugaya, Hideharu Amano
2021 — conf
A programming environment for multi-FPGA systems based on CyberWorkBench: an integrated design tool.
HEART
Hiroaki Suzuki, Wataru Takahashi, Kazutoshi Wakabayashi, Hideharu Amano
2021 J jnl
An FPGA-Based Optimizer Design for Distributed Deep Learning with Multiple GPUs.
IEICE Trans. Inf. Syst.
Tomoya Itsubo, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani
2021 J jnl
An implementation methodology for Neural Network on a Low-end FPGA Board.
Int. J. Netw. Comput.
Kaijie Wei, Koki Honda, Hideharu Amano
2021 — conf
Analysis of Resistance Distribution and Voltage Drop in Chips with Inductive Coupling Wireless Communication Interface.
CANDAR (Workshops)
Hideto Kayashima, Hideharu Amano
2021 J jnl
Analytical Performance Estimation for Large-Scale Reconfigurable Dataflow Platforms.
ACM Trans. Reconfigurable Technol. Syst.
Ryota Yasudo, José Gabriel de Figueiredo Coutinho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, Tobias Becker, Ce Guo
2021 J jnl
CLAHE Implementation and Evaluation on a Low-End FPGA Board by High-Level Synthesis.
IEICE Trans. Inf. Syst.
Koki Honda, Kaijie Wei, Masatoshi Arai, Hideharu Amano
2021 — conf
Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops.
MCSoC
Aika Kamei, Takuya Kojima, Hideharu Amano, Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho
2021 — conf
GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph.
ACIT
Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2021 — conf
Hybrid Network of Packet Switching and STDM in a Multi-FPGA System.
COOL CHIPS
Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano
2021 — conf
Implementing VTA, a tensor accelerator on Flow-in-Cloud.
ACIT
Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano
2021 J jnl
Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System.
IEICE Trans. Inf. Syst.
Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano
2021 — conf
Low-Latency High-Bandwidth Interconnection Networks by Selective Packet Compression.
CANDAR
Naoya Niwa, Hideharu Amano, Michihiro Koibuchi
2021 C conf
Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths.
PDP
Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi
2021 — conf
M-KUBOS/PYNQ Cluster for multi-access edge computing.
CANDAR
Takumi Inage, Kazuei Hironaka, Kensuke Iizuka, Kohei Ito, Yasuyu Fukushima, Mitaro Namiki, Hideharu Amano
2021 — conf
Parallel Implementation of CNN on Multi-FPGA Cluster.
MCSoC
Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano
2021 — conf
Power Consumption Reduction Method and Edge Offload Server for Multiple Robots.
EDGE
Sannomiya Natsuho, Takeshi Ohkawa, Hideharu Amano, Midori Sugaya
2021 J jnl
Recovering Faulty Non-Volatile Flip Flops for Coarse-Grained Reconfigurable Architectures.
IEICE Trans. Electron.
Takeharu Ikezoe, Takuya Kojima, Hideharu Amano
2021 J jnl
Remote Dynamic Reconfiguration of a Multi-FPGA System FiC (Flow-in-Cloud).
IEICE Trans. Inf. Syst.
Kazuei Hironaka, Kensuke Iizuka, Miho Yamakura, Akram Ben Ahmed, Hideharu Amano
2021 — conf
Resource-saving FPGA Implementation of the Satisfiability Problem Solver: AmoebaSATslim.
FPT
Ying Jie Yan, Hideharu Amano, Masashi Aono, Kaori Ohkoda, Shingo Fukuda, Kenta Saito, Seiya Kasai
2021 — conf
TCI Tester: Tester for Through Chip Interface.
ASP-DAC
Hideto Kayashima, Hideharu Amano
2021 — conf
Weight Least Square Filter for Improving the Quality of Depth Map on FPGA.
CANDAR (Workshops)
Renzhi Mao, Kaijie Wei, Hideharu Amano, Yuki Kuno, Masatoshi Arai
2020 J jnl
A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks.
IEICE Trans. Inf. Syst.
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2020 — conf
A Method of Partitioning Convolutional Layer to Multiple FPGAs.
ISOCC
Kensuke Iizuka, Kohei Ito, Kazuei Hironaka, Hideharu Amano
2020 C conf
Accelerating Deep Learning using Multiple GPUs and FPGA-Based 10GbE Switch.
PDP
Tomoya Itsubo, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani
2020 — conf
An implementation methodology for Neural Network on a Low-end FPGA Board.
CANDAR
Kaijie Wei, Koki Honda, Hideharu Amano
2020 — conf
Automated Integration of High-Level Synthesis FPGA Modules with ROS2 Systems.
FPT
Daniel Pinheiro Leal, Midori Sugaya, Hideharu Amano, Takeshi Ohkawa
2020 — conf
CLAHE implementation on a low-end FPGA board by high-level synthesis.
CANDAR (Workshops)
Koki Honda, Kaijie Wei, Masatoshi Arai, Hideharu Amano
2020 — conf
Exploiting temporal parallelism in particle-based incompressive fluid simulation on FPGA.
CANDAR
Manfred Orsztynowicz, Hideharu Amano, Kenichi Kubota, Takaaki Miyajima
2020 J jnl
Extracting Success from IBM's 20-Qubit Machines Using Error-Aware Compilation.
ACM J. Emerg. Technol. Comput. Syst.
Shin Nishio, Yulu Pan, Takahiko Satoh, Hideharu Amano, Rodney Van Meter
2020 — conf
FPGA Acceleration of ROS2-Based Reinforcement Learning Agents.
CANDAR (Workshops)
Daniel Pinheiro Leal, Midori Sugaya, Hideharu Amano, Takeshi Ohkawa
2020 J jnl
FiC-RNN: A Multi-FPGA Acceleration Framework for Deep Recurrent Neural Networks.
IEICE Trans. Inf. Syst.
Yuxi Sun, Hideharu Amano
2020 J jnl
GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse-Grained Reconfigurable Architectures.
IEEE Trans. Very Large Scale Integr. Syst.
Takuya Kojima, Nguyen Anh Vu Doan, Hideharu Amano
2020 — conf
Horizontal division of deep learning applications with all-to-all communication on a multi-FPGA system.
CANDAR (Workshops)
Yugo Yamauchi, Akram Ben Ahmed, Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano
2020 — conf
Implementation of FM-Index Based Pattern Search on a Multi-FPGA System.
ARC
M. M. Imdad Ullah, Akram Ben Ahmed, Hideharu Amano
2020 — conf
Implementing a Multi-ejection Switch and Making the Use of Multiple Lanes in a Circuit-switched Multi-FPGA System.
CANDAR (Workshops)
Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano
2020 — conf
Layout-Oriented Low-Diameter Topology for HPC Interconnection Networks.
CANDAR (Workshops)
Ryuta Kawano, Hiroki Matsutani, Hideharu Amano
2020 — conf
Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization.
COOL CHIPS
Kimiyoshi Usami, Sosuke Akiba, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Kenta Suzuki, Yasuo Kanda
2020 J jnl
Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks.
IEICE Trans. Inf. Syst.
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2019 — conf
A Coarse-Grained Reconfigurable Architecture with a Fault Tolerant Non-Volatile Configurable Memory.
FPT
Takeharu Ikezoe, Takuya Kojima, Hideharu Amano
2019 J jnl
A Fine-Grained Multicasting of Configuration Data for Coarse-Grained Reconfigurable Architectures.
IEICE Trans. Inf. Syst.
Takuya Kojima, Hideharu Amano
2019 — conf
A Preliminary Evaluation of Building Block Computing Systems.
MCSoC
Sayaka Terashima, Takuya Kojima, Hayate Okuhara, Kazusa Musha, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Mitaro Namiki
2019 — conf
A Rapid Optimization Method for Visual Indirect SLAM Using a Subset of Feature Points.
CANDAR Workshops
Ryosuke Kazami, Hideharu Amano
2019 — conf
A STDM (Static Time Division Multiplexing) Switch on a Multi-FPGA System.
MCSoC
Keita Azegami, Kazusa Musha, Kazuei Hironaka, Akram Ben Ahmed, Michihiro Koibuchi, Yao Hu, Hideharu Amano
2019 — conf
A System Delay Monitor Exploiting Automatic Cell-Based Design Flow and Post-Silicon Calibration.
MCSoC
Hayate Okuhara, Ryosuke Kazami, Hideharu Amano
2019 — conf
Acceleration of ART Algorithm on an FPGA Board with Xilinx SDAccel.
CANDAR Workshops
Yasuaki Okamoto, Hideharu Amano
2019 — conf
Acceleration of Deep Recurrent Neural Networks with an FPGA cluster.
HEART
Yuxi Sun, Akram Ben Ahmed, Hideharu Amano
2019 — conf
An ARM-based heterogeneous FPGA accelerator for Hall thruster simulation.
HEART
Hiroyuki Noda, Manfred Orsztynowicz, Kensuke Iizuka, Takaaki Miyajima, Naoyuki Fujita, Hideharu Amano
2019 — conf
Deadlock-Free Layered Routing for Infiniband Networks.
CANDAR Workshops
Ryuta Kawano, Hiroki Matsutani, Hideharu Amano
2019 B conf
Demonstration of Flow-in-Cloud: A Multi-FPGA System.
FPL
Kazuei Hironaka, Kensuke Iizuka, Akram Ben Ahmed, M. M. Imdad Ullah, Yugo Yamauchi, Yuxi Sun, Miho Yamakura, Aoi Hiruma, Hideharu Amano
2019 B conf
Demonstration of Low Power Stream Processing Using a Variable Pipelined CGRA.
FPL
Takuya Kojima, Naoki Ando, Yusuke Matsushita, Hideharu Amano
2019 J jnl
Designing High-Performance Interconnection Networks with Host-Switch Graphs.
IEEE Trans. Parallel Distributed Syst.
Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano
2019 J jnl
Extracting Success from IBM's 20-Qubit Machines Using Error-Aware Compilation.
CoRR
Shin Nishio, Yulu Pan, Takahiko Satoh, Hideharu Amano, Rodney Van Meter
2019 — conf
FPGA/Python Co-Design for Lane Line Detection on a PYNQ-Z1 Board.
MCSoC
Koki Honda, Kaijie Wei, Hideharu Amano
2019 — conf
Implementing a large application(LSTM) on the multi-FPGA system: Flow-in-Cloud.
COOL CHIPS
Yugo Yamauchi, Kazusa Musha, Hideharu Amano
2019 — conf
Key-value Store Chip Design for Low Power Consumption.
COOL CHIPS
Yuta Tokusashi, Hiroki Matsutani, Hideharu Amano
2019 C conf
Multi-FPGA Management on Flow-in-Cloud Prototype System.
SNPD
Kazuei Hironaka, Akram Ben Ahmed, Hideharu Amano
2019 — conf
Real Chip Performance Evaluation on Through Chip Interface IP for Renesas SOTB 65nm Process.
CANDAR Workshops
Hideto Kayashima, Takuya Kojima, Hayate Okuhara, Tsunaaki Shidei, Hideharu Amano
2019 — conf
Refinements in Data Manipulation Method for Coarse Grained Reconfigurable Architectures.
ReCoSoC
Takuya Kojima, Hideharu Amano
2019 A* conf
Sparse 3-D NoCs with Inductive Coupling.
DAC
Michihiro Koibuchi, Lambert T. Leong, Tomohiro Totoki, Naoya Niwa, Hiroki Matsutani, Hideharu Amano, Henri Casanova
2019 — conf
The Evaluation of Partial Reconfiguration for a Multi-board FPGA System FiCSW.
HEART
Miho Yamakura, Kazuei Hironaka, Keita Azegami, Kazusa Musha, Hideharu Amano
2018 — conf
A Coarse Grained-Reconfigurable Accelerator with energy efficient MTJ-based Non-volatile Flip-flops.
ReConFig
Takeharu Ikezoe, Hideharu Amano, Junya Akaike, Kimiyoshi Usami, Masaru Kudo, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami
2018 B conf
A Configuration Data Multicasting Method for Coarse-Grained Reconfigurable Architectures.
FPL
Takuya Kojima, Hideharu Amano
2018 — conf
Accelerator-in-Switch: A Novel Cooperation Framework for FPGAs and GPUs.
FPT
Hideharu Amano
2018 — conf
Adaptive Body Bias Control Scheme for Ultra Low-Power Network-on-Chip Systems.
MCSoC
Akram Ben Ahmed, Hayate Okuhara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2018 — conf
An Extension of A Temperature Modeling Tool HotSpot 6.0 for Castle-of-Chips Stacking.
CANDAR Workshops
Tomohiro Totoki, Michihiro Koibuchi, Hideharu Amano
2018 — conf
An Trace-Driven Performance Prediction Method for Exploring NoC Design Optimization.
CANDAR Workshops
Naoya Niwa, Tomohiro Totoki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2018 J jnl
Analysis of Body Bias Control Using Overhead Conditions for Real Time Systems: A Practical Approach.
IEICE Trans. Inf. Syst.
Carlos Cesar Cortes Torres, Hayate Okuhara, Nobuyuki Yamasaki, Hideharu Amano
2018 J jnl
Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization.
IEEE Trans. Very Large Scale Integr. Syst.
Hayate Okuhara, Akram Ben Ahmed, Johannes Maximilian Kühn, Hideharu Amano
2018 — conf
AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation.
NOCS
Akram Ben Ahmed, Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2018 J jnl
Body Bias Control for Renewable Energy Source with a High Inner Resistance.
IEEE Trans. Multi Scale Comput. Syst.
Keita Azegami, Hayate Okuhara, Hideharu Amano
2018 — conf
C4: An FPGA-based Compression Algorithm for ExpEther.
CANDAR Workshops
Hideki Shimura, Hiroyuki Noda, Hideharu Amano
2018 — conf
Deep Learning on High Performance FPGA Switching Boards: Flow-in-Cloud.
ARC
Kazusa Musha, Tomohiro Kudoh, Hideharu Amano
2018 — conf
Design automation methodology of a critical path monitor for adaptive voltage controls.
COOL CHIPS
Ryosuke Kazami, Hayate Okuhara, Hideharu Amano
2018 J jnl
Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hayate Okuhara, Akram Ben Ahmed, Hideharu Amano
2018 — conf
Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application.
NVMSA
Kimiyoshi Usami, Junya Akaike, Sosuke Akiba, Masaru Kudo, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami
2018 J jnl
Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface.
Int. J. Netw. Comput.
Akio Nomura, Yusuke Matsushita, Junichiro Kadomoto, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano
2018 — conf
FPGA Design for Autonomous Vehicle Driving Using Binarized Neural Networks.
FPT
Kaijie Wei, Koki Honda, Hideharu Amano
2018 J jnl
Optimization of Body Biasing for Variable Pipelined Coarse-Grained Reconfigurable Architectures.
IEICE Trans. Inf. Syst.
Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano
2018 — conf
Performance Estimation for Exascale Reconfigurable Dataflow Platforms.
FPT
Ryota Yasudo, José Gabriel F. Coutinho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, Tobias Becker
2018 Misc conf
Performance Prediction for Large-Scale Heterogeneous Platforms.
FCCM
Ryota Yasudo, Ana Lucia Varbanescu, José Gabriel F. Coutinho, Wayne Luk, Hideharu Amano
2018 — book
Principles and Structures of FPGAs.
Hideharu Amano
2018 J jnl
Proxy Responses by FPGA-Based Switch for MapReduce Stragglers.
IEICE Trans. Inf. Syst.
Koya Mitsuzuka, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani
2018 — conf
Real Chip Evaluation of a Low Power CGRA with Optimized Application Mapping.
HEART
Takuya Kojima, Naoki Ando, Yusuke Matshushita, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano
2018 C conf
Superpixel Accelerator for Computer Vision Applications on Arria 10 SoC.
DDECS
Amila Akagic, Emir Buza, Razija Turcinhodzic, Hana Haseljic, Hiroyuki Noda, Hideharu Amano
2018 — conf
Towards an Optimized Multi FPGA Architecture with STDM Network: A Preliminary Study.
ARC
Kazuei Hironaka, Ng. Anh Vu Doan, Hideharu Amano
2018 — conf
k-Optimized Path Routing for High-Throughput Data Center Networks.
CANDAR
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano
2017 — conf
3D Layout of Spidergon, Flattened Butterfly and Dragonfly on a Chip Stack with Inductive Coupling Through Chip Interface.
ISPAN-FCST-ISCC
Hiroshi Nakahara, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi
2017 C conf
A Case for Uni-directional Network Topologies in Large-Scale Clusters.
CLUSTER
Michihiro Koibuchi, Tomohiro Totoki, Hiroki Matsutani, Hideharu Amano, Fabien Chaix, Ikki Fujiwara, Henri Casanova
2017 J jnl
A Layout-Oriented Routing Method for Low-Latency HPC Networks.
IEICE Trans. Inf. Syst.
Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2017 J jnl
A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing.
IEICE Trans. Inf. Syst.
Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2017 — conf
A Practical Collision Avoidance Method for an Inter-Chip Bus with Wireless Inductive through Chip Interface.
CANDAR
Akio Nomura, Junichiro Kadomoto, Tadahiro Kuroda, Hideharu Amano
2017 — conf
Acceleration of the aggregation process in a Hall-thruster simulation using Intel FPGA SDK for OpenCL.
HEART
Hiroyuki Noda, Ryotaro Sakai, Takaaki Miyajima, Naoyuki Fujita, Hideharu Amano
2017 B conf
Accelerator-in-switch: A framework for tightly coupled switching hub and an accelerator with FPGA.
FPL
Chiharu Tsuruta, Takahiro Kaneda, Naoki Nishikawa, Hideharu Amano
2017 — conf
An inductive-coupling link for 3-D Network-on-Chips.
ISOCC
Junichiro Kadomoto, Hideharu Amano, Tadahiro Kuroda
2017 J jnl
Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator.
IEICE Trans. Inf. Syst.
Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano
2017 — conf
Body bias control for renewable energy source with a high inner resistance.
COOL Chips
Keita Azegami, Hayate Okuhara, Hideharu Amano
2017 B conf
Body bias optimization for variable pipelined CGRA.
FPL
Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano
2017 — conf
Building block multi-chip systems using inductive coupling through chip interface.
ISOCC
Hideharu Amano, Tadahiro Kuroda, Hiroshi Nakamura, Kimiyoshi Usami, Masaaki Kondo, Hiroki Matsutani, Mitaro Namiki
2017 — conf
Building block operating system for 3D stacked computer systems with inductive coupling interconnect.
ISOCC
Shinsuke Hamada, Atsushi Koshiba, Mitaro Namiki, Hideharu Amano
2017 — conf
Digital embedded memory scheme using voltage scaling and body bias separation for low-power system.
ISOCC
Yusuke Yoshida, Kimiyoshi Usami, Hideharu Amano
2017 — conf
FPGA-based accelerator for losslessly quantized convolutional neural networks.
FPT
Mankit Sit, Ryosuke Kazami, Hideharu Amano
2017 — conf
Glitch-aware variable pipeline optimization for CGRAs.
ReConFig
Takuya Kojima, Naoki Ando, Hayate Okuhara, Hideharu Amano
2017 B conf
HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies.
ICPADS
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2017 A* conf
High-Bandwidth Low-Latency Approximate Interconnection Networks.
HPCA
Daichi Fujiki, Kiyo Ishii, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Henri Casanova, Michihiro Koibuchi
2017 B conf
Implementation of Bitsliced AES Encryption on CUDA-Enabled GPU.
NSS
Naoki Nishikawa, Hideharu Amano, Keisuke Iwai
2017 B conf
In-switch approximate processing: Delayed tasks management for MapReduce applications.
FPL
Koya Mitsuzuka, Ami Hayashi, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani
2017 — conf
Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI.
VLSI-SoC (Selected Papers)
Kimiyoshi Usami, Shunsuke Kogure, Yusuke Yoshida, Ryo Magasaki, Hideharu Amano
2017 C conf
Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI.
VLSI-SoC
Kimiyoshi Usami, Shunsuke Kogure, Yusuke Yoshida, Ryo Magasaki, Hideharu Amano
2017 — conf
Leveraging asymmetric body bias control for low power LSI design.
COOL Chips
Hayate Okuhara, Akram Ben Ahmed, Johannes Maximilian Kühn, Hideharu Amano
2017 — conf
Multi-objective Optimization for Application Mapping and Body Bias Control on a CGRA.
MCSoC
Nguyen Anh Vu Doan, Yusuke Matsushita, Naoki Ando, Hayate Okuhara, Hideharu Amano
2017 B conf
Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks.
ICPP
Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano
2017 — conf
Panel discussions: "Cool chips for the next decade".
COOL Chips
Hideharu Amano, Tadao Nakamura, Hiroaki Kobayashi, Hironori Kasahara, Yoshiaki Hagiwara, Jeffrey L. Burns, David Brash
2017 — conf
Performance Evaluation of PEACH3: Field-Programmable Gate Array Switch for Tightly Coupled Accelerators.
HEART
Takahiro Kaneda, Ryotaro Sakai, Naoki Nishikawa, Toshihiro Hanawa, Chiharu Tsuruta, Hideharu Amano
2017 J jnl
Power Optimization Methodology for Ultralow Power Microcontroller With Silicon on Thin BOX MOSFET.
IEEE Trans. Very Large Scale Integr. Syst.
Hayate Okuhara, Yu Fujita, Kimiyoshi Usami, Hideharu Amano
2017 J jnl
Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers.
IEEE Trans. Computers
Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura
2017 — conf
Scalable deep neural network accelerator cores with cubic integration using through chip interface.
ISOCC
Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima, Hideharu Amano
2017 — conf
The Design and Implementation of Scalable Deep Neural Network Accelerator Cores.
MCSoC
Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima, Hideharu Amano
2017 J jnl
The First 25 Years of the FPL Conference: Significant Papers.
ACM Trans. Reconfigurable Technol. Syst.
Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, João M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang
2017 — conf
Towards Tightly-coupled Datacenter with Free-space Optical Links.
ICCBDC
Yao Hu, Hiroaki Hara, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi
2017 — conf
XYZ-Randomization using TSVs for Low-Latency Energy Efficient 3D-NoCs.
NOCS
Hiroshi Nakahara, Ng. Anh Vu Doan, Ryota Yasudo, Hideharu Amano
2016 C conf
ACRO: Assignment of channels in reverse order to make arbitrary routing deadlock-free.
ICIS
Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2016 — conf
Acceleration of Full-PIC Simulation on a CPU-FPGA Tightly Coupled Environment.
MCSoC
Ryotaro Sakai, Naru Sugimoto, Takaaki Miyajima, Naoyuki Fujita, Hideharu Amano
2016 J jnl
An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications.
IEICE Trans. Electron.
Atsushi Koshiba, Mikiko Sato, Kimiyoshi Usami, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki
2016 — conf
An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips.
A-SSCC
Junichiro Kadomoto, Tomoki Miyata, Hideharu Amano, Tadahiro Kuroda
2016 B conf
Body bias grain size exploration for a coarse grained reconfigurable accelerator.
FPL
Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano
2016 J jnl
Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces.
IEEE Trans. Very Large Scale Integr. Syst.
Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano
2016 — conf
From FLOPS to BYTES: disruptive change in high-performance computing towards the post-moore era.
Conf. Computing Frontiers
Satoshi Matsuoka, Hideharu Amano, Kengo Nakajima, Koji Inoue, Tomohiro Kudoh, Naoya Maruyama, Kenjiro Taura, Takeshi Iwashita, Takahiro Katagiri, Toshihiro Hanawa, Toshio Endo
2016 — conf
Implementing Breadth-First Search on a Compact Supercomputer Suiren.
CANDAR
Takuji Mitsuishi, Takahiro Kaneda, Sunao Torii, Hideharu Amano
2016 — conf
LOREN: A Scalable Routing Method for Layout-Conscious Random Topologies.
CANDAR
Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2016 A* conf
Leveraging FDSOI through body bias domain partitioning and bias search.
DAC
Johannes Maximilian Kühn, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel
2016 — conf
MuCCRA4-BB: A fine-grained body biasing capable DRP.
COOL Chips
Johannes Maximilian Kühn, Akram Ben Ahmed, Hayate Okuhara, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel
2016 J jnl
Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Systems.
IEICE Trans. Electron.
Akram Ben Ahmed, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano
2016 J jnl
Novel Chip Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface.
IEICE Trans. Inf. Syst.
Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2016 — conf
On-the-Fly Data Compression/Decompression Mechanism with ExpEther.
CANDAR
Hideki Shimura, Takuji Mitsuishi, Masaki Kan, Takashi Yoshikawa, Hideharu Amano
2016 J jnl
Optical network technologies for HPC: computer-architects point of view.
IEICE Electron. Express
Michihiro Koibuchi, Ikki Fujiwara, Kiyo Ishii, Shu Namiki, Fabien Chaix, Hiroki Matsutani, Hideharu Amano, Tomohiro Kudoh
2016 C conf
Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication.
PDP
Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2016 — conf
Trax solver on Zynq using incremental update algorithm.
FPT
Hiroshi Nakahara, Tetsui Ohkubo, Hideki Shimura, Ryotaro Sakai, Chiharu Tsuruta, Takahiro Kaneda, Hideharu Amano
2016 — conf
Variable pipeline structure for Coarse Grained Reconfigurable Array CMA.
FPT
Naoki Ando, Koichiro Masuyama, Hayate Okuhara, Hideharu Amano
2016 — conf
Vertical Packet Switching Elevator Network Using Inductive Coupling ThruChip Interface.
CANDAR
Akio Nomura, Hiroki Matsutani, Tadahiro Kuroda, Junichiro Kadomoto, Yusuke Matsushita, Hideharu Amano
2016 — conf
Zynq Cluster for CFD Parametric Survey.
ARC
Naru Sugimoto, Takaaki Miyajima, Ryotaro Sakai, Yasunori Osana, Naoyuki Fujita, Hideharu Amano
2015 — conf
3D Shared Bus Architecture Using Inductive Coupling Interconnect.
MCSoC
Akio Nomura, Yu Fujita, Hiroki Matsutani, Hideharu Amano
2015 B conf
7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2.
FPL
Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano
2015 — conf
A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2.
ReConFig
Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano
2015 J jnl
A Co-Processor Design for an Energy Efficient Reconfigurable Accelerator CMA.
Int. J. Netw. Comput.
Mai Izawa, Nobuaki Ozaki, Yusuke Koizumi, Rie Uno, Hideharu Amano
2015 J jnl
A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units.
IEICE Trans. Electron.
Atsushi Koshiba, Motoki Wada, Ryuichi Sakamoto, Mikiko Sato, Tsubasa Kosaka, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki
2015 J jnl
A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode.
IEICE Trans. Electron.
Koichiro Ishibashi, Nobuyuki Sugii, Shiro Kamohara, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham
2015 J jnl
A Toolchain for Dynamic Function Off-load on CPU-FPGA Platforms.
J. Inf. Process.
Takaaki Miyajima, David B. Thomas, Hideharu Amano
2015 — conf
A leakage current monitor circuit using silicon on thin BOX MOSFET for dynamic back gate bias control.
COOL Chips
Hayate Okuhara, Kimiyoshi Usami, Hideharu Amano
2015 — conf
A metamorphotic Network-on-Chip for various types of parallel applications.
ASAP
Seiichi Tade, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi
2015 A conf
An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET.
ISLPED
Hayate Okuhara, Kuniaki Kitamori, Yu Fujita, Kimiyoshi Usami, Hideharu Amano
2015 J jnl
Breadth First Search on Cost-efficient Multi-GPU Systems.
SIGARCH Comput. Archit. News
Takuji Mitsuishi, Jun Suzuki, Yuki Hayashi, Masaki Kan, Hideharu Amano
2015 J jnl
Courier: A Toolchain for Application Acceleration on Heterogeneous Platforms.
IPSJ Trans. Syst. LSI Des. Methodol.
Takaaki Miyajima, David B. Thomas, Hideharu Amano
2015 — conf
Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips.
MCSoC
Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2015 — conf
Fined-grained body biasing for frequency scaling in advanced SOI processes.
COOL Chips
Johannes Maximilian Kühn, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel
2015 J jnl
Off-Loading LET Generation to PEACH2: A Switching Hub for High Performance GPU Clusters.
SIGARCH Comput. Archit. News
Chiharu Tsuruta, Yohei Miki, Takuya Kuhara, Hideharu Amano, Masayuki Umemura
2015 — conf
On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck.
NOCS
Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura
2015 C conf
Optimized Core-Links for Low-Latency NoCs.
PDP
Ryuta Kawano, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi
2015 — conf
Power Optimization Considering the Chip Temperature of Low Power Reconfigurable Accelerator CMA-SOTB.
CANDAR
Yu Fujita, Hayate Okuhara, Koichiro Masuyama, Hideharu Amano
2015 B conf
Reduction calculator in an FPGA based switching Hub for high performance clusters.
FPL
Takuya Kuhara, Chiharu Tsuruta, Toshihiro Hanawa, Hideharu Amano
2015 B conf
Significant papers from the first 25 years of the FPL conference.
FPL
Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, João M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang
2015 A conf
Spatial and temporal granularity limits of body biasing in UTBB-FDSOI.
DATE
Johannes Maximilian Kühn, Dustin Peterson, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel
2015 — conf
Towards Unification of Accelerated Computing and Interconnection For Extreme-Scale Computing.
ARC
Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Hideharu Amano, Hitoshi Murai, Masayuki Umemura, Mitsuhisa Sato
2015 — conf
Trax solver on Zynq with Deep Q-Network.
FPT
Naru Sugimoto, Takuji Mitsuishi, Takahiro Kaneda, Chiharu Tsuruta, Ryotaro Sakai, Hideki Shimura, Hideharu Amano
2014 J jnl
3D NoC with Inductive-Coupling Links for Building-Block SiPs.
IEEE Trans. Computers
Yasuhiro Take, Hiroki Matsutani, Daisuke Sasaki, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano
2014 — conf
A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology.
COOL Chips
Koichiro Ishibashi, Nobuyuki Sugii, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham, Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Hidekazu Oda, Takumi Hasegawa, Shinobu Okanishi, Hiroshi Yanagita, Shiro Kamohara, Masaru Kadoshima, Keiichi Maekawa, Tomohiro Yamashita, Duc-Hung Le, Takumu Yomogita, Masaru Kudo, Kuniaki Kitamori, Shuya Kondo, Yuuki Manzawa
2014 — conf
A Preliminarily Evaluation of PEACH3: A Switching Hub for Tightly Coupled Accelerators.
CANDAR
Takuya Kuhara, Takahiro Kaneda, Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Hideharu Amano
2014 — conf
A Thermal Management System for Building Block Computing Systems.
MCSoC
Yu Fujita, Kimiyoshi Usami, Hideharu Amano
2014 B conf
A high speed design and implementation of dynamically reconfigurable processor using 28NM SOI technology.
FPL
Toru Katagiri, Hideharu Amano
2014 — conf
A low power NoC router using the marching memory through type.
COOL Chips
Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura
2014 — conf
A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode.
Hot Chips Symposium
Shiro Kamohara, Nobuyuki Sugii, Koichiro Ishibashi, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham
2014 J jnl
Accelerating Breadth First Search on GPU-BOX.
SIGARCH Comput. Archit. News
Takuji Mitsuishi, Shimpei Nomura, Jun Suzuki, Yuki Hayashi, Masaki Kan, Hideharu Amano
2014 J jnl
An Automatic Mixed Software Hardware Pipeline Builder for CPU-FPGA Platforms.
CoRR
Takaaki Miyajima, David B. Thomas, Hideharu Amano
2014 B conf
Body bias control for a coarse grained reconfigurable accelerator implemented with Silicon on Thin BOX technology.
FPL
Honlian Su, Yu Fujita, Hideharu Amano
2014 — conf
Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors.
ASP-DAC
Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui, Weihan Wang, Hideharu Amano, Hiroaki Kobayashi, Ryuichi Sakamoto, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
2014 A conf
Design and evaluation of fine-grained power-gating for embedded microprocessors.
DATE
Masaaki Kondo, Hiroaki Kobayashi, Ryuichi Sakamoto, Motoki Wada, Jun Tsukamoto, Mitaro Namiki, Weihan Wang, Hideharu Amano, Kensaku Matsunaga, Masaru Kudo, Kimiyoshi Usami, Toshiya Komoda, Hiroshi Nakamura
2014 — conf
Design of a low power NoC router using Marching Memory Through type.
NOCS
Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura
2014 J jnl
Dynamic Power Consumption Optimization for Inductive-Coupling based Wireless 3D NoCs.
IPSJ Trans. Syst. LSI Des. Methodol.
Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2014 — conf
FPGA Implementation of Viscous Function in a Package for Computational Fluid Dynamics.
CANDAR
Dipikarani Mishra, Mao Hatto, Takuya Kuhara, Naoyuki Fujita, Yasunori Osana, Hideharu Amano
2014 — conf
Hardware/software co-design architecture for Blokus Duo solver.
FPT
Naru Sugimoto, Hideharu Amano
2014 — conf
Image processing by A 0.3V 2MW coarse-grained reconfigurable accelerator CMA-SOTB with a solar battery.
FPT
Yu Fujita, Koichiro Masuyama, Hideharu Amano
2014 A conf
Low-latency wireless 3D NoCs via randomized shortcut chips.
DATE
Hiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, Paul Bogdan, Radu Marculescu, Hideharu Amano
2014 J jnl
Performance Analysis of the Multi-GPU System with ExpEther.
SIGARCH Comput. Archit. News
Shimpei Nomura, Takuji Mitsuishi, Jun Suzuki, Yuki Hayashi, Masaki Kan, Hideharu Amano
2014 J jnl
Reconfigurable Out-of-Order System for Fluid Dynamics Computation Using Unstructured Mesh.
IEICE Trans. Inf. Syst.
Takayuki Akamine, Mohamad Sofian Abu Talip, Yasunori Osana, Naoyuki Fujita, Hideharu Amano
2014 — conf
Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating.
ISSoC
Kimiyoshi Usami, Makoto Miyauchi, Masaru Kudo, Kazumitsu Takagi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
2013 — conf
A Circuit Division Method for High-Level Synthesis on Multi-FPGA Systems.
AINA Workshops
Kugami Daiki, Takaaki Miyajima, Hideharu Amano
2013 — conf
A Co-processor Design of an Energy Efficient Reconfigurable Accelerator CMA.
CANDAR
Mai Izawa, Nobuyuki Ozaki, Yusuke Koizumi, Rie Uno, Hideharu Amano
2013 — conf
A Routing Strategy for Inductive-Coupling Based Wireless 3-D NoCs by Maximizing Topological Regularity.
ICA3PP (2)
Daisuke Sasaki, Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2013 J jnl
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface.
IEEE Micro
Noriyuki Miura, Yusuke Koizumi, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2013 — conf
A case for wireless 3D NoCs for CMPs.
ASP-DAC
Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Yasuhiro Take, Daisuke Sasaki, Hao Zhang, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano
2013 B conf
A fully pipelined FPGA architecture for stochastic simulation of chemical systems.
FPL
David B. Thomas, Hideharu Amano
2013 B conf
A hardware complete detection mechanism for an energy efficient reconfigurable accelerator CMA.
FPL
Akihito Tsusaka, Mai Izawa, Rie Uno, Nobuyuki Ozaki, Hideharu Amano
2013 — conf
A low power reconfigurable accelerator using a back-gate bias control technique.
FPT
Hongliang Su, Weihan Wang, Kuniaki Kitamori, Hideharu Amano
2013 — conf
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface.
COOL Chips
Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2013 — conf
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface.
Hot Chips Symposium
Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2013 — conf
A speculative gather system for Cool Mega-Array.
FPT
Rie Uno, Nobuaki Ozaki, Mai Izawa, Akihito Tsusaka, Takaaki Miyajima, Hideharu Amano
2013 J jnl
Adaptive Flux Calculation Scheme in Advection Term Computation Using Partial Reconfiguration.
Int. J. Netw. Comput.
Mohamad Sofian Abu Talip, Takayuki Akamine, Mao Hatto, Yasunori Osana, Naoyuki Fujita, Hideharu Amano
2013 — conf
An FPGA Acceleration for the Kd-tree Search in Photon Mapping.
ARC
Takuya Kuhara, Takaaki Miyajima, Masato Yoshimi, Hideharu Amano
2013 — conf
An FPGA Implementation of Reconfigurable Real-Time Vision Architecture.
AINA Workshops
Jorge Hiraiwa, Hideharu Amano
2013 — conf
Artificial intelligence of Blokus Duo on FPGA using Cyber Work Bench.
FPT
Naru Sugimoto, Takaaki Miyajima, Takuya Kuhara, Yuki Katuta, Takushi Mitsuichi, Hideharu Amano
2013 B conf
Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links.
FPL
Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2013 J jnl
Design and Implementation of IP-based iSCSI Offload Engine on an FPGA.
IPSJ Trans. Syst. LSI Des. Methodol.
Amila Akagic, Hideharu Amano
2013 — conf
Dynamic power on/off method for 3D NoCs with wireless inductive-coupling links.
COOL Chips
Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2013 J jnl
Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design.
IEICE Trans. Electron.
Hiroshi Nakamura, Weihan Wang, Yuya Ohta, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Mitaro Namiki
2013 J jnl
Foreword.
IEICE Trans. Inf. Syst.
Hideharu Amano
2013 J jnl
Foreword.
IEICE Trans. Inf. Syst.
Hideharu Amano
2013 — conf
Headfirst sliding routing: A time-based routing scheme for bus-NoC hybrid 3-D architecture.
NOCS
Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2013 J jnl
High-Speed Fully-Adaptable CRC Accelerators.
IEICE Trans. Inf. Syst.
Amila Akagic, Hideharu Amano
2013 — conf
MCMA: A modular processing elements array based low-power coarse-grained reconfigurable accelerator.
ReConFig
Remi Chaintreuil, Rie Uno, Hideharu Amano
2013 — conf
Partially reconfigurable flux calculation scheme in advection term computation.
FPT
Mohamad Sofian Abu Talip, Takayuki Akamine, Mao Hatto, Yasunori Osana, Naoyuki Fujita, Hideharu Amano
2013 — conf
Research of PE Array Connection Network for Cool Mega-Array.
AINA Workshops
Rie Uno, Nobuaki Ozaki, Hideharu Amano
2013 — conf
Task level pipelining with PEACH2: An FPGA switching fabric for high performance computing.
FPT
Takaaki Miyajima, Takuya Kuhara, Toshihiro Hanawa, Hideharu Amano, Taisuke Boku
2013 — conf
Tutorial: Introduction to Interconnection Networks from System Area Network to Network on Chips.
CANDAR
Hideharu Amano
2013 J jnl
Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs.
IEICE Trans. Inf. Syst.
Hao Zhang, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano
2012 Misc conf
A Domain Specific Language and Toolchain for OpenCV Runtime Binary Acceleration Using GPU.
ICNC
Takaaki Miyajima, David B. Thomas, Hideharu Amano
2012 A* conf
A case for random shortcut topologies for HPC interconnects.
ISCA
Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casanova
2012 — conf
A multi-Vdd dynamic variable-pipeline on-chip router for CMPs.
ASP-DAC
Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano
2012 — conf
A study of adaptable co-processors for Cyclic Redundancy Check on an FPGA.
FPT
Amila Akagic, Hideharu Amano
2012 B conf
An OpenCL Runtime Library for Embedded Multi-Core Accelerator.
RTCSA
Ryuichi Sakamoto, Mikiko Sato, Yusuke Koizumi, Hideharu Amano, Mitaro Namiki
2012 B conf
CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect.
FPL
Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2012 — conf
Castle of Chips: A New Chip Stacking Structure with Wireless Inductive Coupling for Large Scale 3-D Multicore Systems.
NBiS
Hideharu Amano
2012 — conf
Cost Effective Implementation of Flux Limiter Functions Using Partial Reconfiguration.
ARC
Mohamad Sofian Abu Talip, Takayuki Akamine, Yasunori Osana, Naoyuki Fujita, Hideharu Amano
2012 — conf
Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect.
FPT
Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2012 — conf
Dynamically reconfigurable flux limiter functions in MUSCL scheme.
ReCoSoC
Mohamad Sofian Abu Talip, Takayuki Akamine, Yasunori Osana, Naoyuki Fujita, Hideharu Amano
2012 — conf
Extension of Memory Controller Equipped with MuCCRA-3-DP: Dynamically Reconfigurable Processor Array.
NBiS
Toru Katagiri, Kazuei Hironaka, Hideharu Amano
2012 — conf
Fine-Grained Power Control Using A Multi-Voltage Variable Pipeline Router.
MCSoC
Takeo Nakamura, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano
2012 J jnl
Foreword.
IEICE Trans. Inf. Syst.
Hideharu Amano
2012 J jnl
Foreword.
IEICE Trans. Inf. Syst.
Hideharu Amano
2012 — ch.
Geyser.
Handbook of Energy-Aware and Green Computing
Hiroshi Sasaki, Hideharu Amano, Kimiyoshi Usami, Masaaki Kondo, Mitaro Namiki, Hiroshi Nakamura
2012 J jnl
Partial Reconfiguration of Flux Limiter Functions in MUSCL Scheme Using FPGA.
IEICE Trans. Inf. Syst.
Mohamad Sofian Abu Talip, Takayuki Akamine, Yasunori Osana, Naoyuki Fujita, Hideharu Amano
2012 B conf
Performance analysis of fully-adaptable CRC accelerators on an FPGA.
FPL
Amila Akagic, Hideharu Amano
2012 B conf
Reconfigurable out-of-order mechanism generator for unstructured grid computation in computational fluid dynamics.
FPL
Takayuki Akamine, Kenta Inakagata, Yasunori Osana, Naoyuki Fujita, Hideharu Amano
2012 — conf
Removing Context Memory from a Multi-context Dynamically Reconfigurable Processor.
MCSoC
Hideharu Amano, Masayuki Kimura, Nobuaki Ozaki
2012 — conf
Trade-off analysis of fine-grained power gating methods for functional units in a CPU.
COOL Chips
Weihan Wang, Yuya Ohta, Yoshifumi Ishii, Kimiyoshi Usami, Hideharu Amano
2012 — conf
Vertical Link On/Off Control Methods for Wireless 3-D NoCs.
ARCS
Hao Zhang, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano
2011 — ch.
3-D NoC on Inductive Wireless Interconnect.
3D Integration for NoC-based SoC Architectures
Hiroki Matsutani, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano
2011 — conf
A Dynamic Link-Width Optimization for Network-on-Chip.
RTCSA (2)
Daihan Wang, Michihiro Koibuchi, Tomohiro Yoneda, Hiroki Matsutani, Hideharu Amano
2011 J jnl
A Leakage Efficient Data TLB Design for Embedded Processors.
IEICE Trans. Inf. Syst.
Lei Zhao, Hui Xu, Daisuke Ikebuchi, Tetsuya Sunata, Mitaro Namiki, Hideharu Amano
2011 J jnl
A Leakage Efficient Instruction TLB Design for Embedded Processors.
IEICE Trans. Inf. Syst.
Zhao Lei, Hui Xu, Daisuke Ikebuchi, Tetsuya Sunata, Mitaro Namiki, Hideharu Amano
2011 J jnl
A Switch-Tagged Routing Methodology for PC Clusters with VLAN Ethernet.
IEEE Trans. Parallel Distributed Syst.
Michihiro Koibuchi, Tomohiro Otsuka, Tomohiro Kudoh, Hideharu Amano
2011 — conf
A vertical bubble flow network using inductive-coupling for 3-D CMPs.
NOCS
Hiroki Matsutani, Yasuhiro Take, Daisuke Sasaki, Masayuki Kimura, Yuki Ono, Yukinori Nishiyama, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano
2011 J jnl
An analytical network performance model for SIMD processor CSX600 interconnects.
J. Syst. Archit.
Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano
2011 J jnl
An implementation of out-of-order execution system for acceleration of computational fluid dynamics on FPGAs.
SIGARCH Comput. Archit. News
Takayuki Akamine, Kenta Inakagata, Yasunori Osana, Naoyuki Fujita, Hideharu Amano
2011 — conf
Cool Mega-Array: A highly energy efficient reconfigurable accelerator.
FPT
Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo
2011 J jnl
Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips.
IEEE Micro
Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo
2011 J jnl
Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units.
Inf. Media Technol.
Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano
2011 J jnl
Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units.
IPSJ Trans. Syst. LSI Des. Methodol.
Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano
2011 J jnl
Design and Implementation of Echo Instructions for an Embedded Processor.
IPSJ Trans. Syst. LSI Des. Methodol.
Arda Karaduman, Iver Stubdal, Hideharu Amano
2011 — conf
Dynamic V
ARC
Tatsuya Yamamoto, Kazuei Hironaka, Yuki Hayakawa, Masayuki Kimura, Hideharu Amano, Kimiyoshi Usami
2011 — conf
Geyser-2: The second prototype CPU with fine-grained run-time power gating.
ASP-DAC
Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo
2011 J jnl
High speed CRC with 64-bit generator polynomial on an FPGA.
SIGARCH Comput. Archit. News
Amila Akagic, Hideharu Amano
2011 J jnl
Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, Hideharu Amano
2011 A conf
On-chip detection methodology for break-even time of power gated function units.
ISLPED
Kimiyoshi Usami, Yuya Goto, Kensaku Matsunaga, Satoshi Koyama, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura
2011 Misc conf
Performance Evaluation of Power-Aware Multi-tree Ethernet for HPC Interconnects.
ICNC
Michihiro Koibuchi, Takafumi Watanabe, Atsushi Minamihata, Masahiro Nakao, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano
2011 J jnl
Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano
2011 — conf
Power Centric Application Mapping for Dynamically Reconfigurable Processor Array with Dual Vdd and Dual Vth.
ReConFig
Kazuei Hironaka, Hideharu Amano
2011 J jnl
Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors.
IEEE Trans. Computers
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga
2011 Misc conf
Proposal of Auto MPI Expansion Tool for Cell Broadband Engine Cluster.
ICNC
Tetsuya Nakahama, Masahiro Yamada, Masato Yoshimi, Hideharu Amano
2011 — conf
Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations.
FPT
Masayuki Kimura, Kazuei Hironaka, Hideharu Amano
2011 — ch.
Run-Time Power-Gating Techniques for Low-Power On-Chip Networks.
Low Power Networks-on-Chip
Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura, Hideharu Amano
2011 — conf
SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator.
COOL Chips
Nobuaki Ozaki, Kimiyoshi Usami, Hideharu Amano, Mitaro Namiki, Hiroshi Nakamura, Masaaki Kondo
2011 — conf
The realtime image processing demonstration with CMA-1: An ultra low-power reconfigurable accelerator.
FPT
Kazuei Hironaka, Nobuaki Ozaki, Hideharu Amano
2011 Misc conf
Vegeta: An Implementation and Evaluation of Development-Support Middleware on Multiple OpenCL Platform.
ICNC
Akihiro Shitara, Tetsuya Nakahama, Masahiro Yamada, Toshiaki Kamata, Yuri Nishikawa, Masato Yoshimi, Hideharu Amano
2010 — conf
A Deadlock-Free Non-minimal Fully Adaptive Routing Using Virtual Cut-Through Switching.
NAS
Yuri Nishikawa, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano
2010 — conf
A Performance Evaluation of CUBE: One-Dimensional 512 FPGA Cluster.
ARC
Masato Yoshimi, Yuri Nishikawa, Mitsunori Miki, Tomoyuki Hiroyasu, Hideharu Amano, Oskar Mencer
2010 — conf
A datapath classification method for FPGA-based scientific application accelerator systems.
FPT
Yui Ogawa, Tomonori Ooya, Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano, Yuichiro Shibata, Kiyoshi Oguri
2010 — conf
A variable-pipeline on-chip router optimized to traffic pattern.
NoCArc@MICRO
Yuto Hirata, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2010 — conf
Adaptive power gating for function units in a microprocessor.
ISQED
Kimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
2010 J jnl
Automatic Pipeline Construction Focused on Similarity of Rate Law Functions for an FPGA-based Biochemical Simulator.
IPSJ Trans. Syst. LSI Des. Methodol.
Hideki Yamada, Yui Ogawa, Tomonori Ooya, Tomoya Ishimori, Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano, Yuichiro Shibata, Kiyoshi Oguri
2010 — conf
Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating.
ASP-DAC
Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo
2010 J jnl
Implementation and evaluation of an arithmetic pipeline on FLOPS-2D: multi-FPGA system.
SIGARCH Comput. Archit. News
Hirokazu Morishita, Kenta Inakagata, Yasunori Osana, Naoyuki Fujita, Hideharu Amano
2010 — conf
MuCCRA-3: a low power dynamically reconfigurable processor array.
ASP-DAC
Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano
2010 — ed.
Reconfigurable Computing: Architectures, Tools and Applications, 6th International Symposium, ARC 2010, Bangkok, Thailand, March 17-19, 2010. Proceedings
ARC
Phaophak Sirisuk, Fearghal Morgan, Tarek A. El-Ghazawi, Hideharu Amano
2010 — conf
Reducing instruction TLB's leakage power consumption for embedded processors.
Green Computing Conference
Zhao Lei, Hui Xu, Daisuke Ikebuchi, Hideharu Amano, Tetsuya Sunata, Mitaro Namiki
2010 — conf
Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping.
FPT
Kazuei Hironaka, Masayuki Kimura, Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano
2010 — conf
Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks.
NAS
José Miguel Montañana Aliaga, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano
2010 — conf
Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs.
NOCS
Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano
2010 — conf
Wire congestion aware synthesis for a dynamically reconfigurable processor.
FPT
Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, Hideharu Amano
2009 J jnl
A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs.
IEICE Trans. Inf. Syst.
Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2009 — conf
A Modular Approach to Heterogeneous Biochemical Model Simulation on an FPGA.
ReConFig
Hideki Yamada, Yasunori Osana, Tomoya Ishimori, Tomonori Ooya, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano, Yuichiro Shibata, Kiyoshi Oguri
2009 — conf
A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array.
ERSA
Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano
2009 Misc conf
An On/Off Link Activation Method for Power Regulation in InfiniBand.
PDPTA
José Miguel Montañana Aliaga, Michihiro Koibuchi, Takafumi Watanabe, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano
2009 A conf
An on/off link activation method for low-power ethernet in PC clusters.
IPDPS
Michihiro Koibuchi, Tomohiro Otsuka, Hiroki Matsutani, Hideharu Amano
2009 — conf
Balanced Dimension-Order Routing for k-ary n-cubes.
ICPP Workshops
José Miguel Montañana Aliaga, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano
2009 — conf
Cache Controller Design on Ultra Low Leakage Embedded Processors.
ARCS
Lei Zhao, Hui Xu, Naomi Seki, Yoshiki Saito, Yohei Hasegawa, Kimiyoshi Usami, Hideharu Amano
2009 J jnl
Code Compression with Split Echo Instructions.
IEICE Trans. Inf. Syst.
Iver Stubdal, Arda Karaduman, Hideharu Amano
2009 — conf
Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors.
ERSA
Toru Sano, Yoshiki Saito, Hideharu Amano
2009 B conf
Configuring area and performance: Empirical evaluation on an FPGA-based biochemical simulator.
FPL
Tomonori Ooya, Hideki Yamada, Tomoya Ishimori, Yuichiro Shibata, Yasunori Osana, Kiyoshi Oguri, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano
2009 Misc conf
Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression.
VLSI Design
Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura
2009 A conf
Evaluation of a multicore reconfigurable architecture with variable core sizes.
IPDPS
Vu Manh Tuan, Naohiro Katsura, Hiroki Matsutani, Hideharu Amano
2009 J jnl
Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network.
IEEE Trans. Parallel Distributed Syst.
Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, D. Frank Hsu, Hideharu Amano
2009 B conf
Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors.
FPL
Toru Sano, Yoshiki Saito, Masaru Kato, Hideharu Amano
2009 J jnl
Guest Editors' Introduction: ICFPT 2007.
ACM Trans. Reconfigurable Technol. Syst.
Hideharu Amano, Tadao Nakamura
2009 — conf
Japanese Dynamically Reconfigurable Processors.
ERSA
Hideharu Amano
2009 — conf
Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells.
FPT
Keiichiro Hirai, Masaru Kato, Yoshiki Saito, Hideharu Amano
2009 B conf
Modularizing flux limiter functions for a Computational Fluid Dynamics accelerator on FPGAs.
FPL
Kenta Inakagata, Hirokazu Morishita, Yasunori Osana, Naoyuki Fujita, Hideharu Amano
2009 B conf
MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link.
FPL
Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano
2009 C conf
Performance Analysis of ClearSpeed's CSX600 Interconnects.
ISPA
Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Akihiro Shitara, Kenichi Miura, Hideharu Amano
2009 — conf
Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical Simulator.
ARC
Tomoya Ishimori, Hideki Yamada, Yuichiro Shibata, Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Kiyoshi Oguri
2009 A* conf
Prediction router: Yet another low latency on-chip router architecture.
HPCA
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga
2008 — conf
A Lightweight Fault-Tolerant Mechanism for Network-on-Chip.
NOCS
Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy Mark Pinkston
2008 J jnl
A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors.
IEICE Trans. Inf. Syst.
Vu Manh Tuan, Hideharu Amano
2008 — conf
A Method for Capturing State Data on Dynamically Reconfigurable Processors.
ERSA
Vu Manh Tuan, Hideharu Amano
2008 — conf
A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor.
ARC
Vu Manh Tuan, Hideharu Amano
2008 J jnl
A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processors.
IEICE Trans. Inf. Syst.
Vu Manh Tuan, Hideharu Amano
2008 J jnl
A Retargetable Compiler Based on Graph Representation for Dynamically Reconfigurable Processor Arrays.
IEICE Trans. Inf. Syst.
Vasutan Tunbunheng, Hideharu Amano
2008 C conf
A fine-grain dynamic sleep control scheme in MIPS R3000.
ICCD
Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
2008 B conf
A link removal methodology for Networks-on-Chip on reconfigurable systems.
FPL
Daihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi
2008 — conf
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks.
NOCS
Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano
2008 — conf
Design and Implementation of Adaptive Viterbi Decoder for Using A Dynamic Reconfigurable Processor.
ReConFig
Yuken Kishimoto, Shinichiro Haruyama, Hideharu Amano
2008 — conf
Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor with Directly Interconnected PEs.
ERSA
Masaru Kato, Yohei Hasegawa, Hideharu Amano
2008 — conf
Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs.
FPT
Hirokazu Morishita, Yasunori Osana, Naoyuki Fujita, Hideharu Amano
2008 — conf
Exploring the optimal size for multicasting configuration data of dynamically reconfigurable processors.
FPT
Takuro Nakamura, Toru Sano, Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbunheng, Hideharu Amano
2008 B conf
Instruction buffer mode for multi-context Dynamically Reconfigurable Processors.
FPL
Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano
2008 — conf
Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique.
FPT
Yoshiki Saito, Tomoaki Shirai, Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami, Hideharu Amano
2008 B conf
Power reduction techniques for Dynamically Reconfigurable Processor Arrays.
FPL
Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito, Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbunheng, Hideharu Amano
2008 B conf
Practical implementation of a network-based stochastic biochemical simulation system on an FPGA.
FPL
Masato Yoshimi, Yuri Nishikawa, Yasunori Osana, Akira Funahashi, Yuichiro Shibata, Hideki Yamada, Noriko Hiroi, Hiroaki Kitano, Hideharu Amano
2008 — conf
Run-time power gating of on-chip routers using look-ahead routing.
ASP-DAC
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang
2008 — conf
Three-Dimensional Layout of On-Chip Tree-Based Networks.
ISPAN
Hiroki Matsutani, Michihiro Koibuchi, D. Frank Hsu, Hideharu Amano
2007 — ed.
2007 International Conference on Field-Programmable Technology, ICFPT 2007, Kitakyushu, Japan, December 12-14, 2007
FPT
Hideharu Amano, Andy Ye, Takeshi Ikenaga
2007 B conf
A Combining technique of rate law functions for a cost-effective reconfigurable biological simulator.
FPL
Hideki Yamada, Naoki Iwanaga, Yuichiro Shibata, Yasunori Osana, Masato Yoshimi, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Hiroaki Kitano, Kiyoshi Oguri
2007 — conf
A Framework for Implementing a Network-Based Stochastic Biochemical Simulator on an FPGA.
FPT
Masato Yoshimi, Yuri Nishikawa, Toshinori Kojima, Yasunori Osana, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Hideki Yamada, Hiroaki Kitano, Hideharu Amano
2007 B conf
A High Speed License Plate Recognition System on an FPGA.
FPL
Takamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka
2007 — conf
A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors.
FPT
Vu Manh Tuan, Hideharu Amano
2007 J jnl
A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs.
IEICE Trans. Inf. Syst.
Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2007 B conf
A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems.
FPL
Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2007 J jnl
An Effective Design of Deadlock-Free Routing Algorithms Based on 2D Turn Model for Irregular Networks.
IEEE Trans. Parallel Distributed Syst.
Akiya Jouraku, Michihiro Koibuchi, Hideharu Amano
2007 J jnl
Data Multicasting Procedure for Increasing Configuration Speed of Coarse Grain Reconfigurable Devices.
IEICE Trans. Inf. Syst.
Vasutan Tunbunheng, Masayasu Suzuki, Hideharu Amano
2007 B conf
Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays.
FPL
Yohei Hasegawa, Hideharu Amano
2007 B conf
FPGA Implementation of a Data-Driven Stochastic Biochemical Simulator with the Next Reaction Method.
FPL
Masato Yoshimi, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Yasunori Osana, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hideki Yamada, Hiroaki Kitano, Hideharu Amano
2007 Misc conf
Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot.
PDPTA
Atsushi Ohta, Yoshihiro Hamada, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo
2007 C conf
Implementation and Evaluation of a High Speed License Plate Recognition System on an FPGA.
CIT
Takamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka
2007 J jnl
Martini: A Network Interface Controller Chip for High Performance Computing with Distributed PCs.
IEEE Trans. Parallel Distributed Syst.
Konosuke Watanabe, Tomohiro Otsuka, Junichiro Tsuchiya, Hiroaki Nishi, Junji Yamamoto, Noboru Tanabe, Tomohiro Kudoh, Hideharu Amano
2007 — conf
Overwrite Configuration Technique in Multicast Configuration Scheme for Dynamically Reconfigurable Processor Arrays.
FPT
Satoshi Tsutsumi, Vasutan Tunbunheng, Yohei Hasegawa, Adepu Parimala, Takuro Nakamura, Takashi Nishimura, Hideharu Amano
2007 — conf
Performance Analysis of Multi-process Execution Model on Dynamically Reconfigurable Processor.
ERSA
Vu Manh Tuan, Yohei Hasegawa, Hideharu Amano
2007 B conf
Performance Improvement Methodology for ClearSpeed's CSX600.
ICPP
Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano
2007 — conf
Performance evaluation on low-latency communication mechanism of DIMMnet-2.
Parallel and Distributed Computing and Networks
Akira Kitamura, Yasuo Miyabe, Tomotaka Miyashiro, Noboru Tanabe, Hironori Nakajo, Hideharu Amano
2007 A conf
Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network.
IPDPS
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2007 B conf
Tightly-Coupled Multi-Layer Topologies for 3-D NoCs.
ICPP
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2006 B conf
A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors.
FPL
Hideharu Amano, Yohei Hasegawa, Shohei Abe, Kenichiro Ishikawa, Shunsuke Tsutsumi, Shunsuke Kurotaki, Takuro Nakamura, Takashi Nishimura
2006 — conf
A Parametric Study of Scalable Interconnects on FPGAs.
ERSA
Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano
2006 J jnl
A Simple Data Transfer Technique Using Local Address for Networks-on-Chips.
IEEE Trans. Parallel Distributed Syst.
Michihiro Koibuchi, Kenichiro Anjo, Yutaka Yamada, Akiya Jouraku, Hideharu Amano
2006 J jnl
A Survey on Dynamically Reconfigurable Processors.
IEICE Trans. Commun.
Hideharu Amano
2006 — conf
A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks.
PDCS
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2006 A conf
A cost-effective context memory structure for dynamically reconfigurable processors.
IPDPS
Masayasu Suzuki, Yohei Hasegawa, Vu Manh Tuan, Shohei Abe, Hideharu Amano
2006 B conf
An FPGA Implementation of High Throughput Stochastic Simulator for Large-Scale Biochemical Systems.
FPL
Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano
2006 — conf
An adaptive Viterbi decoder on the dynamically reconfigurable processor.
FPT
Shohei Abe, Yohei Hasegawa, Takao Toi, Takeshi Inuo, Hideharu Amano
2006 C conf
Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels.
ISPA
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2006 B conf
Performance Evaluation of an Fpga-Based Biochemical Simulator ReCSip.
FPL
Yasunori Osana, Masato Yoshimi, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano
2006 A conf
Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor.
IPDPS
Yohei Hasegawa, Shohei Abe, Shunsuke Kurotaki, Vu Manh Tuan, Naohiro Katsura, Takuro Nakamura, Takashi Nishimura, Hideharu Amano
2006 — conf
Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor.
ARC
Vu Manh Tuan, Yohei Hasegawa, Naohiro Katsura, Hideharu Amano
2006 B conf
Switch-tagged VLAN Routing Methodology for PC Clusters with Ethernet.
ICPP
Tomohiro Otsuka, Michihiro Koibuchi, Tomohiro Kudoh, Hideharu Amano
2005 B conf
A Framework for ODE-Based Multimodel Biochemical Simulations on an FPGA.
FPL
Yasunori Osana, Yow Iwaoka, Tomonori Fukushima, Masato Yoshimi, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano
2005 Misc conf
A Packet Forwarding Layer for DIMMnet and its Hardware Implementation.
PDPTA
Yoshihiro Hamada, Hiroaki Nishi, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo
2005 — conf
An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor.
FPT
Yohei Hasegawa, Shohei Abe, Hiroki Matsutani, Hideharu Amano, Kenichiro Anjo, Toru Awashima
2005 A conf
An FPGA-Based, Multi-model Simulation Method for Biochemical Systems.
IPDPS
Yasunori Osana, Tomonori Fukushima, Masato Yoshimi, Yow Iwaoka, Yuichiro Shibata, Hiroaki Kitano, Akira Funahashi, Noriko Hiroi, Hideharu Amano
2005 B conf
An I/O mechanism on a Dynamically Reconfigurable Processor - Which should be moved: Data or Configuration?
FPL
Hideharu Amano, Shohei Abe, Katsuaki Deguchi, Yohei Hasegawa
2005 Misc conf
Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips.
PDPTA
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2005 B conf
Efficient Scheduling of Rate Law Functions for ODE-Based Multimodel Biochemical Simulation on an FPGA.
FPL
Naoki Iwanaga, Yuichiro Shibata, Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Tomonori Fukushima, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Hiroaki Kitano, Kiyoshi Oguri
2005 C conf
Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board.
PDCAT
Akira Kitamura, Yasuo Miyabe, Tetsu Izawa, Tomotaka Miyashiro, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano, Yoshihiro Hamada, Noboru Tanabe, Hironori Nakajo
2005 — conf
Implementation and Evaluation of the Mechanisms for Low Latency Communication on DIMMnet-2.
ISHPC
Yasuo Miyabe, Akira Kitamura, Yoshihiro Hamada, Tomotaka Miyashiro, Tetsu Izawa, Noboru Tanabe, Hironori Nakajo, Hideharu Amano
2005 Misc conf
Implementation of ISIS-SimpleScalar.
PDPTA
Toshihiro Hanawa, Toshiya Minai, Yasuki Tanabe, Hideharu Amano
2005 A conf
Implementation of active direction-pass filter on dynamically reconfigurable processor.
IROS
Shunsuke Kurotaki, Noriaki Suzuki, Kazuhiro Nakadai, Hiroshi G. Okuno, Hideharu Amano
2005 — conf
Implementing core tasks of JPEG2000 Encoder on the Dynamically Reconfigurable Processor.
ARCS Workshops
Katsuaki Deguchi, Shohei Abe, Masayasu Suzuki, Kenichiro Anjo, Toru Awashima, Hideharu Amano
2005 J jnl
MMLRU Selection Function: A Simple and Efficient Output Selection Function in Adaptive Routing.
IEICE Trans. Inf. Syst.
Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano
2005 — conf
Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips.
ICPP Workshops
Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano
2005 J jnl
Path selection algorithm: the strategy for designing deterministic routing from alternative paths.
Parallel Comput.
Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano
2005 J jnl
Performance Evaluation of Deterministic Routings, Multicasts, and Topologies on RHiNET-2 Cluster.
IEEE Trans. Parallel Distributed Syst.
Michihiro Koibuchi, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano
2005 Misc conf
Performance and Cost Analysis of Time-Multiplexed Execution on the Dynamically Reconfigurable Processor.
FCCM
Hideharu Amano, Shohei Abe, Yohei Hasegawa, Katsuaki Deguchi, Masayasu Suzuki
2005 — conf
RoMultiC: Fast and Simple Configuration Data Multicasting Scheme for Coarse Grain Reconfigurable Devices.
FPT
Vasutan Tunbunheng, Masayasu Suzuki, Hideharu Amano
2005 — conf
The Design of Scalable Stochastic Biochemical Simulator on FPGA.
FPT
Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano
2005 J jnl
The performance of SNAIL-2 (a SSS-MIN connected multiprocessor with cache coherent mechanism).
Parallel Comput.
Takashi Midorikawa, Daisuke Shiraishi, Masayoshi Shigeno, Yasuki Tanabe, Toshihiro Hanawa, Hideharu Amano
2005 A conf
Time-multiplexed execution on the dynamically reconfigurable processor: a performance/cost evaluation.
FPGA
Yohei Hasegawa, Shohei Abe, Katsuaki Deguchi, Masayasu Suzuki, Hideharu Amano
2005 B conf
VLAN-Based Minimal Paths in PC Cluster with Ethernet on Mesh and Torus.
ICPP
Tomohiro Otsuka, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano
2004 — conf
A New Memory Module for Memory Intensive Applications.
PARELEC
Noboru Tanabe, Hironori Nakajo, Hirotaka Hakozaki, Masasige Nakatake, Yasunori Dohi, Hideharu Amano
2004 J jnl
An FPGA-Based Acceleration Method for Metabolic Simulation.
IEICE Trans. Inf. Syst.
Yasunori Osana, Tomonori Fukushima, Masato Yoshimi, Hideharu Amano
2004 A conf
BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-Chips.
IPDPS
Kenichiro Anjo, Yutaka Yamada, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano
2004 — conf
Design and Evaluation of a Switch Architecture for Multistage Interconnection Network with Temporary Directory.
PDCS
Masato Sumiyoshi, Takashi Midorikawa, Yasuki Tanabe, Hideharu Amano
2004 C conf
Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor Array.
EUC
Yutaka Yamada, Hideharu Amano, Michihiro Koibuchi, Akiya Jouraku, Kenichiro Anjo, Katsunobu Nishimura
2004 — conf
Future reconfigurable computing system.
ASP-DAC
Masahiko Kawamura, Hideharu Amano
2004 Misc conf
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor.
FCCM
Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Toru Awashima
2004 — conf
ReCSiP: a reconfigurable cell simulation platform: accelerating biological applications with FPGA.
ASP-DAC
Yasunori Osana, Tomonori Fukushima, Hideharu Amano
2004 B conf
Stochastic Simulation for Biochemical Reactions on FPGA.
FPL
Masato Yoshimi, Yasunori Osana, Tomonori Fukushima, Hideharu Amano
2004 — conf
Stream applications on the dynamically reconfigurable processor.
FPT
Masayasu Suzuki, Yohei Hasegawa, Yutaka Yamada, Naoto Kaneko, Katsuaki Deguchi, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takao Toi, Toru Awashima
2004 B conf
Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor - An Approach to Tough Cases.
FPL
Hideharu Amano, Takeshi Inuo, Hirokazu Kami, Taro Fujii, Masayasu Suzuki
2003 B conf
A Dynamically Adaptive Switching Fabric on a Multicontext Reconfigurable Device.
FPL
Hideharu Amano, Akiya Jouraku, Kenichiro Anjo
2003 — conf
An implementation of the Rijndael on Async-WASMII.
FPT
Yoshinori Adachi, Kenichiro Ishikawa, Satoshi Tsutsumi, Hideharu Amano
2003 B conf
Descending Layers Routing: A Deadlock-Free Deterministic Routing using Virtual Channels in System Area Networks with Irregular Topologies.
ICPP
Michihiro Koibuchi, Akiya Jouraku, Konosuke Watanabe, Hideharu Amano
2003 — ed.
High Performance Computing, 5th International Symposium, ISHPC 2003, Tokyo-Odaiba, Japan, October 20-22, 2003, Proceedings
ISHPC
Alexander V. Veidenbaum, Kazuki Joe, Hideharu Amano, Hideo Aiso
2003 B conf
Implementation of ReCSiP: A ReConfigurable Cell SImulation Platform.
FPL
Yasunori Osana, Tomonori Fukushima, Hideharu Amano
2003 — conf
MAPLE chip: a processing element for a static scheduling centric multiprocessor.
ASP-DAC
Kenta Yasufuku, Riku Ogawa, Keisuke Iwai, Hideharu Amano
2003 Misc conf
Performance Evaluation of 3-Dimensional MIN with Cache Consistency Maintenance Mechanism.
PDPTA
Yasuki Tanabe, Takashi Midorikawa, Daisuke Shiraishi, Masayoshi Shigeno, Toshihiro Hanawa, Hideharu Amano
2003 Misc conf
Performance Evaluation of Instruction Set Architecture of MBP-Light: A Distributed Memory Controller for a Large Scale Multiprocessor.
PDPTA
Noriaki Suzuki, Hideharu Amano
2003 B conf
Performance Evaluation of RHiNET-2/NI: A Network Interface for Distributed Parallel Computing Systems.
CCGRID
Konosuke Watanabe, Tomohiro Otsuka, Junichiro Tsuchiya, Hideharu Amano, Hiroshi Harada, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh
2003 C conf
Performance Evaluation of Routing Algorithms in RHiNET-2 Cluster.
CLUSTER
Michihiro Koibuchi, Konosuke Watanabe, Kenichi Kono, Akiya Jouraku, Hideharu Amano
2003 — conf
Performance Evaluation of a Prototype of RHiNET-2: A Network-based Distributed Parallel Computing System.
Applied Informatics
Tomohiro Otsuka, Konosuke Watanabe, Junichiro Tsuchiya, Hiroshi Harada, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Hideharu Amano
2003 B conf
Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device.
FPL
Toshiro Kitaoka, Hideharu Amano, Kenichiro Anjo
2002 B conf
A General Hardware Design Model for Multicontext FPGAs.
FPL
Naoto Kaneko, Hideharu Amano
2002 — conf
Low Latency Communication on DIMMnet-1 Network Interface Plugged into a DIMM Slot.
PARELEC
Noboru Tanabe, Yoshihiro Hamada, Hironori Nakajo, Hideki Imashiro, Junji Yamamoto, Tomohiro Kudoh, Hideharu Amano
2002 J jnl
Low Latency High Bandwidth Message Transfer Mechanisms for a Network Interface Plugged into a Memory Slot.
Clust. Comput.
Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano
2002 B conf
RHiNET/NI: A Reconfigurable Network Interface for Cluster Computing.
FPL
Naoyuki Izu, Tomonori Yokoyama, Junichiro Tsuchiya, Konosuke Watanabe, Hideharu Amano
2002 — conf
Routing Algorithms Based on 2D Turn Model for Irregular Networks.
ISPAN
Akiya Jouraku, Michihiro Koibuchi, Hideharu Amano, Akira Funahashi
2002 Misc conf
The Impact of Path Selection Algorithm of Adaptive Routing for Implementing Deterministic Routing.
PDPTA
Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano
2001 J jnl
A network switch for supporting high-performance parallel processing by computers distributed in local areas.
Syst. Comput. Jpn.
Hiroaki Nishi, Koji Tasho, Tomohiro Kudoh, Hideharu Amano
2001 — conf
A prototype chip of multicontext FPGA with DRAM for virtual hardware.
ASP-DAC
Daisuke Kawakami, Yuichiro Shibata, Hideharu Amano
2001 B conf
L-Turn Routing: An Adaptive Routing in Irregular Networks.
ICPP
Michihiro Koibuchi, Akira Funahashi, Akiya Jouraku, Hideharu Amano
2001 — conf
MMLRU Selection Function: An Output Selection Function on Adaptive Routing.
PDCS
Michihiro Koibuchi, Akiya Jouraku, Akira Funahashi, Hideharu Amano
2001 — conf
RHiNET-3/SW: an 80-Gbit/s high-speed network switch for distributed parallel computing.
Hot Interconnects
Shinji Nishimura, Tomohiro Kudoh, Hiroaki Nishi, Junji Yamamoto, Ryuichiro Ueno, Katsuyoshi Harasawa, Shuji Fukuda, Yasutaka Shikichi, Shigeto Akutsu, Koji Tasho, Hideharu Amano
2001 J jnl
Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers.
IEEE Trans. Parallel Distributed Syst.
Yulu Yang, Akira Funahashi, Akiya Jouraku, Hiroaki Nishi, Hideharu Amano, Toshinori Sueyoshi
2001 Misc conf
The impact of output selection function on adaptive routing.
CATA
Akira Funahashi, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano
2000 A conf
A Local Area System Network RHinet-1: A Network for High Performance Parallel Computing.
HPDC
Hiroaki Nishi, Koji Tasho, Junji Yamamoto, Tomohiro Kudoh, Hideharu Amano
2000 Misc conf
A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems.
FCCM
Ou Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano
2000 B conf
A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems.
FPL
Ou Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano
2000 Misc conf
A Virtual Hardware System on a Dynamically Reconfigurable Logic Device.
FCCM
Yuichiro Shibata, Masaki Uno, Hideharu Amano, Koichiro Furuta, Taro Fujii, Masato Motomura
2000 — conf
A floating point arithmetic unit for a static scheduling and compiler oriented multiprocessor system.
ASP-DAC
Takahiro Kawaguchi, Takayuki Suzuki, Hideharu Amano
2000 Misc conf
Coherence Protocol for Home Proxy Cache on RHiNET.
PDPTA
Hironori Nakajo, M. Ishii, T. Kudo, Hideharu Amano
2000 B conf
Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware.
FPL
Atsushi Takayama, Yuichiro Shibata, Keisuke Iwai, Hideharu Amano
2000 — conf
Environment for Multiprocessor Simulator Development.
ISPAN
Masaki Wakabayashi, Hideharu Amano
2000 C conf
MEMOnet : Network interface plugged into a memory slot.
CLUSTER
Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano
2000 — conf
On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism.
ISPAN
Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano
2000 J jnl
RHiNET-2/SW a Hight-throughput, Compact Network-switch Using 8.8-Gbit/s Optical Interconnection.
New Gener. Comput.
Shinji Nishimura, Katsuyoshi Harasawa, N. Matsudaira, Shigeto Akutsu, Tomohiro Kudoh, Hiroaki Nishi, Hideharu Amano
2000 B conf
Reconfigurable Systems: New Activities in Asia.
FPL
Hideharu Amano, Yuichiro Shibata, Masaki Uno
1999 — conf
A Routing Algorithm for DS-WDM Ring.
Applied Informatics
Xiaoshe Dong, Tomohiro Kudoh, Hideharu Amano
1999 — conf
A Torus Assignment for an Interconnection Network Recursive Diagonal Torus.
ISPAN
Qin Fan, Yulu Yang, Akira Funahashi, Hideharu Amano
1999 — conf
An Educational System of LSI Design with Free-Wares for VDEC.
MSE
Fumiharu Morisawa, Daisuke Kawakami, Kensuke Tanaka, Hideharu Amano
1999 — conf
Floating Point Arithmetic Unit for the Custom Processor Maple.
Applied Informatics
Takahiro Kawaguchi, Takashi Fujiwara, Katsuto Sakamoto, Keisuke Iwai, Hideharu Amano
1999 — conf
ISIS: Multiprocessor Simulator Library.
Applied Informatics
Masaki Wakabayashi, Keisuke Inoue, Hideharu Amano
1999 — conf
Implementation and Evaluation of the Compiler for WASMII, a Virtual Hardware System.
ICPP Workshops
Atsushi Takayama, Yuichiro Shibata, Keisuke Iwai, Hidenori Miyazaki, Koichi Higure, Xiao-ping Ling, Hideharu Amano
1999 — conf
Internal Parallelization of Data-Driven Virtual Hardware.
ICPP Workshops
Yuichiro Shibata, Xiao-ping Ling, Hideharu Amano
1999 J jnl
Performance evaluation of SNAIL: A multiprocessor based on the simple serial synchronized multistage interconnection network architecture.
Parallel Comput.
Junji Yamamoto, Takashi Fujiwara, T. Komeda, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano
1998 J jnl
An analysis of fairness and overhead in the arbitration protocol of the IEEE Futurebus standard.
Syst. Comput. Jpn.
Ou Yamamoto, Takuya Terasawa, Hideharu Amano
1998 J jnl
Design and implementation of reconfigurable sensing system for networked robots.
Adv. Robotics
Asami Miyajima, Kazumasa Nukata, Hideharu Amano, Yuichiro Anzai
1998 — conf
HOSMII: A Virtual Hardware Integrated with DRAM.
IPPS/SPDP Workshops
Yuichiro Shibata, Hidenori Miyazaki, Xiao-ping Ling, Hideharu Amano
1998 — conf
Reconfigurable Systems: Activities in Asia and South Pacific (Embedded Tutorial).
ASP-DAC
Hideharu Amano, Yuichiro Shibata
1998 — conf
The MINC (Multistage Interconnection Network with Cache Control Mechanism) Chip.
ASP-DAC
Takashi Midorikawa, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano
1997 B conf
A reconfigurable sensor-data processing system for personal robots.
FPL
Kazumasa Nukata, Yuichiro Shibata, Hideharu Amano, Yuichiro Anzai
1997 J jnl
A study on snoop cache systems for single-chip multiprocessors.
Syst. Comput. Jpn.
Takuya Terasawa, Keisuke Inoue, Hitoshi Kurosawa, Hideharu Amano
1997 — conf
Adaptive Routing on the Recursive Diagonal Torus.
ISHPC
Akira Funahashi, Toshihiro Hanawa, Hideharu Amano, Tomohiro Kudoh
1997 — conf
An LSI implementation of the simple serial synchronized multistage interconnection network.
ASP-DAC
Takayuki Kamei, Masashi Sasahara, Hideharu Amano
1997 — conf
Shared vs. Snoop: Evaluation of Cache Structure for Single-Chip Multiprocessors.
Euro-Par
Toru Kisuki, Masaki Wakabayashi, Junji Yamamoto, Keisuke Inoue, Hideharu Amano
1997 — conf
The RDT network router chip.
ASP-DAC
Hiroaki Nishi, Hideharu Amano, Katsunobu Nishimura, Kenichiro Anjo, Tomohiro Kudoh
1997 Misc conf
Total System Image of the Reconfigurable Machine WASMII.
PDPTA
Xiao-ping Ling, Yuichiro Shibata, Hidenori Miyazaki, Hideharu Amano, Koichi Higure
1997 — conf
Wavelength Division Multiple Access Ring - Virtual Topology on a Simple Ring Network.
ISPAN
Xiaoshe Dong, Tomohiro Kudoh, Hideharu Amano
1996 B conf
ATTEMPT-1: A Reconfigurable Multiprocessor Testbed.
FPL
Keisuke Inoue, Toru Kisuki, Michitaka Okuno, Etsuko Shimizu, Takuya Terasawa, Hideharu Amano
1996 B conf
An Emulation System of the WASMII: A Data Driven Computer on a Virtual Hardware.
FPL
Yuichiro Shibata, Xiao-ping Ling, Hideharu Amano
1996 — conf
Hot spot contention and message combining in the simple serial synchronized multistage interconnection network.
SPDP
Toshihiro Hanawa, Takashi Fujiwara, Hideharu Amano
1996 J jnl
Recursive Diagonal Torus (RDT): An Interconnection Network for the Massively Parallel Computers.
Syst. Comput. Jpn.
Yulu Yang, Hideharu Amano, Hidetomo Shibamura, Toshinori Sueyoshi
1995 J jnl
A Performance Evaluation of the Multiprocessor Testbed ATTEMPT-0.
Parallel Comput.
Takuya Terasawa, Ou Yamamoto, Tomohiro Kudoh, Hideharu Amano
1995 — conf
A Preprocessing System of the EULASH: An Environment for Efficient use of Multiprocessors with Local Memory.
Parallel and Distributed Computing and Systems
Junji Yamamoto, D. Hattori, Jun-ichi Yamato, T. Tokuyoshi, Y. Yamaguchi, Hideharu Amano
1995 J jnl
An analysis of the hot spot contention and message combining on the simple serial synchronized-multistage interconnection network.
Syst. Comput. Jpn.
Kalidou Gaye, Toshihiro Hanawa, Hideharu Amano
1995 — conf
Hierarchical Bit-Map Directory Schemes on the RDT Interconnection Network for a Massively Parallel Processor JUMP-1.
ICPP (1)
Tomohiro Kudoh, Hideharu Amano, Takashi Matsumoto, Kei Hiraki, Yulu Yang, Katsunobu Nishimura, Koichi Yoshimura, Yasuhito Fukushima
1995 J jnl
Neural network parallel computing for multi-layer channel routing problems.
Neurocomputing
Kyotaro Suzuki, Hideharu Amano, Yoshiyasu Takefuji
1995 J jnl
WASMII: An MPLD with data-driven control on a virtual hardware.
J. Supercomput.
Xiao-ping Ling, Hideharu Amano
1994 — conf
Message transfer algorithms on the recursive diagonal torus.
ISPAN
Yulu Yang, Hideharu Amano
1994 — conf
Multistage Interconnection Networks with Multiple Outlets.
ICPP (1)
Toshihiro Hanawa, Hideharu Amano, Yoshifumi Fujikawa
1994 — conf
Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations.
ISPAN
Kei Hiraki, Hideharu Amano, Morihiro Kuga, Toshinori Sueyoshi, Tomohiro Kudoh, Hiroshi Nakashima, Hironori Nakajo, Hideo Matsuda, Takashi Matsumoto, Shin-ichiro Mori
1994 — conf
SNAIL: A Multiprocessor Based on the Simple Serial Synchronized Multistage Interconnection Network Architecture.
ICPP (1)
Masashi Sasahara, Jun Terada, Luo Zhou, Kalidou Gaye, Jun-ichi Yamato, Satoshi Ogura, Hideharu Amano
1994 B conf
Software Environment for WASMII: a Data Driven Machine with a Virtual Hardware.
FPL
Xiao-Yu Chen, Xiao-ping Ling, Hideharu Amano
1993 J jnl
A query-based parallel logic simulation algorithm.
Syst. Comput. Jpn.
Tomohiro Kudoh, Tetsuro Kimura, Hideharu Amano, Takuya Terasawa
1993 — conf
Performance evaluation of WASMII: a data driven computer on a virtual hardware.
PARLE
Xiao-ping Ling, Hideharu Amano
1993 — conf
Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers.
SPDP
Yulu Yang, Hideharu Amano, Hidetomo Shibamura, Toshinori Sueyoshi
1992 — conf
A Parallel Logic Simulation Algorithm Based on Query.
ICPP (3)
Tomohiro Kudoh, Tetsuro Kimura, Hideharu Amano, Takuya Terasawa
1992 — conf
SSS (Simple Serial Synchronized)-MIN: A Novel Multi Stage Interconnection Architecture for Multiprocessors.
IFIP Congress (1)
Hideharu Amano, Luo Zhou, Kalidou Gaye
1991 — conf
A Batcher Double Omega Network with Combining.
ICPP (1)
Hideharu Amano, Kalidou Gaye
1991 J jnl
NCC: A concurrent description language for scientific calculation on multiprocessors.
Syst. Comput. Jpn.
Taisuke Boku, Tomohiro Kudoh, Hideharu Amano, Tetsuro Kimura
1990 J jnl
(SM)²-II: A Large-Scale Multiprocessor for Sparse Matrix Calculations.
IEEE Trans. Computers
Hideharu Amano, Taisuke Boku, Tomohiro Kudoh
1990 — conf
A Fault Tolerant Batcher Network.
ICPP (1)
Hideharu Amano
1989 — conf
A New Version of a Parallel Production System Machine, MANJI-II.
IWDM
Jun Miyazaki, Kenji Takeda, Hideharu Amano, Hideo Aiso
1989 — conf
A static scheduling system for a parallel machine (SM)
PARLE (1)
Xiao-ping Ling, Hideharu Amano
1989 — conf
Cache with Synchronization Mechanism.
IFIP Congress
Hideharu Amano, Takuya Terasawa, Tomohiro Kudoh
1988 A* conf
IMPULSE: A High Performance Processing Unit for Multiprocessors for Scientific Calculation.
ISCA
Taisuke Boku, Shigehiro Nomura, Hideharu Amano
1987 — conf
A Shared Memory Architecture for MANJI Production System Machine.
IWDM
Jun Miyazaki, Hideharu Amano, Kenji Takeda, Hideo Aiso
1986 — conf
An Adaptable Cluster Structure of (SM)²-II.
CONPAR
Chizuko Saito, Hideharu Amano, Tomohiro Kudoh, Hideo Aiso
1986 J jnl
Dynamic fault recovery in mesh-connected parallel computers.
Syst. Comput. Jpn.
Takashi Yokota, Hideharu Amano, Hideo Aiso
1985 A* conf
(SM)²-II: A New Version of the Sparse Matrix Solving Machine.
ISCA
Hideharu Amano, Taisuke Boku, Tomohiro Kudoh, Hideo Aiso
1985 J jnl
Performance analysis of parallel machines using multi-read memory.
Syst. Comput. Jpn.
Hideharu Amano, Junji Chikawa, Takaichi Yoshida, Hideo Aiso
1983 A* conf
(SM)2: Sparse Matrix Solving Machine
ISCA
Hideharu Amano, Takaichi Yoshida, Hideo Aiso