Hideaki Yamamoto

21 papers B 4C 2Journal 11Unranked 4
YearRankTypeTitle / Venue / Authors
2026 — conf
Body-scale NFC for wearables: human-centric body-scale NFC networking for ultra-low-power wearable devices (Demo of UTokyo Kawahara Lab 2025).
CHI Extended Abstracts
Hideaki Yamamoto, Yifan Li, Wakako Yukita, Tomoyuki Yokota, Takao Someya, Ryo Takahashi, Yoshihiro Kawahara
2026 J jnl
Body-scale NFC for wearables: human-centric body-scale NFC networking for ultra-low-power wearable devices (Demo of UTokyo Kawahara Lab 2025).
CoRR
Hideaki Yamamoto, Yifan Li, Wakako Yukita, Tomoyuki Yokota, Takao Someya, Ryo Takahashi, Yoshihiro Kawahara
2025 — conf
Analog CMOS Spiking Neural Network for Time-Series Signal Recognition.
ISMVL
Shigeo Sato, Satoshi Moriya, Masaya Ishikawa, Hideaki Yamamoto
2025 J jnl
Analog VLSI Implementation of Subthreshold Spiking Neural Networks and Its Application to Reservoir Computing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Satoshi Moriya, Masaya Ishikawa, Satoshi Ono, Hideaki Yamamoto, Yasushi Yuminaka, Yoshihiko Horio, Jordi Madrenas, Shigeo Sato
2025 J jnl
Directional intermodular coupling enriches functional complexity in biological neuronal networks.
Neural Networks
Nobuaki Monma, Hideaki Yamamoto, Naoya Fujiwara, Hakuba Murota, Satoshi Moriya, Ayumi Hirano-Iwata, Shigeo Sato
2025 J jnl
Efficient connectivity and intrinsic noise separation in recurrent spiking neural networks trained with e-prop.
Neuromorph. Comput. Eng.
Davide Noè, Hideaki Yamamoto, Yuichi Katori, Shigeo Sato
2025 C conf
Event-Driven Inference with Spiking Neural Networks Enhanced by Non-Volatile Analog Spin-Orbit Torque Devices.
ISCAS
Satoshi Moriya, Yosuke Iida, Aurélien Lagarrigue, K. Vihanga De Zoysa, Masaya Ishikawa, Hideaki Yamamoto, Sunsuke Fukami, Shigeo Sato
2024 B conf
Design of Mixed-Signal LSI with Analog Spiking Neural Network and Digital Inference Circuits for Reservoir Computing.
IJCNN
Satoshi Moriya, Hideaki Yamamoto, Masaya Ishikawa, Yasushi Yuminaka, Yoshihiko Horio, Jordi Madrenas, Shigeo Sato
2022 B conf
A Fully Analog CMOS Implementation of a Two-variable Spiking Neuron in the Subthreshold Region and its Network Operation.
IJCNN
Satoshi Moriya, Hideaki Yamamoto, Shigeo Sato, Yasushi Yuminaka, Yoshihiko Horio, Jordi Madrenas
2021 — conf
A Subthreshold Spiking Neuron Circuit Based on the Izhikevich Model.
ICANN (5)
Shigeo Sato, Satoshi Moriya, Yuka Kanke, Hideaki Yamamoto, Yoshihiko Horio, Yasushi Yuminaka, Jordi Madrenas
2021 J jnl
Computational Efficiency of a Modular Reservoir Network for Image Recognition.
Frontiers Comput. Neurosci.
Yifan Dai, Hideaki Yamamoto, Masao Sakuraba, Shigeo Sato
2020 J jnl
Contribution of AMPA and NMDA receptors in the spontaneous firing patterns of single neurons in autaptic culture.
Biosyst.
Kouhei Hattori, Takeshi Hayakawa, Akira Nakanishi, Mihoko Ishida, Hideaki Yamamoto, Ayumi Hirano-Iwata, Takashi Tanii
2019 B conf
Quantitative Analysis of Dynamical Complexity in Cultured Neuronal Network Models for Reservoir Computing Applications.
IJCNN
Satoshi Moriya, Hideaki Yamamoto, Ayumi Hirano-Iwata, Shigeru Kubota, Shigeo Sato
2018 J jnl
Effective Subnetwork Topology for Synchronizing Interconnected Networks of Coupled Phase Oscillators.
Frontiers Comput. Neurosci.
Hideaki Yamamoto, Shigeru Kubota, Fabio A. Shimizu, Ayumi Hirano-Iwata, Michio Niwano
2017 J jnl
Control of the Correlation of Spontaneous Neuron Activity in Biological and Noise-activated CMOS Artificial Neural Microcircuits.
CoRR
Ramin M. Hasani, Giorgio Ferrari, Hideaki Yamamoto, Sho Kono, Koji Ishihara, Soya Fujimori, Takashi Tanii, Enrico Prati
2017 B conf
Modularity-dependent modulation of synchronized bursting activity in cultured neuronal network models.
IJCNN
Satoshi Moriya, Hideaki Yamamoto, Hisanao Akima, Ayumi Hirano-Iwata, Michio Niwano, Shigeru Kubota, Shigeo Sato
2011 J jnl
A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM.
IEEE J. Solid State Circuits
Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Masatoshi Fukuda, Yasuhiro Koshio, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Hirokazu Ezawa, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Masafumi Takahashi, Yukihito Oowaki
2010 — conf
A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm.
ISSCC
Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Yukihito Oowaki
2009 J jnl
Ultra-Small Reader/Writer with Multiple Contactless Interfaces on a Flexible Circuit Board.
IEICE Trans. Commun.
Hideaki Yamamoto, Minoru Ikeda, Yasuhiro Hosoda
2000 J jnl
A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM.
IEEE J. Solid State Circuits
Masafumi Takahashi, Tsuyoshi Nishikawa, Mototsugu Hamada, Toshinari Takayanagi, Hideho Arakida, Noriaki Machida, Hideaki Yamamoto, Toshihide Fujiyoshi, Yoko Ohashi, Osamu Yamagishi, Tatsuo Samata, Atsushi Asano, Toshihiro Terazawa, Kenji Ohmori, Yoshinori Watanabe, Hiroki Nakamura, Shigenobu Minami, Tadahiro Kuroda, Tohru Furuyama
2000 C conf
A scalable MPEG-4 video codec architecture for IMT-2000 multimedia applications.
ISCAS
Masafumi Takahashi, Tsuyoshi Nishikawa, Hideho Arakida, Noriaki Machida, Hideaki Yamamoto, Toshihide Fujiyoshi, Yoko Matsumoto, Osamu Yamagishi, Tatsuo Samata, Atsushi Asano, Toshihiro Terazawa, Kenji Ohmori, Junya Shirakura, Yoshinori Watanabe, Hiroki Nakamura, Shigenobu Minami, Tohru Furuyama