Henry Selvaraj

72 papers B 1C 20Misc 2Journal 25Unranked 24

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Sensor failure mitigation in RTOS based internet of things (IoT) systems using machine learning. J. Parallel Distributed Comput. Saugat Sharma, Grzegorz Chmaj, Henry Selvaraj
2022	—	`conf`	A Novel Optimized Context-Based Deep Architecture for Scene Parsing. ICONIP (6) Ranju Mandal, Brijesh K. Verma, Basim Azam, Henry Selvaraj
2017	C	`ed.`	25th International Conference on Systems Engineering, ICSEng 2017, Las Vegas, NV, USA, August 22-24, 2017 ICSEng Henry Selvaraj, Grzegorz Chmaj, Dawid Zydek
2017	C	`conf`	Analog and Mixed-Signal Verification Using Satisfiability Solver on Discretized Models. ICSEng Henry Selvaraj, Nikita Ramesh Wanjale
2017	C	`conf`	FPGA Implementation for Epileptic Seizure Detection Using Amplitude and Frequency Analysis of EEG Signals. ICSEng D. Selvathi, Henry Selvaraj
2017	C	`conf`	Improved Genetic Algorithm for Finite-Horizon Optimal Control of Nonlinear Systems. ICSEng Ahmed Khamis, Dawid Zydek, Henry Selvaraj
2017	C	`conf`	Interconnection Networks Efficiency in System-on-Chip Distributed Computing System: Concentrated Mesh and Fat Tree. ICSEng Grzegorz Chmaj, Henry Selvaraj
2016	J	`jnl`	Energy-Efficient Computing Solutions for Internet of Things with ZigBee Reconfigurable Devices. Int. J. Softw. Innov. Grzegorz Chmaj, Henry Selvaraj
2015	—	`conf`	Concentrated mesh and fat tree usage efficiency in System-on-Chip based multiprocessor distributed processing architectures. MECO Grzegorz Chmaj, Henry Selvaraj
2015	C	`conf`	Energy-efficient distributed computing solutions for Internet of Things with ZigBee devices. ICIS Grzegorz Chmaj, Henry Selvaraj
2015	J	`jnl`	FPGA Implementation of Fuzzy Inference System Based Edge Detection Algorithm. Int. J. Comput. Intell. Appl. D. Selvathi, Henry Selvaraj, J. Dharani
2015	C	`ed.`	Progress in Systems Engineering - Proceedings of the Twenty-Third International Conference on Systems Engineering, ICSEng 2014, Las Vegas, NV, USA, August 19-21, 2014. ICSEng Henry Selvaraj, Dawid Zydek, Grzegorz Chmaj
2014	C	`conf`	A Survey on Design and Implementation of Floating Point Adder in FPGA. ICSEng Luka Daoud, Dawid Zydek, Henry Selvaraj
2014	C	`conf`	Distributed Processing Applications for UAV/drones: A Survey. ICSEng Grzegorz Chmaj, Henry Selvaraj
2014	C	`conf`	UAV Cooperative Data Processing Using Distributed Computing Platform. ICSEng Grzegorz Chmaj, Henry Selvaraj
2013	—	`conf`	A Survey of High Level Synthesis Languages, Tools, and Compilers for Reconfigurable High Performance Computing. ICSS Luka Daoud, Dawid Zydek, Henry Selvaraj
2013	—	`conf`	Fast FPGA-based fault injection tool for embedded processors. ISQED Mohammad Shokrolah Shirazi, Brendan Morris, Henry Selvaraj
2013	—	`conf`	Matrix Multiplication in Multiphysics Systems Using CUDA. ICSS Dawid Krol, Dawid Zydek, Henry Selvaraj
2013	—	`conf`	Tracker-Node Model for Energy Consumption in Reconfigurable Processing Systems. ICSS Grzegorz Chmaj, Henry Selvaraj, Laxmi P. Gewali
2012	C	`conf`	Accelerating High Performance Computing Applications: Using CPUs, GPUs, Hybrid CPU/GPU, and FPGAs. PDCAT Bin Liu, Dawid Zydek, Henry Selvaraj, Laxmi P. Gewali
2012	—	`conf`	Overlay-NoC and H-Phy based computing using modern Chip Multiprocessors. EIT Grzegorz Chmaj, Dawid Zydek, Yehia Zakarya Elhalwagy, Henry Selvaraj
2011	C	`ed.`	21st International Conference on Systems Engineering (ICSEng 2011), Las Vegas, NV, USA, Aug. 16-18, 2011 ICSEng Henry Selvaraj, Dawid Zydek
2011	C	`conf`	Ear-Slicing and Quality Triangulation. ICSEng Bartosz Kajak, Laxmi P. Gewali, Henry Selvaraj
2011	J	`jnl`	Energy characteristic of a processor allocator and a network-on-chip. Int. J. Appl. Math. Comput. Sci. Dawid Zydek, Henry Selvaraj, Grzegorz Borowik, Tadeusz Luba
2011	C	`conf`	Extended Analysis of Resource Assignment in Modern Chip Multiprocessors. ICSEng Dawid Zydek, Grzegorz Chmaj, Henry Selvaraj
2011	J	`jnl`	Fast and efficient processor allocation algorithm for torus-based chip multiprocessors. Comput. Electr. Eng. Dawid Zydek, Henry Selvaraj
2011	J	`jnl`	Supervised Classification of White Blood Cells by Fusion of Color Texture Features and Neural Network. Int. J. Comput. Intell. Appl. G. Wiselin Jiji, Henry Selvaraj, G. Evelin Suji
2010	J	`jnl`	Hardware implementation of processor allocation schemes for mesh-based chip multiprocessors. Microprocess. Microsystems Dawid Zydek, Henry Selvaraj
2010	J	`jnl`	Hybrid Approach for Brain Tumor Segmentation in Magnetic Resonance Images Using Cellular Neural Networks and Optimization Techniques. Int. J. Comput. Intell. Appl. D. Selvathi, Henry Selvaraj, S. Thamarai Selvi
2010	—	`conf`	Synthesis of Processor Allocator for Torus-Based Chip MultiProcessors. ITNG Dawid Zydek, Henry Selvaraj, Laxmi P. Gewali
2009	J	`jnl`	Constrained Disjoint Paths in Geometric Networks. Int. J. Comput. Intell. Appl. Laxmi P. Gewali, Dan Mazzella, Henry Selvaraj
2009	J	`jnl`	Editorial: Applications of Computational Intelligence. Int. J. Comput. Intell. Appl. Henry Selvaraj, S. Arivazhagan
2009	—	`conf`	Processor Allocation Problem for NoC-Based Chip Multiprocessors. ITNG Dawid Zydek, Henry Selvaraj
2008	J	`jnl`	Iteration-Free Fractal Coding for Image Compression Using Genetic Algorithm. Int. J. Comput. Intell. Appl. A. R. Nadira Banu Kamal, S. Thamarai Selvi, Henry Selvaraj
2007	J	`jnl`	An efficient variable partitioning approach for functional decomposition of circuits. J. Syst. Archit. Venkatesan Muthukumar, Robert J. Bignall, Henry Selvaraj
2007	—	`conf`	Interference Aware Routing in Sensor Network. ITNG Min Tun, Laxmi P. Gewali, Henry Selvaraj
2007	J	`jnl`	Placement-Directed Behavioral Synthesis Scheme for Simultaneous Scheduling Binding and Partitioning with Resources Operating at Multiple Voltages. Int. J. Comput. Their Appl. Dongxin Wen, Ling Wang, Yingtao Jiang, Henry Selvaraj, Xiao-Zong Yang
2007	J	`jnl`	Scheduling and optimal voltage selection with multiple supply voltages under resource constraints. Integr. Ling Wang, Yingtao Jiang, Henry Selvaraj
2006	J	`jnl`	Abnormality Detection in Brain MR Images Using Minimum Error Thresholding Method. Int. J. Comput. Intell. Appl. D. Selvathi, S. Thamarai Selvi, Henry Selvaraj
2006	J	`jnl`	Functional Decomposition - the Value and Implication for Both Neural Networks and Digital Designing. Int. J. Comput. Intell. Appl. Henry Selvaraj, Piotr Sapiecha, Mariusz Rawski, Tadeusz Luba
2006	J	`jnl`	Multilevel Synthesis of Finite State Machines Based on Symbolic Functional Decomposition. Int. J. Comput. Intell. Appl. Mariusz Rawski, Henry Selvaraj, Tadeusz Luba, Piotr Szotkowski
2006	J	`jnl`	Scheduling and Partitioning Schemes for Low Power Designs Using Multiple Supply Voltages. J. Supercomput. Ling Wang, Yingtao Jiang, Henry Selvaraj
2006	J	`jnl`	Support Vector Machine Based Automatic Classification of Human Brain Using MR Image Features. Int. J. Comput. Intell. Appl. Henry Selvaraj, S. Thamarai Selvi, D. Selvathi, R. Ramkumar
2005	J	`jnl`	An application of functional decomposition in ROM-based FSM implementation in FPGA devices. J. Syst. Archit. Mariusz Rawski, Henry Selvaraj, Tadeusz Luba
2005	—	`conf`	Efficient Application of Modern Logic Synthesis in FPGA-Based Designing of Information and Signal Processing Systems. ITCC (2) Henry Selvaraj, Pawel Tomaszewicz, Mariusz Rawski, Tadeusz Luba
2005	C	`conf`	Efficient Implementation of Digital Filters with Use of Advanced Synthesis Methods Targeted FPGA Architectures. DSD Mariusz Rawski, Pawel Tomaszewicz, Henry Selvaraj, Tadeusz Luba
2005	J	`jnl`	Multiple voltage and frequency scheduling for power minimization. J. Syst. Archit. Venkatesan Muthukumar, Bharath Radhakrishnan, Henry Selvaraj
2005	J	`jnl`	Multiple voltage synthesis scheme for low power design under timing and resource constraints. Integr. Comput. Aided Eng. Ling Wang, Yingtao Jiang, Henry Selvaraj
2005	J	`jnl`	Reconfigurable embedded systems: Synthesis, design and application. J. Syst. Archit. Henry Selvaraj, Lech Józwiak
2004	—	`conf`	A Hybrid Approach to a Classification Problem. Intelligent Information Systems Piotr Sapiecha, Henry Selvaraj, Jaroslaw Tomasz Stanczak, Krzysztof Sep, Tadeusz Luba
2004	C	`conf`	Efficient Method of Input Variable Partitioning in Functional Decomposition Based on Evolutionary Algorithms. DSD Mariusz Rawski, Henry Selvaraj, Pawel Morawiecki
2004	C	`conf`	Hybrid Greedy/Face Routing for Ad-Hoc Sensor Network. DSD Jianhong Li, Laxmi P. Gewali, Henry Selvaraj, Muthukumar Venkatesan
2004	—	`conf`	Synthesis Scheme for Low Power Designs with Multiple Supply Voltages by Heuristic Algorithms. ITCC (2) Ling Wang, Yingtao Jiang, Henry Selvaraj
2004	—	`conf`	Synthesis scheme for low power designs with multiple supply voltages by tabu search. ISCAS (5) Ling Wang, Yingtao Jiang, Henry Selvaraj
2003	C	`conf`	A Scheduling and Partitioning Scheme for Low Power Circuit Operating at Multiple Voltages. DSD Ling Wang, Henry Selvaraj
2003	C	`conf`	An Application of Functional Decomposition in ROM-Based FSM Implementation in FPGA Devices. DSD Mariusz Rawski, Henry Selvaraj, Tadeusz Luba
2003	Misc	`conf`	Comparison of Heuristic Algorithms for Variable Partitioning in Circuit Implementation. VLSI Design Muthukumar Venkatesan, Henry Selvaraj
2003	C	`conf`	NOAH, a tool for argument reduction, serial and parallel decomposition of decision tables. DSD Michal Pleban, Hubert Niewiadomski, Piotr Buciak, Henry Selvaraj, Piotr Sapiecha, Tadeusz Luba
2003	—	`conf`	Scheduling and Optimal Voltage Selection with Multiple Supply Voltages under Resource Constraints. VLSI Ling Wang, Yingtao Jiang, Henry Selvaraj
2002	—	`conf`	FSM Implementation in Embedded Memory Blocks of Programmable Logic Devices Using Functional Decomposition. ITCC Henry Selvaraj, Mariusz Rawski, Tadeusz Luba
2002	—	`conf`	Performance Driven Circuit Clustering and Partitioning. ITCC Ling Wang, Henry Selvaraj
2001	—	`conf`	A variable partition approach for disjoint decomposition. ISCAS (5) Muthukumar Venkatesan, Robert J. Bignall, Henry Selvaraj
2001	J	`jnl`	Functional Decomposition and Its Applications in Machine Learning and Neural Networks. Int. J. Comput. Intell. Appl. Henry Selvaraj, Piotr Sapiecha, Tadeusz Luba
2000	—	`conf`	A Parameter to Measure the Efficiency of FPGA Based Logic Synthesis Tools. EUROMICRO Henry Selvaraj, B. Li
2000	—	`conf`	An Improved Column Compatibility Approach for Partition Based Functional Decomposition. EUROMICRO Muthukumar Venkatesan, Robert J. Bignall, Henry Selvaraj
2000	—	`conf`	An Input-Output Encoding Approach for Serial Decomposition. SBCCI Venkatesan Muthukumar, Robert J. Bignall, Henry Selvaraj
2000	—	`conf`	Decomposition of Boolean Relations and Functions in Logic Synthesis and Data Analysis. Rough Sets and Current Trends in Computing Piotr Sapiecha, Henry Selvaraj, Michal Pleban
1999	B	`conf`	Content based image retrieval using a neuro-fuzzy technique. IJCNN S. Kulkami, Brijesh K. Verma, P. Sharma, Henry Selvaraj
1998	—	`conf`	A Reconfiguarable Printed Character Recognition System Using a Logic Synthesis Tool. EUROMICRO Henry Selvaraj, Muthukumar Venkatesan
1998	Misc	`conf`	Decomposition Strategies and their Performance in Fpga-Based Technology Mapping. VLSI Design Henry Selvaraj, Miroslawa Nowicka, Tadeusz Luba
1995	J	`jnl`	A General Approach to Boolean Function Decomposition and its Application in FPGABased Synthesis. VLSI Design Tadeusz Luba, Henry Selvaraj
1995	—	`conf`	A balanced multilevel decomposition method. ED&TC Henry Selvaraj, Tadeusz Luba