Henry Park

18 papers C 1Journal 7Unranked 10
YearRankTypeTitle / Venue / Authors
2025 — conf
7.1 A 212.5Gb/s DSP-Based PAM-4 Transceiver with 50dB Loss Compensation for Large AI System Interconnects in 4nm FinFET.
ISSCC
Ehung Chen, Henry Park, Mohammed Abdullatif, Miguel Gandara, Ahmed ElShater, Amr Khashaba, Shih-Hao Huang, Tsz-Bin Liu, Atharav Atharav, Joonyeong Lee, Qaiser Nehal, Mohamed Megahed, Yusang Chun, Cheng-En Shieh, Vidhan Jolly, SoonWon Kwon, Hsin-Ta Chien, Ke-Chung Wu, Cheng-En Liu, Peng Yan, Po-Jui Li, Chun-Han Chen, Tzu-Shun Lin, Pei-Chieh Liu, Tamer A. Ali
2025 — conf
7.4 A 112Gb/s DSP-Based PAM-4 Receiver with an LC-Resonator-Based CTLE for >52dB Loss Compensation in 4nm FinFET.
ISSCC
Henry Park, Qaiser Nehal, Miguel Gandara, Atharav Atharav, Joonyeong Lee, Jengfeng Li, Tamer Ali
2023 — conf
A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET.
ISSCC
Henry Park, Mohammed Abdullatif, Ehung Chen, Ahmed Elmallah, Qaiser Nehal, Miguel Gandara, Tsz-Bin Liu, Amr Khashaba, Joonyeong Lee, Chih-Yi Kuan, Dhinessh Ramachandran, Ruey-Bo Sun, Atharav Atharav, Yusang Chun, Mantian Zhang, Deng-Fu Weng, Chung-Hsien Tsai, Chen-Hao Chang, Chia-Sheng Peng, Sheng-Tsung Hsu, Tamer A. Ali
2021 — conf
56/112Gbps Wireline Transceivers for Next Generation Data Centers on 7nm FINFET CMOS Technology.
CICC
Tamer A. Ali, Mohammed Abdullatif, Henry Park, Ehung Chen, Ramy Awad, Miguel Gandara
2020 — conf
6.2 A 460mW 112Gb/s DSP-Based Transceiver with 38dB Loss Compensation for Next-Generation Data Centers in 7nm FinFET Technology.
ISSCC
Tamer A. Ali, Ehung Chen, Henry Park, Ramy Yousry, Yu-Ming Ying, Mohammed Abdullatif, Miguel Gandara, Chun-Cheng Liu, Po-Shuan Weng, Huan-Sheng Chen, Mohammad Elbadry, Qaiser Nehal, Kun-Hung Tsai, Kevin Tan, Yi-Chieh Huang, Chung-Hsien Tsai, Yuyun Chang, Yuan-Hao Tung
2019 — conf
A 180mW 56Gb/s DSP-Based Transceiver for High Density IOs in Data Center Switches in 7nm FinFET Technology.
ISSCC
Tamer A. Ali, Ramy Yousry, Henry Park, Ehung Chen, Po-Shuan Weng, Yi-Chieh Huang, Chun-Cheng Liu, Chien-Hua Wu, Shih-Hao Huang, Chungshi Lin, Ke-Chung Wu, Kun-Hung Tsai, Kai-Wen Tan, Ahmed ElShater, Kuang-Ren Chen, Wei-Hao Tsai, Huan-Sheng Chen, Weiyu Leng, Mazen Soliman
2019 J jnl
Male Adolescents' and Young Adults' Evaluations of Interracial Exclusion in Offline and Online Settings.
Cyberpsychology Behav. Soc. Netw.
Henry Park, Seçil Gönültas, Kelly Lynn Mulvey, Melanie Killen, Martin D. Ruck
2016 — conf
A 125 mW 8.5-11.5 Gb/s serial link transceiver with a dual path 6-bit ADC/5-tap DFE receiver and a 4-tap FFE transmitter in 28 nm CMOS.
VLSI Circuits
Bharath Raghavan, Aida Varzaghani, Lakshmi P. Rao, Henry Park, Xiaochen Yang, Zhi Huang, Yu Chen, Rama Kattamuri, Chunhui Wu, Bo Zhang, Jun Cao, Afshin Momtaz, Namik Kocaman
2016 J jnl
A 3.8 mW/Gbps Quad-Channel 8.5-13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS.
IEEE J. Solid State Circuits
Namik Kocaman, Tamer A. Ali, Lakshmi P. Rao, Ullas Singh, Mohammed M. Abdul-Latif, Yang Liu, Amr Amin Hafez, Henry Park, Anand Vasani, Zhi Huang, Arvindh Iyer, Bo Zhang, Afshin Momtaz
2015 — conf
A 3.8 mW/Gbps quad-channel 8.5-13 Gbps serial link with a 5-tap DFE and a 4-tap transmit FFE in 28 nm CMOS.
VLSIC
Tamer A. Ali, Lakshmi P. Rao, Ullas Singh, Mohammed M. Abdul-Latif, Yang Liu, Amr Amin Hafez, Henry Park, Anand Vasani, Zhi Huang, Arvindh Iyer, Bo Zhang, Afshin Momtaz, Namik Kocaman
2014 J jnl
Stability Estimation of a 6T-SRAM Cell Using a Nonlinear Regression.
IEEE Trans. Very Large Scale Integr. Syst.
Henry Park, Chih-Kong Ken Yang
2013 C conf
A digitally-calibrated 10GS/s reconfigurable flash ADC in 65-nm CMOS.
ISCAS
Ramy Yousry, Henry Park, E-Hung Chen, Chih-Kong Ken Yang
2013 J jnl
An INL Yield Model of the Digital-to-Analog Converter.
IEEE Trans. Circuits Syst. I Regul. Pap.
Henry Park, Chih-Kong Ken Yang
2013 J jnl
In Situ SRAM Static Stability Estimation in 65-nm CMOS.
IEEE J. Solid State Circuits
Henry Park, Chih-Kong Ken Yang
2013 J jnl
Reference Calibration of Body-Voltage Sensing Circuit for High-Speed STT-RAMs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Fengbo Ren, Henry Park, Chih-Kong Ken Yang, Dejan Markovic
2012 — conf
A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs).
ISQED
Fengbo Ren, Henry Park, Richard Dorrance, Yuta Toriyama, Chih-Kong Ken Yang, Dejan Markovic
2012 J jnl
Nearly Exact Analytical Formulation of the DNL Yield of the Digital-to-Analog Converter.
IEEE Trans. Circuits Syst. II Express Briefs
Henry Park, Chih-Kong Ken Yang
2011 — conf
Analysis of STT-RAM cell design with multiple MTJs per access.
NANOARCH
Henry Park, Richard Dorrance, Amr Amin Hafez, Fengbo Ren, Dejan Markovic, Chih-Kong Ken Yang