Henrik Hulgaard

26 papers A* 2A 4B 2C 1Journal 11Unranked 6
YearRankTypeTitle / Venue / Authors
2003 J jnl
Satisfiability checking using Boolean Expression Diagrams.
Int. J. Softw. Tools Technol. Transf.
Poul Frederick Williams, Henrik Reif Andersen, Henrik Hulgaard
2002 J jnl
Boolean Expression Diagrams.
Inf. Comput.
Henrik Reif Andersen, Henrik Hulgaard
2002 J jnl
Symbolic model checking of timed guarded commands using difference decision diagrams.
J. Log. Algebraic Methods Program.
Jesper B. Møller, Henrik Hulgaard, Henrik Reif Andersen
2002 — conf
Timed Verification of Asynchronous Circuits.
Concurrency and Hardware Design
Jesper B. Møller, Henrik Hulgaard, Henrik Reif Andersen
2002 J jnl
Verification of Hierarchical State/Event Systems using Reusability and Compositionality.
Formal Methods Syst. Des.
Gerd Behrmann, Kim Guldstrand Larsen, Henrik Reif Andersen, Henrik Hulgaard, Jørn Lind-Nielsen
2001 A conf
Satisfiability Checking Using Boolean Expression Diagrams.
TACAS
Poul Frederick Williams, Henrik Reif Andersen, Henrik Hulgaard
2001 J jnl
Verification of Large State/Event Systems Using Compositionality and Dependency Analysis.
Formal Methods Syst. Des.
Jørn Lind-Nielsen, Henrik Reif Andersen, Henrik Hulgaard, Gerd Behrmann, Kåre J. Kristoffersen, Kim Guldstrand Larsen
2000 J jnl
Practical Verification of Embedded Software.
Computer
Jørgen Staunstrup, Henrik Reif Andersen, Henrik Hulgaard, Jørn Lind-Nielsen, Kim Guldstrand Larsen, Gerd Behrmann, Kåre J. Kristoffersen, Arne Skou, Henrik Leerberg, Niels Bo Theilgaard
2000 J jnl
Symbolic timing analysis of asynchronous systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Henrik Hulgaard, Tod Amon
1999 B conf
Difference Decision Diagrams.
CSL
Jesper B. Møller, Jakob Lichtenberg, Henrik Reif Andersen, Henrik Hulgaard
1999 J jnl
Equivalence checking of combinational circuits using Boolean expression diagrams.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Henrik Hulgaard, Poul Frederick Williams, Henrik Reif Andersen
1999 — conf
Equivalence checking of hierarchical combinational circuits.
ICECS
Poul Frederick Williams, Henrik Hulgaard, Henrik Reif Andersen
1999 — conf
Fully Symbolic Model Checking of Timed Systems using Difference Decision Diagrams.
SMC@FLoC
Jesper B. Møller, Jakob Lichtenberg, Henrik Reif Andersen, Henrik Hulgaard
1999 — conf
Symbolic Time Separation of Events.
ASYNC
Tod Amon, Henrik Hulgaard
1999 A conf
Verification of Hierarchical State/Event Systems Using Reusability and Compositionality.
TACAS
Gerd Behrmann, Kim Guldstrand Larsen, Henrik Reif Andersen, Henrik Hulgaard, Jørn Lind-Nielsen
1998 B conf
Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints.
FMCAD
Fen Jin, Henrik Hulgaard, Eduard Cerny
1998 A conf
Verification of Large State/Event Systems Using Compositionality and Dependency Analysis.
TACAS
Jørn Lind-Nielsen, Henrik Reif Andersen, Gerd Behrmann, Henrik Hulgaard, Kåre J. Kristoffersen, Kim Guldstrand Larsen
1997 A* conf
Boolean Expression Diagrams (Extended Abstract).
LICS
Henrik Reif Andersen, Henrik Hulgaard
1997 J jnl
Bounded Delay Timing Analysis of a Class of CSP Programs.
Formal Methods Syst. Des.
Henrik Hulgaard, Steven M. Burns
1995 J jnl
An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems.
IEEE Trans. Computers
Henrik Hulgaard, Steven M. Burns, Tod Amon, Gaetano Borriello
1995 A* conf
Efficient Timing Analysis of a Class of Petri Nets.
CAV
Henrik Hulgaard, Steven M. Burns
1995 J jnl
Testing asynchronous circuits: A survey.
Integr.
Henrik Hulgaard, Steven M. Burns, Gaetano Borriello
1994 — conf
Bounded delay timing analysis of a class of CSP programs with choice.
ASYNC
Henrik Hulgaard, Steven M. Burns
1993 C conf
An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems.
ICCD
Tod Amon, Henrik Hulgaard, Steven M. Burns, Gaetano Borriello
1993 A conf
Practical applications of an efficient time separation of events algorithm.
ICCAD
Henrik Hulgaard, Steven M. Burns, Tod Amon, Gaetano Borriello
1991 — conf
Synthesizing Delay Insensitive Circuits from Verified Programs.
Research Directions in High-Level Parallel Programming Languages
Henrik Hulgaard, Per H. Christensen, Jørgen Staunstrup