Heng Zhang

11 papers Journal 3Unranked 8
YearRankTypeTitle / Venue / Authors
2025 J jnl
An 800GbE PAM-4 PHY Transceiver for 42 dB Copper and Direct-Drive Optical Applications in 7 nm.
IEEE Solid State Circuits Lett.
Chang Liu, Burak Catli, Yong Liu, Anand Vasani, Guansheng Li, Kun Chuai, Lakshmi P. Rao, Yang Liu, Xin Meng, Jiawen Zhang, Tim He, Batu Dayanik, Vadim Milirud, Meisam Honarvar Nazari, Hyo Gyuem Rhew, Derui Kong, Arvindh Iyer, Nan Wang, Alireza Nilchi, Aminghasem Safarian, Ray Wang, Hyung-Joon Jeon, Xiaochen Yang, Boyu Hu, Jerry Han, Adesh Garg, Kumar Thasari, Heng Zhang, Namik Kocaman, Ali Nazemi, Delong Cui, Afshin Momtaz, Jun Cao
2025 — conf
An 800GbE PAM-4 PHY Transceiver that Supports 42dB Copper and Direct-Drive Optical Applications in 7nm.
CICC
Chang Liu, Burak Çatli, Yong Liu, Anand Vasani, Guansheng Li, Kun Chuai, Lakshmi P. Rao, Yang Liu, Xin Meng, Jiawen Zhang, Tim He, Batu Dayanik, Vadim Milirud, Meisam Honarvar Nazari, Hyo Gyuem Rhew, Derui Kong, Arvindh Iyer, Nan Wang, Alireza Nilchi, Aminghasem Safarian, Ray Wang, Hyung-Joon Jeon, Alex Yang, Boyu Hu, Jerry Han, Adesh Garg, Kumar Thasari, Heng Zhang, Namik Kocaman, Ali Nazemi, Delong Cui, Afshin Momtaz, Jun Cao
2024 — conf
18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS.
ISSCC
Guansheng Li, Adesh Garg, Tim He, Ullas Singh, Jiawen Zhang, Lakshmi P. Rao, Chang Liu, Meisam Honarvar Nazari, Yang Liu, Yong Liu, Heng Zhang, Tamer A. Ali, Hyo Gyuem Rhew, Jiayoon Ru, Delong Cui, Ali Nazemi, Bo Zhang, Afshin Momtaz, Jun Cao
2022 — conf
An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology.
ISSCC
Namik Kocaman, Ullas Singh, Bharath Raghavan, Arvindh Iyer, Kumar Thasari, Saurabh Surana, Jun Won Jung, Jaehun Jeong, Heng Zhang, Anand Vasani, Yonghyun Shim, Zhi Huang, Adesh Garg, Hsiang-bin Lee, Bo Wu, Feifei Liu, Ray Wang, Matthew Loh, Alex Wang, Mario Caresosa, Bo Zhang, Afshin Momtaz
2017 — conf
29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS.
ISSCC
Jun Cao, Delong Cui, Ali Nazemi, Tim He, Guansheng Li, Burak Çatli, Mehdi Khanpour, Kangmin Hu, Tamer A. Ali, Heng Zhang, Hairong Yu, Ben Rhew, Shiwei Sheng, Yonghyun Shim, Bo Zhang, Afshin Momtaz
2016 — conf
3.2 A 320mW 32Gb/s 8b ADC-based PAM-4 analog front-end with programmable gain control and analog peaking in 28nm CMOS.
ISSCC
Delong Cui, Heng Zhang, Nick Huang, Ali Nazemi, Burak Çatli, Hyo Gyuem Rhew, Bo Zhang, Afshin Momtaz, Jun Cao
2015 J jnl
A 40 nm CMOS 195 mW/55 mW Dual-Path Receiver AFE for Multi-Standard 8.5-11.5 Gb/s Serial Links.
IEEE J. Solid State Circuits
Bo Zhang, Ali Nazemi, Adesh Garg, Namik Kocaman, Mahmoud Reza Ahmadi, Mehdi Khanpour, Heng Zhang, Jun Cao, Afshin Momtaz
2014 — conf
2.2 A 780mW 4×28Gb/s transceiver for 100GbE gearbox PHY in 40nm CMOS.
ISSCC
Ullas Singh, Adesh Garg, Bharath Raghavan, Nick Huang, Heng Zhang, Zhi Huang, Afshin Momtaz, Jun Cao
2014 — conf
A 23mW/lane 1.2-6.8Gb/s multi-standard transceiver in 28nm CMOS.
A-SSCC
Seong-Ho Lee, Duke Tran, Tamer A. Ali, Burak Çatli, Heng Zhang, Wei Zhang, Mohammed M. Abdul-Latif, Zhi Huang, Guansheng Li, Mahmoud Reza Ahmadi, Afshin Momtaz
2014 J jnl
A 780 mW 4 × 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS.
IEEE J. Solid State Circuits
Ullas Singh, Adesh Garg, Bharath Raghavan, Nick Huang, Heng Zhang, Zhi Chao Huang, Afshin Momtaz, Jun Cao
2013 — conf
A 195mW / 55mW dual-path receiver AFE for multistandard 8.5-to-11.5 Gb/s serial links in 40nm CMOS.
ISSCC
Bo Zhang, Ali Nazemi, Adesh Garg, Namik Kocaman, Mahmoud Reza Ahmadi, Mehdi Khanpour, Heng Zhang, Jun Cao, Afshin Momtaz