Hemangee K. Kapoor

125 papers A* 3A 4B 3C 9Misc 22Journal 41Unranked 43

Year	Rank	Type	Title / Venue / Authors
2025	Misc	`conf`	ABMF: Adaptive Bonsai Merkle Forests for Efficient Integrity Verification in Secure Persistent Memories. VLSID Hemangee K. Kapoor, Kartikay Bhardwaj
2025	Misc	`conf`	E-DOSA: Efficient Dataflow for Optimising SNN Acceleration. VLSID Hemangee K. Kapoor, Imlijungla Longchar, Binayak Behera
2025	Misc	`conf`	Optimizing Bandwidth Utilization Through Word Based Compression in Main Memories. VLSID N. S. Aswathy, Harsh Verma, Hemangee K. Kapoor
2025	Misc	`conf`	PAF-Enc: Position Affine Encoding to Reduce Bit-Flips in Non-Volatile Main Memories. VLSID Swati Upadhyay, Hemangee K. Kapoor
2025	J	`jnl`	WEnSIBR: Compression using dynamic bases supported with encoding and zone wise wear leveling for NVMs. J. Syst. Archit. Swati Upadhyay, Arijit Nath, Hemangee K. Kapoor
2024	J	`jnl`	AmLuCEP: Amalgamating LUT-based Compression and Adaptive Encoding Assisted Block Placement To Improve Lifetime of PCM-based Main Memories. ACM Trans. Design Autom. Electr. Syst. Arijit Nath, Hemangee K. Kapoor
2024	Misc	`conf`	Bit-Beading: Stringing bit-level MAC results for Accelerating Neural Networks. VLSID Zeeshan Anwar, Imlijungla Longchar, Hemangee K. Kapoor
2024	C	`conf`	DynaCache: A Checkpoint Aware Reconfigurable Cache for Intermittently Powered Computing Systems. VLSI-SoC Rishabh Mahanta, Hemangee K. Kapoor
2024	J	`jnl`	Increasing Diversity, Equity, and Inclusion Awareness: An Example from India. Commun. ACM Hemangee K. Kapoor, David A. Patterson
2024	J	`jnl`	Migration-aware slot-based memory request scheduler to guarantee QoS in DRAM-PCM hybrid memories. J. Syst. Archit. N. S. Aswathy, Hemangee K. Kapoor
2024	C	`conf`	Opportunistic Migration for Hybrid Memories While Mitigating Aging Effects. ICCD N. S. Aswathy, Hemangee K. Kapoor
2024	—	`conf`	Write Intensity based Foresightful Page Migration for Hybrid memories. ISQED N. S. Aswathy, Hemangee K. Kapoor
2023	—	`conf`	A Leap of Confidence: A Write-Intensity Aware Prudent Page Migration for Hybrid Memories. VLSI-SoC (Selected Papers) N. S. Aswathy, Aishwarya Gupta, Hemangee K. Kapoor
2023	J	`jnl`	A Predictable QoS-aware Memory Request Scheduler for Soft Real-time Systems. ACM Trans. Embed. Comput. Syst. N. S. Aswathy, Arnab Sarkar, Hemangee K. Kapoor
2023	C	`conf`	ADaMaT: Towards an Adaptive Dataflow for Maximising Throughput in Neural Network Inference. VLSI-SoC Imlijungla Longchar, Hemangee K. Kapoor
2023	—	`conf`	AGRAS: Aging and memory request rate aware scheduler for PCM memories. ISQED N. S. Aswathy, Hemangee K. Kapoor
2023	J	`jnl`	ALAMNI: Adaptive LookAside Memory Based Near-Memory Inference Engine for Eliminating Multiplications in Real-Time. IEEE Trans. Computers Palash Das, Shashank Sharma, Hemangee K. Kapoor
2023	J	`jnl`	Adaptive distribution of control messages for improving bandwidth utilization in multiple NoC. J. Supercomput. Sonal Yadav, Vijay Laxmi, Hemangee K. Kapoor, Manoj Singh Gaur, Amit Kumar
2023	J	`jnl`	CADEN: Compression-Assisted Adaptive Encoding to Improve Lifetime of Encrypted Nonvolatile Main Memories. IEEE Embed. Syst. Lett. Arijit Nath, Hemangee K. Kapoor
2023	J	`jnl`	CAPMIG: Coherence-Aware Block Placement and Migration in Multiretention STT-RAM Caches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sheel Sindhu Manohar, Hemangee K. Kapoor
2023	B	`conf`	CCGRID 2023: A Holistic Approach to Inclusion and Belonging. CCGrid Beth Plale, Preeti Malakar, Meenakshi D'Souza, Hemangee K. Kapoor, Yogesh Simmhan, Ilkay Altintas, Manohar Swaminathan
2023	C	`conf`	Look before you leap: An Access-based Prudent Page Migration for Hybrid Memories. VLSI-SoC Aishwarya Gupta, N. S. Aswathy, Hemangee K. Kapoor
2023	—	`conf`	NDIE: A Near DRAM Inference Engine Exploiting DIMM's Parallelism. APCCAS Palash Das, Hemangee K. Kapoor
2023	Misc	`conf`	WIB-SAR: Write Intensity Based Selective Address Remapping. VLSID N. S. Aswathy, Deep Bhuinya, Hemangee K. Kapoor
2023	—	`conf`	ZOCHEN: Compression Using Zero Chain Elimination and Encoding to Improve Endurance of Non-Volatile Memories. ISQED Nishant Bharti, Arijit Nath, Swati Upadhyay, Hemangee K. Kapoor
2022	J	`jnl`	CORIDOR: Using COherence and TempoRal LocalIty to Mitigate Read Disurbance ErrOR in STT-RAM Caches. ACM Trans. Embed. Comput. Syst. Sheel Sindhu Manohar, Sparsh Mittal, Hemangee K. Kapoor
2022	—	`conf`	CluSpa: Computation Reduction in CNN Inference by exploiting Clustering and Sparsity. AIMLSystems Imlijungla Longchar, Amey Varhade, Chetan Ingle, Saurabh Baranwal, Hemangee K. Kapoor
2022	—	`conf`	CoSeP: Compression and Content-based Selection Procedure to Improve Lifetime of Encrypted Non-Volatile Main Memories. ACM Great Lakes Symposium on VLSI Arijit Nath, Hemangee K. Kapoor
2022	—	`conf`	DEI activities at the ACM and How to make CS education more inclusive: Keynote Abstract. COMPUTE Hemangee K. Kapoor
2022	A	`conf`	Exploiting successive identical words and differences with dynamic bases for effective compression in Non-Volatile Memories. ISLPED Swati Upadhyay, Arijit Nath, Hemangee K. Kapoor
2022	A	`conf`	Hydra: A near hybrid memory accelerator for CNN inference. DATE Palash Das, Ajay Joshi, Hemangee K. Kapoor
2022	J	`jnl`	Pop-Crypt: Identification and Management of Popular Words for Enhancing Lifetime of EnCrypted Nonvolatile Main Memories. IEEE Trans. Very Large Scale Integr. Syst. Arijit Nath, Hemangee K. Kapoor
2022	—	`conf`	SRS-Mig: Selection and Run-time Scheduling of page Migration for improved response time in hybrid PCM-DRAM memories. ACM Great Lakes Symposium on VLSI N. S. Aswathy, Sreesiddesh Bhavanasi, Arnab Sarkar, Hemangee K. Kapoor
2022	J	`jnl`	SWEL-COFAE : Wear Leveling and Adaptive Encoding Assisted Compression of Frequent Words in Non-Volatile Main Memories. IEEE Trans. Computers Arijit Nath, Hemangee K. Kapoor
2022	C	`conf`	ZaLoBI: Zero avoiding Load Balanced Inference accelerator. VLSI-SoC Imlijungla Longchar, Palash Das, Hemangee K. Kapoor
2022	—	`conf`	i-MAX: Just-In-Time Wakeup of Maximally Gated Router for Power Efficient Multiple NoC. VDAT Neelkamal, Sonal Yadav, Hemangee K. Kapoor
2021	B	`conf`	A Soft Real-time Memory Request Scheduler for Phase Change Memory Systems. RTCSA N. S. Aswathy, Hemangee K. Kapoor, Arnab Sarkar
2021	J	`jnl`	CLU: A Near-Memory Accelerator Exploiting the Parallelism in Convolutional Neural Networks. ACM J. Emerg. Technol. Comput. Syst. Palash Das, Hemangee K. Kapoor
2021	—	`conf`	DAMUS: Dynamic Allocation based on Write Frequency in MUlti-Retention STT-RAM based Last Level Caches. ISQED Mayank Baranwal, Udbhav Chugh, Shivang Dalal, Sukarn Agarwal, Hemangee K. Kapoor
2021	J	`jnl`	Improving the Performance of Hybrid Caches Using Partitioned Victim Caching. ACM Trans. Embed. Comput. Syst. Sukarn Agarwal, Hemangee K. Kapoor
2021	J	`jnl`	Investigating Frequency Scaling, Nonvolatile, and Hybrid Memory Technologies for On-Chip Routers to Support the Era of Dark Silicon. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Khushboo Rani, Hemangee K. Kapoor
2021	—	`conf`	SeNonDiv: Securing Non-Volatile Memory using Hybrid Memory and Critical Data Diversion. ISQED Arijit Nath, Manik B. Bhosle, Hemangee K. Kapoor
2021	J	`jnl`	TARTS: A Temperature-Aware Real-Time Deadline-Partitioned Fair Scheduler. J. Syst. Archit. Sanjay Moulik, Arnab Sarkar, Hemangee K. Kapoor
2021	—	`conf`	WeiSub: Weighted Subset-based Cache Replacement Policy for Last Level Caches. ICCCNT Manojit Ghose, Hemangee K. Kapoor
2021	J	`jnl`	nZESPA: A Near-3D-Memory Zero Skipping Parallel Accelerator for CNNs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Palash Das, Hemangee K. Kapoor
2020	A	`conf`	DidaSel: dirty data based selection of VC for effective utilization of NVM buffers in on-chip interconnects. ISLPED Khushboo Rani, Sukarn Agarwal, Hemangee K. Kapoor
2020	—	`conf`	Dimming Hybrid Caches to Assist in Temperature Control of Chip MultiProcessors. ACM Great Lakes Symposium on VLSI Chirag Joshi, Palash Das, Ashwini A. Kulkarni, Hemangee K. Kapoor
2020	—	`conf`	LiNoVo: Longevity Enhancement of Non-Volatile Last Level Caches in Chip Multiprocessors. ISVLSI Sukarn Agarwal, Hemangee K. Kapoor
2020	—	`conf`	Reinforcement Learning Based Refresh Optimized Volatile STT-RAM Cache. ISVLSI Shashank Suman, Hemangee K. Kapoor
2020	J	`jnl`	Reuse Distance-based Victim Cache for Effective Utilisation of Hybrid Main Memory System. ACM Trans. Design Autom. Electr. Syst. Arijit Nath, Sukarn Agarwal, Hemangee K. Kapoor
2020	A	`conf`	WELCOMF: wear leveling assisted compression using frequent words in non-volatile main memories. ISLPED Arijit Nath, Hemangee K. Kapoor
2020	A*	`conf`	ZENCO: Zero-bytes based ENCOding for Non-Volatile Buffers in On-Chip Interconnects. DAC Khushboo Rani, Hemangee K. Kapoor
2019	J	`jnl`	Cost effective routing techniques in 2D mesh NoC using on-chip transmission lines. J. Parallel Distributed Comput. Dipika Deb, John Jose, Shirshendu Das, Hemangee K. Kapoor
2019	J	`jnl`	Dynamic reconfiguration of embedded-DRAM caches employing zero data detection based refresh optimisation. J. Syst. Archit. Sheel Sindhu Manohar, Hemangee K. Kapoor
2019	—	`conf`	Enhancing the Lifetime of Non-Volatile Caches by Exploiting Module-Wise Write Restriction. ACM Great Lakes Symposium on VLSI Sukarn Agarwal, Hemangee K. Kapoor
2019	J	`jnl`	Exploring the Role of Large Centralised Caches in Thermal Efficient Chip Design. ACM Trans. Design Autom. Electr. Syst. Shounak Chakraborty, Hemangee K. Kapoor
2019	A*	`conf`	Improving Static Power Efficiency via Placement of Network Demultiplexer over Control Plane of Router in Multi-NoCs. DAC Sonal Yadav, Vijay Laxmi, Manoj Singh Gaur, Hemangee K. Kapoor
2019	J	`jnl`	Improving the Lifetime of Non-Volatile Cache by Write Restriction. IEEE Trans. Computers Sukarn Agarwal, Hemangee K. Kapoor
2019	—	`conf`	Lightweight Message Encoding of Power-Gating Controller for On-Time Wakeup of Gated Router in Network-on-Chip. ISED Neelkamal, Sonal Yadav, Hemangee K. Kapoor
2019	Misc	`conf`	Refresh optimised embedded-dram caches based on zero data detection. SAC Sheel Sindhu Manohar, Hemangee K. Kapoor
2019	—	`conf`	Towards Optimizing Refresh Energy in embedded-DRAM Caches using Private Blocks. ACM Great Lakes Symposium on VLSI Sheel Sindhu Manohar, Sukarn Agarwal, Hemangee K. Kapoor
2019	J	`jnl`	Write Variation Aware Buffer Assignment for Improved Lifetime of Non-Volatile Buffers in On-Chip Interconnects. IEEE Trans. Very Large Scale Integr. Syst. Khushboo Rani, Hemangee K. Kapoor
2019	Misc	`conf`	Write Variation Aware Cache Partitioning for Improved Lifetime in Non-volatile Caches. VLSID Arijit Nath, Hemangee K. Kapoor
2019	Misc	`conf`	Write Variation Aware Non-volatile Buffers for On-Chip Interconnects. VLSID Khushboo Rani, Hemangee K. Kapoor
2019	J	`jnl`	Write-variation aware alternatives to replace SRAM buffers with non-volatile buffers in on-chip interconnects. IET Comput. Digit. Tech. Khushboo Rani, Hemangee K. Kapoor
2018	—	`conf`	A Power Efficient Crossbar Arbitration in Multi-NoC for Multicast and Broadcast Traffic. iSES Sonal Yadav, Vijay Laxmi, Hemangee K. Kapoor, Manoj Singh Gaur, Mark Zwolinski
2018	J	`jnl`	Analysing the Role of Last Level Caches in Controlling Chip Temperature. IEEE Trans. Sustain. Comput. Shounak Chakraborty, Hemangee K. Kapoor
2018	Misc	`conf`	DPFair Scheduling with Slowdown and Suspension. VLSID Sanjay Moulik, Arnab Sarkar, Hemangee K. Kapoor
2018	Misc	`conf`	Dynamic Thermal Management by Using Task Migration in Conjunction with Frequency Scaling for Chip Multiprocessors. VLSID Alankar V. Umdekar, Arijit Nath, Shirshendu Das, Hemangee K. Kapoor
2018	J	`jnl`	Energy aware frame based fair scheduling. Sustain. Comput. Informatics Syst. Sanjay Moulik, Arnab Sarkar, Hemangee K. Kapoor
2018	Misc	`conf`	Fault Tolerance in Network on Chip Using Bypass Path Establishing Packets. VLSID Sharma Priya, Sukarn Agarwal, Hemangee K. Kapoor
2018	—	`conf`	Non-blocking Gated Buffers for Energy Efficient on-chip Interconnects in the era of Dark Silicon. ISED Khushboo Rani, Sukarn Agarwal, Hemangee K. Kapoor
2018	J	`jnl`	Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches. IEEE Trans. Very Large Scale Integr. Syst. Sukarn Agarwal, Hemangee K. Kapoor
2018	—	`conf`	Towards Analysing the Effect of Hybrid Caches on the Temperature of Tiled Chip Multi-Processors. iSES Ashwini A. Kulkarni, Khushboo Rani, Sukarn Agarwal, Shrinivas P. Mahajan, Hemangee K. Kapoor
2018	—	`conf`	Towards Analysing the Effect of Snoozy Caches on the Temperature of Tiled Chip Multi-Processors. ISED Ashwini A. Kulkarni, Chirag Joshi, Khushboo Rani, Sukarn Agarwal, Shrinivas P. Mahajan, Hemangee K. Kapoor
2018	Misc	`conf`	Towards Near Data Processing of Convolutional Neural Networks. VLSID Palash Das, Shivam Lakhotia, Prabodh Shetty, Hemangee K. Kapoor
2018	—	`conf`	Towards Near-Data Processing of Compare Operations in 3D-Stacked Memory. ACM Great Lakes Symposium on VLSI Palash Das, Hemangee K. Kapoor
2018	—	`conf`	Utility Aware Snoozy Caches for Energy Efficient Chip Multi-Processors. ACM Great Lakes Symposium on VLSI Ashwini A. Kulkarni, Shounak Chakraborty, Shrinivas P. Mahajan, Hemangee K. Kapoor
2017	J	`jnl`	Dynamic Associativity Management in Tiled CMPs by Runtime Adaptation of Fellow Sets. IEEE Trans. Parallel Distributed Syst. Shirshendu Das, Hemangee K. Kapoor
2017	—	`conf`	Latency Aware Block Replacement for L1 Caches in Chip Multiprocessor. ISVLSI Shirshendu Das, Hemangee K. Kapoor
2017	—	`conf`	Lifetime Enhancement of Non-Volatile Caches by Exploiting Dynamic Associativity Management Techniques. VLSI-SoC (Selected Papers) Sukarn Agarwal, Hemangee K. Kapoor
2017	J	`jnl`	Performance linked dynamic cache tuning: A static energy reduction approach in tiled CMPs. Microprocess. Microsystems Shounak Chakraborty, Hemangee K. Kapoor
2017	C	`conf`	Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets. VLSI-SoC Sukarn Agarwal, Hemangee K. Kapoor
2017	Misc	`conf`	Towards Controlling Chip Temperature by Dynamic Cache Reconfiguration in Multiprocessors. VLSID Shounak Chakraborty, Hemangee K. Kapoor
2017	Misc	`conf`	Towards a Better Lifetime for Non-volatile Caches in Chip Multiprocessors. VLSID Sukarn Agarwal, Hemangee K. Kapoor
2016	J	`jnl`	A Framework for Block Placement, Migration, and Fast Searching in Tiled-DNUCA Architecture. ACM Trans. Design Autom. Electr. Syst. Shirshendu Das, Hemangee K. Kapoor
2016	Misc	`conf`	Dynamic associativity enabled DNUCA to improve block localisation in tiled CMPs. SAC Shirshendu Das, Hemangee K. Kapoor
2016	J	`jnl`	PAFSV: A Formal Framework for Specification and Analysis of SystemVerilog. Comput. Informatics Ka Lok Man, Chi-Un Lei, Hemangee K. Kapoor, Tomas Krilavicius, Jieming Ma, Nan Zhang
2016	C	`conf`	Restricting writes for energy-efficient hybrid cache in multi-core architectures. VLSI-SoC Sukarn Agarwal, Hemangee K. Kapoor
2016	Misc	`conf`	Static energy efficient cache reconfiguration for dynamic NUCA in tiled CMPs. SAC Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor
2016	C	`conf`	Static energy reduction by performance linked dynamic cache resizing. VLSI-SoC Shounak Chakraborty, Hemangee K. Kapoor
2016	—	`conf`	Tag only storage for capacity optimised last level cache in chip multiprocessors. VDAT Surajit Das, Shirshendu Das, Hemangee K. Kapoor
2016	Misc	`conf`	Towards a Better Cache Utilization by Selective Data Storage for CMP Last Level Caches. VLSID Shirshendu Das, Hemangee K. Kapoor
2016	—	`conf`	Towards a dynamic associativity enabled write prediction based hybrid cache. VDAT Sukarn Agarwal, Hemangee K. Kapoor
2015	J	`jnl`	A Discrete Event System Approach to Online Testing of Speed Independent Circuits. VLSI Design Pradeep Kumar Biswal, K. Mishra, Santosh Biswas, Hemangee K. Kapoor
2015	—	`conf`	An efficient searching mechanism for dynamic NUCA in chip multiprocessors. VDAT Kartheek Vanapalli, Hemangee K. Kapoor, Shirshendu Das
2015	Misc	`conf`	Dynamic associativity management using utility based way-sharing. SAC Shirshendu Das, Hemangee K. Kapoor
2015	Misc	`conf`	Exploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPs. VLSID Shirshendu Das, Hemangee K. Kapoor
2015	—	`conf`	Performance Constrained Static Energy Reduction Using Way-Sharing Target-Banks. IPDPS Workshops Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor
2015	—	`conf`	Power aware cache miss reduction by energy efficient victim retention. VDAT Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor
2015	Misc	`conf`	Static energy reduction by performance linked cache capacity management in tiled CMPs. SAC Hemangee K. Kapoor, Shirshendu Das, Shounak Chakraborty
2014	—	`conf`	A New Recursive Partitioning Multicast Routing Algorithm for 3D Network-on-Chip. VDAT Narendra Kumar Meena, Hemangee K. Kapoor, Shounak Chakraborty
2014	—	`conf`	An Approach for Multicast Routing in Networks-on-Chip. ICIT M. Lakshmi Prasad, Shirshendu Das, Hemangee K. Kapoor
2014	—	`conf`	Modelling and analysis of wireless communication over Networks-on-Chip. VDAT Apoorv Kumar, Hemangee K. Kapoor
2014	—	`conf`	RT-DVS for Power Optimization in Multiprocessor Real-Time Systems. ICIT B. Venkateswarlu Naik, Shirshendu Das, Hemangee K. Kapoor
2014	J	`jnl`	Victim retention for reducing cache misses in tiled chip multiprocessors. Microprocess. Microsystems Shirshendu Das, Hemangee K. Kapoor
2013	J	`jnl`	A Security Framework for NoC Using Authenticated Encryption and Session Keys. Circuits Syst. Signal Process. Hemangee K. Kapoor, G. Bhoopal Rao, Sharique Arshi, Gaurav Trivedi
2013	J	`jnl`	A formal framework for interfacing mixed-timing systems. Integr. Shirshendu Das, Parasara Sridhar Duggirala, Hemangee K. Kapoor
2013	J	`jnl`	Design and formal verification of a hierarchical cache coherence protocol for NoC based multiprocessors. J. Supercomput. Hemangee K. Kapoor, Praveen Kanakala, Malti Verma, Shirshendu Das
2013	—	`conf`	Dynamic Associativity Management Using Fellow Sets. ISED Shirshendu Das, Hemangee K. Kapoor
2013	J	`jnl`	Formal Approach for DVS-Based Power Management for Multiple Server System in Presence of Server Failure and Repair. IEEE Trans. Ind. Informatics Lalit Chandnani, Hemangee K. Kapoor
2013	—	`conf`	Random-LRU: A Replacement Policy for Chip Multiprocessors. VDAT Shirshendu Das, Nagaraju Polavarapu, Prateek D. Halwe, Hemangee K. Kapoor
2013	C	`conf`	Towards a Better Cache Utilization Using Controlled Cache Partitioning. DASC Prateek D. Halwe, Shirshendu Das, Hemangee K. Kapoor
2011	—	`conf`	An Authenticated Encryption Based Security Framework for NoC Architectures. ISED K. Sajeesh, Hemangee K. Kapoor
2010	Misc	`conf`	Exploring Use of NoC for Reconfigurable Video Coding. VLSI Design Alpesh Patel, Hemangee K. Kapoor
2010	—	`conf`	Fair diagnosability in PN-based DES models. ICCA Khan Ajoy, Kushagra Misra, Santosh Biswas, Jatindra Kumar Deka, Hemangee K. Kapoor
2009	J	`jnl`	A Process Algebraic View of Latency-Insensitive Systems. IEEE Trans. Computers Hemangee K. Kapoor
2007	J	`jnl`	Controllable Delay-Insensitive Processes. Fundam. Informaticae Mark B. Josephs, Hemangee K. Kapoor
2007	—	`conf`	Modelling Latency-Insensitive Systems in CSP. ACSD Hemangee K. Kapoor
2006	B	`conf`	Formal Modelling and Verification of an Asynchronous DLX Pipeline. SEFM Hemangee K. Kapoor
2006	J	`jnl`	Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments. Fundam. Informaticae Hemangee K. Kapoor, Mark B. Josephs, Dennis P. Furey
2005	—	`conf`	Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation. ACSD Hemangee K. Kapoor, Mark B. Josephs
2004	A*	`conf`	Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis. DAC Hemangee K. Kapoor, Mark B. Josephs
2004	J	`jnl`	Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench. Inf. Process. Lett. Hemangee K. Kapoor, Mark B. Josephs
2004	—	`conf`	Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments. ACSD Hemangee K. Kapoor, Mark B. Josephs, Dennis P. Furey