Helmut Reinig - RankMe

17 papers A 2B 3Misc 2Journal 2Unranked 7

Year	Rank	Type	Title / Venue / Authors
2014	J	`jnl`	Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip Topologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann
2013	A	`conf`	A spectral clustering approach to application-specific network-on-chip synthesis. DATE Vladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann
2012	A	`conf`	Automated construction of a cycle-approximate transaction level model of a memory controller. DATE Vladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann
2012	Misc	`conf`	Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs. CODES+ISSS Vladimir Todorov, Alberto Ghiribaldi, Helmut Reinig, Davide Bertozzi, Ulf Schlichtmann
2011	—	`conf`	Contrasting multi-synchronous MPSoC design styles for fine-grained clock domain partitioning: the full-HD video playback case study. NoCArc@MICRO Hervé Tatenguem, Daniele Ludovici, Alessandro Strano, Davide Bertozzi, Helmut Reinig
2010	—	`conf`	Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in On-chip Networks. NOCS Andreas Lankes, Thomas Wild, Andreas Herkersdorf, Sören Sonntag, Helmut Reinig
2009	—	`conf`	NoC topology exploration for mobile multimedia applications. ICECS Andreas Lankes, Andreas Herkersdorf, Sören Sonntag, Helmut Reinig
2008	—	`conf`	An Efficient Weighted-Round-Robin Algorithm for Multiprocessor Architectures. Annual Simulation Symposium Sören Sonntag, Helmut Reinig
1999	—	`—`	A scalable architecture for custom computing. Helmut Reinig
1998	—	`conf`	Codevelopment of long haul ISDN transceiver and design methodology improves time to market. ICECS Markus Brandstetter, Torsten Harms, Helmut Reinig, Michael Vanrompay
1996	Misc	`conf`	CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework. VLSI Design Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig
1996	J	`jnl`	High-performance computing using a reconfigurable accelerator. Concurr. Pract. Exp. Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig
1995	—	`conf`	A Parallelizing Compilation Method for the Map-oriented Machine. ASAP Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig, Karin Schmidt
1994	B	`conf`	A New FPGA Architecture for Word-Oriented Datapaths. FPL Reiner W. Hartenstein, Rainer Kress, Helmut Reinig
1994	—	`conf`	A dynamically reconfigurable wavefront array architecture for evaluation of expressions. ASAP Reiner W. Hartenstein, Rainer Kress, Helmut Reinig
1994	B	`conf`	Data-Procedural Languages for FPL-based Machines. FPL Andreas Ast, Jürgen Becker, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt
1992	B	`conf`	Novel High Performance Machine Paradigms and Fast- Turnaround ASIC Design Methods. FPL Andreas Ast, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt