Helmut E. Graeb

47 papers A* 7A 19C 2Journal 13Unranked 6

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	A Hierarchical Performance Equation Library for Basic Op-Amp Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Inga Abel, Maximilian Neuner, Helmut E. Graeb
2020	J	`jnl`	PASTEL: Parasitic Matching-Driven Placement and Routing of Capacitor Arrays With Generalized Ratios in Charge-Redistribution SAR-ADCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ye Xing Ding, Florin Burcea, Husni M. Habal, Helmut E. Graeb
2017	A	`conf`	High-density MOM capacitor array with novel mortise-tenon structure for low-power SAR ADC. DATE Nai-Chen Chen, Pang-Yen Chou, Helmut E. Graeb, Mark Po-Hung Lin
2016	J	`jnl`	A New Chessboard Placement and Sizing Method for Capacitors in a Charge-Scaling DAC by Worst-Case Analysis of Nonlinearity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Florin Burcea, Husni M. Habal, Helmut E. Graeb
2016	J	`jnl`	DeMixGen: Deterministic Mixed-Signal Layout Generation With Separated Analog and Digital Signal Paths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mark Po-Hung Lin, Po-Hsun Chang, Shuenn-Yuh Lee, Helmut E. Graeb
2016	A*	`conf`	Procedural capacitor placement in differential charge-scaling converters by nonlinearity analysis. DAC Florin Burcea, Husni M. Habal, Helmut E. Graeb
2015	A	`conf`	Detection of asymmetric aging-critical voltage conditions in analog power-down mode. DATE Michael Zwerger, Helmut E. Graeb
2015	A	`conf`	Power-Down Circuit Synthesis for Analog/Mixed-Signal. ICCAD Michael Zwerger, Maximilian Neuner, Helmut E. Graeb
2013	—	`conf`	Evaluating analog circuit performance in light of MOSFET aging at different time scales. ICICDT Husni M. Habal, Helmut E. Graeb
2013	A*	`conf`	Predicting future product performance: modeling and evaluation of standard cells in FinFET technologies. DAC Veit Kleeberger, Helmut E. Graeb, Ulf Schlichtmann
2012	J	`jnl`	MARS: Matching-Driven Analog Sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Michael Eick, Helmut E. Graeb
2012	J	`jnl`	Tolerance Design of Analog Circuits using a Branch-and-Bound Based Approach. J. Circuits Syst. Comput. Michael Pehl, Helmut E. Graeb
2011	J	`jnl`	Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Michael Eick, Martin Strasser, Kun Lu, Ulf Schlichtmann, Helmut E. Graeb
2010	—	`conf`	Automatic generation of hierarchical placement rules for analog integrated circuits. ISPD Michael Eick, Martin Strasser, Helmut E. Graeb, Ulf Schlichtmann
2010	—	`conf`	Sizing analog circuits using an SQP and Branch and Bound based approach. ICECS Michael Pehl, Michael Zwerger, Helmut E. Graeb
2009	J	`jnl`	A Successive Approach to Compute the Bounded Pareto Front of Practical Multiobjective Optimization Problems. SIAM J. Optim. Daniel Mueller-Gritschneder, Helmut E. Graeb, Ulf Schlichtmann
2008	C	`conf`	A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters. ICCD Michael Pehl, Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann
2008	A	`conf`	From Transistor to PLL - Analogue Design and EDA Methods. DATE David M. Binkley, Helmut E. Graeb, Georges G. E. Gielen, Jaijeet S. Roychowdhury
2008	A	`conf`	Sizing Rules for Bipolar Analog Circuit Design. DATE Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann
2008	J	`jnl`	The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann
2007	J	`jnl`	Analog Performance Space Exploration by Normal-Boundary Intersection and by Fourier-Motzkin Elimination. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Guido Stehr, Helmut E. Graeb, Kurt Antreich
2007	—	`conf`	Pareto-Front Computation and Automatic Sizing of CPPLLs. ISQED Jun Zou, Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann
2007	A	`conf`	Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming. DATE Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann
2006	A*	`conf`	A CPPLL hierarchical optimization methodology considering jitter, power and locking time. DAC Jun Zou, Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann
2006	C	`conf`	Fast evaluation of analog circuit structures by polytopal approximations. ISCAS Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann
2005	A*	`conf`	Deterministic approaches to analog performance space exploration (PSE). DAC Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann
2005	—	`conf`	Eigenschaftsraumexploration bei der hierarchischen Dimensionierung analoger integrierter Schaltungen. GI Jahrestagung (1) Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann
2004	A	`conf`	Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizing. ICCAD Guido Stehr, Helmut E. Graeb, Kurt Antreich
2003	A	`conf`	Initial Sizing of Analog Integrated Circuits by Centering Within Topology-Given Implicit Specification. ICCAD Guido Stehr, Michael Pronath, Frank Schenkel, Helmut E. Graeb, Kurt Antreich
2003	A*	`conf`	Performance trade-off analysis of analog circuits by normal-boundary intersection. DAC Guido Stehr, Helmut E. Graeb, Kurt Antreich
2002	A	`conf`	A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits. DATE Michael Pronath, Helmut E. Graeb, Kurt Antreich
2002	A	`conf`	Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets. DATE Robert Schwencker, Frank Schenkel, Michael Pronath, Helmut E. Graeb
2001	A*	`conf`	Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search. DAC Frank Schenkel, Michael Pronath, Stephan Zizala, Robert Schwencker, Helmut E. Graeb, Kurt Antreich
2001	A	`conf`	The Sizing Rules Method for Analog Integrated Circuit Design. ICCAD Helmut E. Graeb, Stephan Zizala, Josef Eckmüller, Kurt Antreich
2000	A	`conf`	A Parametric Test Method for Analog Components in Integrated Mixed-Signal Circuits. ICCAD Michael Pronath, Volker Gloeckel, Helmut E. Graeb
2000	A	`conf`	The Generalized Boundary Curve-A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits. DATE Robert Schwencker, Frank Schenkel, Helmut E. Graeb, Kurt Antreich
1999	J	`jnl`	Analog testing by characteristic observation inference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich
1999	A	`conf`	Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints. DATE Robert Schwencker, Josef Eckmüller, Helmut E. Graeb, Kurt Antreich
1998	A	`conf`	Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults. DATE Walter M. Lindermeir, Thomas J. Vogels, Helmut E. Graeb
1998	A	`conf`	Hierarchical Characterization of Analog Integrated CMOS Circuits. DATE Josef Eckmüller, Martin Groepl, Helmut E. Graeb
1995	A	`conf`	Design based analog testing by Characteristic Observation Inference. ICCAD Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich
1994	J	`jnl`	Circuit analysis and optimization driven by worst-case distances. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kurt Antreich, Helmut E. Graeb, Claudia U. Wieser
1994	A	`conf`	Fast transient power and noise estimation for VLSI circuits. ICCAD Wolfgang T. Eisenmann, Helmut E. Graeb
1993	A*	`conf`	Improved Methods for Worst-Case Analysis and Optimization Incorporating Operating Tolerances. DAC Helmut E. Graeb, Claudia U. Wieser, Kurt Antreich
1992	J	`jnl`	Circuit yield optimization by analyzing performance statistics. Microprocess. Microprogramming Helmut E. Graeb, Reiner E. Lederle
1992	—	`conf`	Design verification considering manufacturing tolerances by using worst-caste distances. EURO-DAC Helmut E. Graeb, Claudia U. Wieser, Kurt Antreich
1991	A	`conf`	Circuit Optimization Driven by Worst-Case Distances. ICCAD Kurt Antreich, Helmut E. Graeb