Heinz Riener - RankMe

57 papers A* 4A 8C 11Journal 14Unranked 19

Year	Rank	Type	Title / Venue / Authors
2025	A*	`conf`	Logic Restructuring with Preserved Logic Blocks. DAC Siang-Yun Lee, Heinz Riener, Sascha Richter, Ankush Sood
2025	J	`jnl`	Technology Legalization and Optimization for Adiabatic Quantum-Flux Parametron. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Siang-Yun Lee, Alessandro Tempia Calvino, Heinz Riener, Giovanni De Micheli
2024	A*	`conf`	Late Breaking Results: Majority-Inverter Graph Minimization by Design Space Exploration. DAC Siang-Yun Lee, Alessandro Tempia Calvino, Heinz Riener, Giovanni De Micheli
2023	J	`jnl`	Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shubham Rai, Alessandro Tempia Calvino, Heinz Riener, Giovanni De Micheli, Akash Kumar
2022	J	`jnl`	A Simulation-Guided Paradigm for Logic Synthesis and Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, Giovanni De Micheli
2022	—	`conf`	A Versatile Mapping Approach for Technology Mapping and Graph Optimization. ASP-DAC Alessandro Tempia Calvino, Heinz Riener, Shubham Rai, Akash Kumar, Giovanni De Micheli
2022	J	`jnl`	An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications. CoRR Siang-Yun Lee, Heinz Riener, Giovanni De Micheli
2022	A*	`conf`	Beyond local optimality of buffer and splitter insertion for AQFP circuits. DAC Siang-Yun Lee, Heinz Riener, Giovanni De Micheli
2022	—	`conf`	Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis. ASP-DAC Heinz Riener, Siang-Yun Lee, Alan Mishchenko, Giovanni De Micheli
2021	—	`conf`	Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits. ASP-DAC Eleonora Testa, Siang-Yun Lee, Heinz Riener, Giovanni De Micheli
2021	A	`conf`	From Boolean functions to quantum circuits: A scalable quantum compilation flow in C++. DATE Bruno Schmitt, Fereshte Mozafari, Giulia Meuli, Heinz Riener, Giovanni De Micheli
2021	J	`jnl`	Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits. CoRR Siang-Yun Lee, Heinz Riener, Giovanni De Micheli
2021	C	`conf`	Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition. DDECS Siang-Yun Lee, Heinz Riener, Giovanni De Micheli
2021	—	`conf`	Optimizing Adiabatic Quantum-Flux-Parametron (AQFP) Circuits using an Exact Database. NANOARCH Dewmini Sudara Marakkalage, Heinz Riener, Giovanni De Micheli
2021	A	`conf`	Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies. DATE Shubham Rai, Heinz Riener, Giovanni De Micheli, Akash Kumar
2021	J	`jnl`	Three-Input Gates for Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dewmini Sudara Marakkalage, Eleonora Testa, Heinz Riener, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli
2020	A	`conf`	A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks. DATE Eleonora Testa, Mathias Soeken, Heinz Riener, Luca G. Amarù, Giovanni De Micheli
2020	J	`jnl`	A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks. IACR Cryptol. ePrint Arch. Eleonora Testa, Mathias Soeken, Heinz Riener, Luca G. Amarù, Giovanni De Micheli
2020	—	`conf`	Automatic Uniform Quantum State Preparation Using Decision Diagrams. ISMVL Fereshte Mozafari, Mathias Soeken, Heinz Riener, Giovanni De Micheli
2020	A	`conf`	Exact DAG-Aware Rewriting. DATE Heinz Riener, Alan Mishchenko, Mathias Soeken
2020	A	`conf`	Learning to Automate the Design Updates From Observed Engineering Changes in the Chip Development Cycle. DATE Victor N. Kravets, Jie-Hong R. Jiang, Heinz Riener
2020	C	`conf`	Revisiting Explicit Enumeration for Exact Synthesis. DSD Gianluca Martino, Heinz Riener, Görschwin Fey
2020	J	`jnl`	Safety Synthesis Sans Specification. CoRR Roderick Bloem, Hana Chockler, Masoud Ebrahimi, Dana Fisman, Heinz Riener
2020	J	`jnl`	Simulation-Guided Boolean Resubstitution. CoRR Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, Giovanni De Micheli
2019	C	`conf`	Evaluating ESOP Optimization Methods in Quantum Compilation Flows. RC Giulia Meuli, Bruno Schmitt, Rüdiger Ehlers, Heinz Riener, Giovanni De Micheli
2019	C	`conf`	Exact Synthesis of LTL Properties from Traces. FDL Heinz Riener
2019	—	`conf`	Logic Optimization of Majority-Inverter Graphs. MBMV Heinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca G. Amarù, Giovanni De Micheli, Mathias Soeken
2019	A	`conf`	On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis. DATE Heinz Riener, Winston Haaswijk, Alan Mishchenko, Giovanni De Micheli, Mathias Soeken
2019	A*	`conf`	Scalable Generic Logic Synthesis: One Approach to Rule Them All. DAC Heinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca G. Amarù, Giovanni De Micheli, Mathias Soeken
2019	J	`jnl`	Synthesizing adaptive test strategies from temporal logic specifications. Formal Methods Syst. Des. Roderick Bloem, Görschwin Fey, Fabian Greif, Robert Könighofer, Ingo Pill, Heinz Riener, Franz Röck
2018	C	`conf`	Design Understanding: From Logic to Specification VLSI-SoC Görschwin Fey, Tara Ghasempouri, Swen Jacobs, Gianluca Martino, Jaan Raik, Heinz Riener
2018	J	`jnl`	Exact Synthesis of ESOP Forms. CoRR Heinz Riener, Rüdiger Ehlers, Bruno Schmitt, Giovanni De Micheli
2018	—	`conf`	Generating Safety Guidance for Medical Injection with Three-Compartment Pharmacokinetics Model. ISVLSI Cunxi Yu, Heinz Riener, Francesca Stradolini, Giovanni De Micheli
2018	—	`conf`	Mining Latency Guarantees for RTL Designs. ISMVL Jan Malburg, Heinz Riener, Görschwin Fey
2018	—	`conf`	Size Optimization of MIGs with an Application to QCA and STMG Technologies. NANOARCH Heinz Riener, Eleonora Testa, Luca G. Amarù, Mathias Soeken, Giovanni De Micheli
2018	J	`jnl`	Synthesizing Adaptive Test Strategies from Temporal Logic Specifications. CoRR Roderick Bloem, Görschwin Fey, Fabian Greif, Robert Könighofer, Ingo Pill, Heinz Riener, Franz Röck
2018	J	`jnl`	The EPFL Logic Synthesis Libraries. CoRR Mathias Soeken, Heinz Riener, Winston Haaswijk, Giovanni De Micheli
2017	—	`conf`	CEGAR-based EF synthesis of Boolean functions with an application to circuit rectification. ASP-DAC Heinz Riener, Rüdiger Ehlers, Görschwin Fey
2017	—	`conf`	Counterexample-Guided EF Synthesis of Boolean Functions. MBMV Heinz Riener, Rüdiger Ehlers, Görschwin Fey
2017	—	`—`	Formal methods for automated debugging. Heinz Riener
2017	J	`jnl`	metaSMT: focus on your application and not on solver integration. Int. J. Softw. Tools Technol. Transf. Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, Görschwin Fey
2016	—	`conf`	Counterexample-guided diagnosis. IVSW Heinz Riener, Görschwin Fey
2016	C	`conf`	Designing reliable cyber-physical systems overview associated to the special session at FDL'16. FDL Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Görschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard K. Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
2016	C	`conf`	Equivalence checking on ESL utilizing a priori knowledge. FDL Niels Thole, Heinz Riener, Görschwin Fey
2016	A	`conf`	Exact diagnosis using boolean satisfiability. ICCAD Heinz Riener, Görschwin Fey
2016	—	`conf`	SMT-Based CPS Parameter Synthesis. ARCH@CPSWeek Heinz Riener, Robert Könighofer, Görschwin Fey, Roderick Bloem
2016	C	`conf`	WCET overapproximation for software in the context of a Cyber-Physical System. VLSI-SoC Niklas Krafczyk, Heinz Riener, Görschwin Fey
2015	C	`conf`	Equivalence Checking on System Level Using a Priori Knowledge. DDECS Niels Thole, Heinz Riener, Görschwin Fey
2015	—	`conf`	Execution Tracing of C Code for Formal Analysis (Extended Abstract). MBMV Heinz Riener, Michael Kirkedal Thomsen, Görschwin Fey
2015	—	`conf`	Path-Based Program Repair. FESCA Heinz Riener, Rüdiger Ehlers, Görschwin Fey
2014	—	`conf`	A Logic for Cardinality Constraints (Extended Abstract). MBMV Heinz Riener, Oliver Keszöcze, Rolf Drechsler, Görschwin Fey
2014	C	`conf`	MetaSMT: a unified interface to SMT-LIB2. FDL Heinz Riener, Mathias Soeken, Clemens Werther, Görschwin Fey, Rolf Drechsler
2013	A	`conf`	Improving fault tolerance utilizing hardware-software-co-synthesis. DATE Heinz Riener, Stefan Frehse, Görschwin Fey
2013	—	`conf`	Yet a Better Error Explanation Algorithm (Extended Abstract). MBMV Heinz Riener, Görschwin Fey
2012	—	`conf`	FAuST: A Framework for Formal Verification, Automated Debugging, and Software Test Generation. SPIN Heinz Riener, Görschwin Fey
2012	C	`conf`	Model-based diagnosis versus error explanation. MEMOCODE Heinz Riener, Görschwin Fey
2011	—	`conf`	Test Case Generation from Mutants Using Model Checking Techniques. ICST Workshops Heinz Riener, Roderick Bloem, Görschwin Fey