Heinrich Theodor Vierhaus

115 papers A 8B 2C 49Misc 1Journal 17Unranked 38

Year	Rank	Type	Title / Venue / Authors
2020	A	`conf`	RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. DATE Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka
2019	J	`jnl`	RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. CoRR Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka
2018	—	`conf`	Migrating Electronic Systems from Fault Tolerant Computing to Error Resilience. SPA Heinrich Theodor Vierhaus
2018	C	`conf`	Optimal Dependability and Fine Granular Error Resilience Methodology for Reconfigurable Systems. DSD Farnoosh Hosseinzadeh, Petr Pfeifer, Heinrich Theodor Vierhaus
2018	—	`conf`	RESCUE: Cross-Sectoral PhD Training Concept for Interdependent Reliability, Security and Quality. EWME Heinrich Theodor Vierhaus, Maksim Jenihhin, Matteo Sonza Reorda
2017	C	`conf`	Fast power overhead prediction for hardware redundancy-based fault tolerance. IOLTS Stefan Scharoba, Heinrich Theodor Vierhaus
2017	C	`conf`	Fault detection and self repair in Hsiao-code FEC circuits. DDECS Davide Dicorato, Petr Pfeifer, Heinrich Theodor Vierhaus
2017	—	`conf`	Forward error correction in wireless communication systems for industrial applications. SPA Petr Pfeifer, Heinrich Theodor Vierhaus
2017	C	`conf`	On comparison of robust configurable FPGA encoders for dependable industrial communication systems. IOLTS Petr Pfeifer, Farnoosh Hosseinzadeh, Heinrich Theodor Vierhaus
2017	J	`jnl`	Test and Diagnosis of Automotive Embedded Processors via High-Speed Standard Interfaces. J. Circuits Syst. Comput. Christian Gleichner, Heinrich Theodor Vierhaus
2017	—	`conf`	The coarse and fine granular fault tolerance techniques in FPGA-based processors. SPA Farnoosh Hosseinzadeh, Petr Pfeifer, Heinrich Theodor Vierhaus
2016	—	`conf`	A comprehensive software-based self-test and self-repair method for statically scheduled superscalar processors. LATS Mario Schölzel, Tobias Koal, Sebastian Müller, Stefan Scharoba, Stephanie Roder, Heinrich Theodor Vierhaus
2016	C	`conf`	An Interactive Design Space Exploration Tool for Dependable Integrated Circuits. DSD Stefan Scharoba, Heinrich Theodor Vierhaus
2016	—	`conf`	Iterative error correction with double/triple error detection. SPA Petr Pfeifer, Heinrich Theodor Vierhaus
2016	J	`jnl`	Non-Cyclic Design Space Exploration for ASIPs - Compiler-Centered Microprocessor Design (CoMet). J. Circuits Syst. Comput. Roberto Urban, Heinrich Theodor Vierhaus, Mario Schölzel, Enrico Altmann, Horst Seelig
2016	C	`conf`	Test of automotive embedded processors with high diagnostic resolution. DDECS Christian Gleichner, Heinrich Theodor Vierhaus
2015	C	`ed.`	18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2015, Belgrade, Serbia, April 22-24, 2015 DDECS Zoran Stamenkovic, Witold A. Pleskacz, Jaan Raik, Heinrich Theodor Vierhaus
2015	—	`conf`	A multi-layer software-based fault-tolerance approach for heterogenous multi-core systems. LATS Sebastian Müller, Tobias Koal, Stefan Scharoba, Heinrich Theodor Vierhaus, Mario Schölzel
2015	C	`conf`	Combining Correction of Delay Faults and Transient Faults. DDECS Tobias Koal, Stefan Scharoba, Heinrich Theodor Vierhaus
2015	C	`conf`	Compiler-Centred Microprocessor Design (CoMet) - From C-Code to a VHDL Model of an ASIP. DDECS Roberto Urban, Mario Schölzel, Heinrich Theodor Vierhaus, Enrico Altmann, Horst Seelig
2015	—	`conf`	Detection and Correction of Logic Errors Using Extra Time Slots. GI-Jahrestagung Davide Dicorato, Heinrich Theodor Vierhaus
2015	—	`conf`	Doktorandenprogramm der INFORMATIK 2015. GI-Jahrestagung Ansgar Scherp, Steffen Becker, Heinrich Theodor Vierhaus
2015	—	`conf`	Error resilience in nano-electronic digital circuits and systems. SPA Heinrich Theodor Vierhaus
2015	—	`conf`	Fehlertolerante und energieeffiziente eingebettete Systeme: Methoden und Anwendungen. GI-Jahrestagung Mario Schölzel, Heinrich Theodor Vierhaus
2015	—	`conf`	Multiple fault testing in systems-on-chip with high-level decision diagrams. IDT Raimund Ubar, Stephen Adeboye Oyeniran, Mario Schölzel, Heinrich Theodor Vierhaus
2015	—	`conf`	Redundancy evaluation process of processor components for permanent fault compensation. AHS Tobias Koal, Heinrich Theodor Vierhaus
2015	—	`conf`	Test eingebetteter Prozessoren im Zielsystem mit hoher diagnostischer Auflösung. GI-Jahrestagung Christian Gleichner, Heinrich Theodor Vierhaus
2014	—	`conf`	Advanced technical education in the age of cyber physical systems. EWME Heinrich Theodor Vierhaus, Mario Schölzel, Jaan Raik, Raimund Ubar
2014	C	`conf`	Combining fault tolerance and self repair at minimum cost in power and hardware. DDECS Tobias Koal, Mario Schölzel, Heinrich Theodor Vierhaus
2014	—	`conf`	Diagnostic self-test for dynamically scheduled superscalar processors based on reconfiguration techniques for handling permanent faults. DFT Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus
2014	B	`conf`	Reconfigurable high performance architectures: How much are they ready for safety-critical applications? ETS Davide Sabena, Luca Sterpone, Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus, S. Wong, Robért Glein, Florian Rittner, C. Stender, Mario Porrmann, Jens Hagemeyer
2014	B	`conf`	Systematic generation of diagnostic software-based self-test routines for processor components. ETS Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus
2014	C	`conf`	Timing for virtual TMR in logic circuits. IOLTS Sebastian Müller, Tobias Koal, Mario Schölzel, Heinrich Theodor Vierhaus
2014	—	`conf`	Vergleich der Beschreibung und Simulation einer Befehlssatzarchitektur in LISA und CoMet. MBMV Roberto Urban, Kai Lehniger, Maximilian Heyne, Mario Schölzel, Heinrich Theodor Vierhaus
2013	—	`conf`	Ein konfigurierbarer Zwischencodesimulator zum compilerzentrierten Mikroprozessorentwurf. MBMV Roberto Urban, Mario Schölzel, Heinrich Theodor Vierhaus
2013	C	`conf`	On performance estimation of a scalable VLIW soft-core in XILINX FPGAs. DDECS Petr Pfeifer, Zdenek Plíva, Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus
2013	C	`conf`	On the feasibility of combining on-line-test and self repair for logic circuits. DDECS Tobias Koal, Markus Ulbricht, Piet Engelke, Heinrich Theodor Vierhaus
2013	C	`conf`	Towards a Graceful Degradable Multicore-System by Hierarchical Handling of Hard Errors. PDP Sebastian Müller, Mario Schölzel, Heinrich Theodor Vierhaus
2013	—	`conf`	Towards an automatic generation of diagnostic in-field SBST for processor components. LATW Mario Schölzel, Tobias Koal, Stephanie Roder, Heinrich Theodor Vierhaus
2013	C	`conf`	Virtual TMR Schemes Combining Fault Tolerance and Self Repair. DSD Tobias Koal, Markus Ulbricht, Heinrich Theodor Vierhaus
2012	C	`conf`	Activity Migration in M-of-N-Systems by Means of Load-Balancing. DSD Markus Ulbricht, Heinrich Theodor Vierhaus, Tobias Koal
2012	C	`conf`	An adaptive self-test routine for in-field diagnosis of permanent faults in simple RISC cores. DDECS Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus
2012	C	`conf`	Combining on-line fault detection and logic self repair. DDECS Tobias Koal, Markus Ulbricht, Heinrich Theodor Vierhaus
2012	—	`conf`	Hierarchical Self-repair in Heterogeneous Multi-core Systems by Means of a Software-based Reconfiguration. ARCS Workshops Sebastian Müller, Mario Schölzel, Heinrich Theodor Vierhaus
2012	C	`ed.`	IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2012, Tallinn, Estonia, April 18-20, 2012 DDECS Jaan Raik, Viera Stopjaková, Heinrich Theodor Vierhaus, Witold A. Pleskacz, Raimund Ubar, Helena Kruus, Maksim Jenihhin
2012	C	`conf`	Scan Based Tests via Standard Interfaces. DSD Christian Gleichner, Heinrich Theodor Vierhaus, Piet Engelke
2011	C	`ed.`	14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011 DDECS Rolf Kraemer, Adam Pawlak, Andreas Steininger, Mario Schölzel, Jaan Raik, Heinrich Theodor Vierhaus
2011	C	`conf`	A new hierarchical built-in self-test with on-chip diagnosis for VLIW processors. DDECS Markus Ulbricht, Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus
2011	—	`conf`	On the Feasibility of Built-In Self Repair for Logic Circuits. DFT Tobias Koal, Daniel Scheit, Mario Schölzel, Heinrich Theodor Vierhaus
2011	C	`conf`	Optimal spare utilization for reliability and mean lifetime improvement of logic built-in self-repair. DDECS Tobias Koal, Heinrich Theodor Vierhaus
2010	C	`ed.`	13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, April 14-16, 2010 DDECS Elena Gramatová, Zdenek Kotásek, Andreas Steininger, Heinrich Theodor Vierhaus, Horst Zimmermann
2010	C	`conf`	A software-based self-test and hardware reconfiguration solution for VLIW processors. DDECS Tobias Koal, Heinrich Theodor Vierhaus
2010	C	`conf`	Combining de-stressing and self repair for long-term dependable systems. DDECS Tobias Koal, Heinrich Theodor Vierhaus
2010	C	`conf`	Test Data and Power Reductions for Transition Delay Tests for Massive-Parallel Scan Structures. DSD René Kothe, Heinrich Theodor Vierhaus
2009	C	`conf`	A Concept for Logic Self Repair. DSD Tobias Koal, Heinrich Theodor Vierhaus, Daniel Scheit
2009	C	`conf`	A scheme of logic self repair including local interconnects. DDECS Tobias Koal, Daniel Scheit, Heinrich Theodor Vierhaus
2009	C	`conf`	Reliability Estimation Process. DSD Tobias Koal, Daniel Scheit, Heinrich Theodor Vierhaus
2008	J	`jnl`	A Scan Controller Concept for Low Power Scan Tests. J. Low Power Electron. René Kothe, Heinrich Theodor Vierhaus
2008	C	`conf`	Basic Architecture for Logic Self Repair. IOLTS Tobias Koal, Heinrich Theodor Vierhaus
2008	C	`conf`	Embedded Diagnostic Logic Test Exploiting Regularity. DSD Heinrich Theodor Vierhaus, René Kothe
2008	J	`jnl`	Simulated fault injections and their acceleration in SystemC. Microprocess. Microsystems Silvio Misera, Heinrich Theodor Vierhaus, André Sieber
2007	C	`conf`	A Configurable Modular Test Processor and Scan Controller Architecture. IOLTS R. Frost, D. Rudolph, Christian Galke, René Kothe, Heinrich Theodor Vierhaus
2007	C	`conf`	Fault Injection Techniques and their Accelerated Simulation in SystemC. DSD Silvio Misera, Heinrich Theodor Vierhaus, André Sieber
2007	C	`conf`	Flip-Flops and Scan-Path Elements for Nanoelectronics. DDECS René Kothe, Heinrich Theodor Vierhaus
2007	C	`conf`	Timing- / Power-Optimization for Digital Logic Based on Standard Cells. DSD Heinrich Theodor Vierhaus, Helmut Rossmann, Silvio Misera
2006	C	`conf`	A Mixed Language Fault Simulation of VHDL and SystemC. DSD Silvio Misera, Heinrich Theodor Vierhaus, Lars Breitenfeld, André Sieber
2006	C	`conf`	Built-in Self Repair by Reconfiguration of FPGAs. IOLTS S. Habermann, René Kothe, Heinrich Theodor Vierhaus
2006	C	`conf`	Embedded Scan Test with Diagnostic Features for Self-Testing SoCs. IOLTS Christian Galke, René Kothe, Sabine Schultke, K. Winkler, Jeanette Honko, Heinrich Theodor Vierhaus
2006	C	`conf`	Embedded Self Repair by Transistor and Gate Level Reconfiguration. DDECS René Kothe, Heinrich Theodor Vierhaus, Torsten Coym, Wolfgang Vermeiren, Bernd Straube
2006	A	`conf`	Evaluating coverage of error detection logic for soft errors using formal methods. DATE Udo Krautz, Matthias Pflanz, Christian Jacobi, Hans-Werner Tast, Kai Weber, Heinrich Theodor Vierhaus
2006	C	`conf`	Hardware/Software Based Hierarchical Self Test for SoCs. DDECS René Kothe, Christian Galke, Sabine Schultke, Henry Fröschke, Steffen Gaede, Heinrich Theodor Vierhaus
2006	—	`conf`	Logic Self Repair. ARCS Workshops Christian Galke, René Kothe, Heinrich Theodor Vierhaus
2006	C	`conf`	Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes. DSD Christian Galke, U. Gätzschmann, Heinrich Theodor Vierhaus
2006	—	`conf`	Timing-/Power-getriebener Layout-Entwurf für Zellen-basierte Digitalschaltungen. MBMV Axel Vick, Helmut Rossmann, Heinrich Theodor Vierhaus
2005	C	`conf`	A Multi-Purpose Concept for SoC Self Test Including Diagnostic Features. IOLTS René Kothe, Christian Galke, Heinrich Theodor Vierhaus
2005	—	`conf`	Power-/Timing - Optimierung für Zellen-basierte Digitalschaltungen in Submikron-Technologien. GI Jahrestagung (1) Heinrich Theodor Vierhaus, Helmut Rossmann
2005	—	`conf`	Synchronization Fault Cryptanalysis for Breaking A5/1. WEA Marcin Gomulkiewicz, Miroslaw Kutylowski, Heinrich Theodor Vierhaus, Pawel Wlaz
2004	C	`conf`	A Hierarchical Self Test Scheme for SoCs. IOLTS Claudia Kretzschmar, Christian Galke, Heinrich Theodor Vierhaus
2004	—	`conf`	FIT - A Parallel Hierarchical Fault Simulation Environment. PARELEC Silvio Misera, Heinrich Theodor Vierhaus
2003	C	`conf`	Control Signal Protection For High Performance Processors. IOLTS Matthias Pflanz, Heinrich Theodor Vierhaus
2003	J	`jnl`	On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check. J. Electron. Test. Matthias Pflanz, Karsten Walther, Christian Galke, Heinrich Theodor Vierhaus
2003	C	`conf`	Perspectives of Combining on-line and off-line Test Technology for Dependable Systems on a Chip. IOLTS Christian Galke, Marcus Grabow, Heinrich Theodor Vierhaus
2002	C	`conf`	A Test Processor Concept for Systems-on-a-Chip. ICCD Christian Galke, Matthias Pflanz, Heinrich Theodor Vierhaus
2002	—	`conf`	On-Line Error Detection and Correction in Storage Elements with Cross-Parity Check. IOLTW Matthias Pflanz, Karsten Walther, Christian Galke, Heinrich Theodor Vierhaus
2002	—	`conf`	On-line Detection and Compensation of Transient Errors in Processor Pipeline-Structures. IOLTW Christian Galke, Matthias Pflanz, Heinrich Theodor Vierhaus
2001	A	`conf`	A register-transfer-level fault simulator for permanent and transient faults in embedded processors. DATE C. Rousselle, Matthias Pflanz, A. Behling, T. Mohaupt, Heinrich Theodor Vierhaus
2001	—	`conf`	On-line Error Detection Techniques for Dependable Embedded Processors with High Complexity. IOLTW Matthias Pflanz, Karsten Walther, Heinrich Theodor Vierhaus
2001	J	`jnl`	Online Check and Recovery Techniques for Dependable Embedded Processors. IEEE Micro Matthias Pflanz, Heinrich Theodor Vierhaus
2000	—	`conf`	A new method for on-line state machine observation for embedded microprocessors. HLDVT Matthias Pflanz, Christian Galke, Heinrich Theodor Vierhaus
1999	A	`conf`	An efficient on-line-test and back-up scheme for embedded processors. ITC Matthias Pflanz, Heinrich Theodor Vierhaus, F. Pompsch
1999	J	`jnl`	SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fulvio Corno, Uwe Gläser, Paolo Prinetto, Matteo Sonza Reorda, Heinrich Theodor Vierhaus, Massimo Violante
1998	J	`jnl`	Generating reliable embedded processors. IEEE Micro Matthias Pflanz, Heinrich Theodor Vierhaus
1997	—	`conf`	A Parallel Approach Solving the Test Generation Problem for Synchronous Sequential Circuits. PARCO H.-Ch. Dahmen, Uwe Gläser, Heinrich Theodor Vierhaus
1997	—	`conf`	An Efficient Dynamic Parallel Approach to Automatic Test Pattern Generation. Great Lakes Symposium on VLSI H.-Ch. Dahmen, Uwe Gläser, Heinrich Theodor Vierhaus
1997	J	`jnl`	Partitioning and analysis of static digital CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Uwe Hübner, Heinrich Theodor Vierhaus, Raul Camposano
1996	—	`conf`	A Design Exploration Environment. Great Lakes Symposium on VLSI Jörg Wilberg, A. Kuth, Raul Camposano, Wolfgang Rosenstiel, Heinrich Theodor Vierhaus
1996	—	`conf`	Automatic Test Pattern Generation with Optimal Load Balancing. PVM H.-Ch. Dahmen, Uwe Gläser, Heinrich Theodor Vierhaus
1996	J	`jnl`	Mixed level test generation for synchronous sequential circuits using the FOGBUSTER algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Uwe Gläser, Heinrich Theodor Vierhaus
1995	—	`conf`	FOGBUSTER: an efficient algorithm for sequential test generation. EURO-DAC Uwe Gläser, Heinrich Theodor Vierhaus
1995	—	`conf`	Gate delay fault test generation for non-scan circuits. ED&TC G. Van Brakel, Uwe Gläser, Hans G. Kerkhoff, Heinrich Theodor Vierhaus
1995	Misc	`conf`	Improving topological ATPG with symbolic techniques. VTS Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Uwe Gläser, Heinrich Theodor Vierhaus
1994	—	`conf`	Local microcode generation in system design. Code Generation for Embedded Processors Michel Langevin, Eduard Cerny, Jörg Wilberg, Heinrich Theodor Vierhaus
1994	A	`conf`	Test generation for bridging faults in CMOS ICs based on current monitoring versus signal propagation. ICCAD Uwe Gläser, Heinrich Theodor Vierhaus, M. Kley, A. Wiederhold
1994	C	`conf`	Testability Analysis for Test Generation in Synchronous Sequential Circuits. ICCD R. Wolber, Uwe Gläser, Heinrich Theodor Vierhaus
1993	A	`conf`	CMOS Bridges and Resistive Transistor Faults: I ITC Heinrich Theodor Vierhaus, Wolfgang Meyer, Uwe Gläser
1993	J	`jnl`	Fault behavior and testability of asynchronous CMOS circuits. Microprocess. Microprogramming Heinrich Theodor Vierhaus, Wolfgang Meyer, Uwe Gläser, Raul Camposano
1992	J	`jnl`	CMOS transistor faults and bridging faults: Testability by delay effects and overcurrents. Microprocess. Microprogramming Uwe Hübner, Wolfgang Meyer, Heinrich Theodor Vierhaus
1992	A	`conf`	Efficient partitioning and analysis of digital CMOS-circuits. ICCAD Uwe Hübner, Heinrich Theodor Vierhaus
1992	C	`conf`	Library Mapping of CMOS-Switch-Level-Circuits by Extraction of Isomorphic Subgraphs. ICCD Ursula Westerholz, Heinrich Theodor Vierhaus
1992	—	`conf`	MILEF: an efficient approach to mixed level automatic test pattern generation. EURO-DAC Uwe Gläser, Heinrich Theodor Vierhaus
1992	A	`conf`	Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects. ITC Uwe Gläser, Uwe Hübner, Heinrich Theodor Vierhaus
1991	J	`jnl`	Mixed level test generation for high fault coverage. Microprocessing and Microprogramming Uwe Hübner, H. Hinsen, M. Hofebauer, Heinrich Theodor Vierhaus
1990	J	`jnl`	CMOS layout generation for improved testability. Microprocessing and Microprogramming Olaf Stern, Heinrich Theodor Vierhaus
1989	J	`jnl`	Testability of non-trivial CMOS faults under realistic conditions. Microprocessing and Microprogramming Heinrich Theodor Vierhaus
1988	J	`jnl`	CMOS fault modeling, test generation and design for testability. Microprocess. Microprogramming C. Matthäus, B. Krüger-Sprengel, C. Glowacz, Uwe Hübner, Heinrich Theodor Vierhaus