Heinrich Meyr - RankMe

226 papers A* 14A 24B 21C 12Misc 21Journal 82Unranked 48

Year	Rank	Type	Title / Venue / Authors
2020	A*	`conf`	Observability Analysis of Flight State Estimation for UAVs and Experimental Validation. ICRA Peng Huang, Heinrich Meyr, Meik Dörpinghaus, Gerhard P. Fettweis
2018	J	`jnl`	Testing Optimality of Sequential Decision-Making. CoRR Meik Dörpinghaus, Izaak Neri, Édgar Roldán, Heinrich Meyr, Frank Jülicher
2017	B	`conf`	An information theoretic analysis of sequential decision-making. ISIT Meik Dorpinghaus, Édgar Roldán, Izaak Neri, Heinrich Meyr, Frank Jülicher
2017	J	`jnl`	On the Performance Gap Between ML and Iterative Decoding of Finite-Length Turbo-Coded BICM in MIMO Systems. IEEE Trans. Commun. Dan Zhang, Heinrich Meyr
2015	J	`jnl`	An Information Theoretic Analysis of Sequential Decision-Making. CoRR Meik Dörpinghaus, Édgar Roldán, Izaak Neri, Heinrich Meyr, Frank Jülicher
2015	B	`conf`	Channel-aware local search (CA-LS) for iterative MIMO detection. PIMRC I-Wei Lai, Chia-Han Lee, Gerd Ascheid, Heinrich Meyr, Tzi-Dar Chiueh
2014	J	`jnl`	Oversampling Increases the Pre-Log of Noncoherent Fading Channels. CoRR Meik Dörpinghaus, Günther Koliander, Giuseppe Durisi, Erwin Riegler, Heinrich Meyr
2014	J	`jnl`	Oversampling Increases the Pre-Log of Noncoherent Rayleigh Fading Channels. IEEE Trans. Inf. Theory Meik Dörpinghaus, Günther Koliander, Giuseppe Durisi, Erwin Riegler, Heinrich Meyr
2013	J	`jnl`	On the Achievable Rate of Stationary Rayleigh Flat-Fading Channels With Gaussian Inputs. IEEE Trans. Inf. Theory Meik Dorpinghaus, Heinrich Meyr, Rudolf Mathar
2012	—	`conf`	A 2.78 mm ESSCIRC Filippo Borlenghi, Ernst Martin Witte, Gerd Ascheid, Heinrich Meyr, Andreas Burg
2012	—	`conf`	An FPGA-accelerated testbed for hardware component development in MIMO wireless communication systems. ICSAMOS Filippo Borlenghi, Dominik Auras, Ernst Martin Witte, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
2012	J	`jnl`	Asymptotic Coded BER Analysis for MIMO BICM-ID with Quantized Extrinsic LLR. IEEE Trans. Commun. I-Wei Lai, Chien-Yi Wang, Tzi-Dar Chiueh, Gerd Ascheid, Heinrich Meyr
2012	J	`jnl`	On the Gain of Joint Processing of Pilot and Data Symbols in Stationary Rayleigh Fading Channels. IEEE Trans. Inf. Theory Meik Dorpinghaus, Adrian Ispas, Heinrich Meyr
2012	—	`conf`	Parallel paradigms and run-time management techniques for many-core architectures: the 2PARMA approach. INA-OCMC@HiPEAC Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Ettore Speziale, Diego Melpignano, J. M. Zins, David Siorpaes, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Alexandros Bartzas, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Heinrich Meyr, Junaid Ansari, Petri Mähönen, Bart Vanthournout
2012	B	`conf`	Searching for optimal scheduling of MIMO doubly iterative receivers: An ant colony optimization-based method. GLOBECOM Dan Zhang, Gaojian Wang, Gerd Ascheid, Heinrich Meyr
2011	—	`conf`	A 772Mbit/s 8.81bit/nJ 90nm CMOS soft-input soft-output sphere decoder. A-SSCC Filippo Borlenghi, Ernst Martin Witte, Gerd Ascheid, Heinrich Meyr, Andreas Peter Burg
2011	J	`jnl`	A retargetable framework for compiler/architecture co-development. Des. Autom. Embed. Syst. Hanno Scharwächter, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2011	—	`conf`	Achievable rate with receivers using iterative channel estimation in stationary fading channels. ISWCS Meik Dorpinghaus, Adrian Ispas, Heinrich Meyr
2011	—	`conf`	Asymptotic BER Analysis for MIMO-BICM with MMSE Detection and Channel Estimation. ICC I-Wei Lai, Gerd Ascheid, Heinrich Meyr, Tzi-Dar Chiueh
2011	J	`jnl`	Efficient Channel-Adaptive MIMO Detection Using Just-Acceptable Error Rate. IEEE Trans. Wirel. Commun. I-Wei Lai, Gerd Ascheid, Heinrich Meyr, Tzi-Dar Chiueh
2011	J	`jnl`	On Complexity, Energy- and Implementation-Efficiency of Channel Decoders. IEEE Trans. Commun. Frank Kienle, Norbert Wehn, Heinrich Meyr
2011	J	`jnl`	On the Achievable Rate of Stationary Rayleigh Flat-Fading Channels with Gaussian Inputs CoRR Meik Dörpinghaus, Heinrich Meyr
2011	J	`jnl`	On the Gain of Joint Processing of Pilot and Data Symbols in Stationary Rayleigh Fading Channels CoRR Meik Dörpinghaus, Adrian Ispas, Heinrich Meyr
2010	—	`conf`	2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures. ISVLSI Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Andrea Di Biagio, Ettore Speziale, Michele Tartara, David Siorpaes, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Alexandros Bartzas, Sotirios Xydis, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Junaid Ansari, Petri Mähönen, Bart Vanthournout
2010	—	`conf`	2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures. ISVLSI (Selected papers) Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Andrea Di Biagio, Ettore Speziale, Michele Tartara, Diego Melpignano, J. M. Zins, David Siorpaes, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Alexandros Bartzas, Sotirios Xydis, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Junaid Ansari, Petri Mähönen, Bart Vanthournout
2010	J	`jnl`	A Scalable VLSI Architecture for Soft-Input Soft-Output Single Tree-Search Sphere Decoding. IEEE Trans. Circuits Syst. II Express Briefs Ernst Martin Witte, Filippo Borlenghi, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
2010	J	`jnl`	A Systematic Framework for Iterative Maximum Likelihood Receiver Design. IEEE Trans. Commun. Lars Schmitt, Heinrich Meyr
2010	J	`jnl`	Analytical and Simulation-based Design Space Exploration of Software Defined Radios. Int. J. Parallel Program. Torsten Kempf, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
2010	J	`jnl`	Automatic Generation of Memory Interfaces for ASIPs. Int. J. Embed. Real Time Commun. Syst. David Kammler, Ernst Martin Witte, Anupam Chattopadhyay, Bastian Bauwens, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
2010	C	`conf`	BER analysis for MIMO BICM-ID assuming finite precision of extrinsic LLR. ISITA Chien-Yi Wang, I-Wei Lai, Tzi-Dar Chiueh, Gerd Ascheid, Heinrich Meyr
2010	Misc	`conf`	Iterative channel estimation control for MIMO-OFDM Systems. CISS Dan Zhang, Konstantinos Nikitopoulos, I-Wei Lai, Gerd Ascheid, Heinrich Meyr
2010	J	`jnl`	On Complexity, Energy- and Implementation-Efficiency of Channel Decoders CoRR Frank Kienle, Norbert Wehn, Heinrich Meyr
2010	J	`jnl`	Systematic Design of Iterative ML Receivers for Flat Fading Channels. IEEE Trans. Commun. Lars Schmitt, Heinrich Meyr, Dan Zhang
2010	C	`conf`	The achievable rate of stationary rayleigh flat-fading channels with IID input symbols. ISITA Meik Dorpinghaus, Heinrich Meyr, Gerd Ascheid
2010	A	`conf`	Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms. DATE Jerónimo Castrillón, Ricardo Velasquez, Anastasia Stulova, Weihua Sheng, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2009	—	`conf`	A Fast and Flexible Platform for Fault Injection and Evaluation in Verilog-Based Simulations. SSIRI David Kammler, Junqing Guan, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
2009	—	`conf`	A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs). SAMOS Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2009	J	`jnl`	A SIMD optimization framework for retargetable compilers. ACM Trans. Archit. Code Optim. Manuel Hohenauer, Felix Engel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2009	J	`jnl`	A Scalable VLSI Architecture for Soft-Input Soft-Output Depth-First Sphere Decoding CoRR Ernst Martin Witte, Filippo Borlenghi, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
2009	Misc	`conf`	A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios. VLSI Design Torsten Kempf, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
2009	Misc	`conf`	A high-level virtual platform for early MPSoC software development. CODES+ISSS Jianjiang Ceng, Weihua Sheng, Jerónimo Castrillón, Anastasia Stulova, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2009	—	`conf`	Automatic generation of memory interfaces. SoC David Kammler, Bastian Bauwens, Ernst Martin Witte, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Anupam Chattopadhyay
2009	B	`conf`	Combining orthogonalized partial metrics: Efficient enumeration for soft-input sphere decoder. PIMRC Chun-Hao Liao, I-Wei Lai, Konstantinos Nikitopoulos, Filippo Borlenghi, David Kammler, Ernst Martin Witte, Dan Zhang, Tzi-Dar Chiueh, Gerd Ascheid, Heinrich Meyr
2009	J	`jnl`	Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves. IACR Cryptol. ePrint Arch. David Kammler, Diandian Zhang, Peter Schwabe, Hanno Scharwächter, Markus Langenberg, Dominik Auras, Gerd Ascheid, Rainer Leupers, Rudolf Mathar, Heinrich Meyr
2009	J	`jnl`	Efficient And Portable SDR Waveform Development: The Nucleus Concept CoRR Venkatesh Ramakrishnan, Ernst Martin Witte, Torsten Kempf, David Kammler, Gerd Ascheid, Heinrich Meyr, Marc Adrat, Markus Antweiler
2009	B	`conf`	Efficient implementations from libraries: Analyzing the influence of configuration parameters on key performance properties. PIMRC Venkatesh Ramakrishnan, Joschka zur Jacobsmuehlen, I-Wei Lai, Torsten Kempf, Marc Adrat, Gerd Ascheid, Markus Antweiler, Heinrich Meyr
2009	J	`jnl`	Integrated verification approach during ADL-driven processor design. Microelectron. J. Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2009	—	`conf`	Low-Complexity Channel-Adaptive MIMO Detection with Just-Acceptable Error Rate. VTC Spring I-Wei Lai, Gerd Ascheid, Heinrich Meyr, Tzi-Dar Chiueh
2009	B	`conf`	Searching in the Delta Lattice: An Efficient MIMO Detection for Iterative Receivers. GLOBECOM I-Wei Lai, Chun-Hao Liao, Ernst Martin Witte, David Kammler, Filippo Borlenghi, Konstantinos Nikitopoulos, Venkatesh Ramakrishnan, Dan Zhang, Tzi-Dar Chiueh, Gerd Ascheid, Heinrich Meyr
2009	Misc	`conf`	TotalProf: a fast and accurate retargetable source code profiler. CODES+ISSS Lei Gao, Jia Huang, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2008	J	`jnl`	A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors. IEEE Trans. Very Large Scale Integr. Syst. Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Chen, David Kammler, Ling Hao, Rainer Leupers, Heinrich Meyr, Gerd Ascheid
2008	—	`conf`	Asymptotic BER Analysis for MIMO-BICM with Zero-Forcing Detectors Assuming Imperfect CSI. ICC I-Wei Lai, Susanne Godtmann, Tzi-Dar Chiueh, Gerd Ascheid, Heinrich Meyr
2008	A	`conf`	High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures. DATE Anupam Chattopadhyay, Xiaolin Chen, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2008	—	`conf`	Long-Term Beamforming in Single Frequency Networks using Semidefinite Relaxation. VTC Spring Markus Jordan, Martin Senst, Gerd Ascheid, Heinrich Meyr
2008	A*	`conf`	MAPS: an integrated framework for MPSoC application parallelization. DAC Jianjiang Ceng, Jerónimo Castrillón, Weihua Sheng, Hanno Scharwächter, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tsuyoshi Isshiki, Hiroaki Kunieda
2008	A*	`conf`	Multiprocessor performance estimation using hybrid simulation. DAC Lei Gao, Kingshuk Karuri, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2008	B	`conf`	Optimal PSK signaling over stationary Rayleigh fading channels. ISIT Meik Dörpinghaus, Gerd Ascheid, Heinrich Meyr, Rudolf Mathar
2008	J	`jnl`	Power-efficient Instruction Encoding Optimization for Various Architecture Classes. J. Comput. Diandian Zhang, Anupam Chattopadhyay, David Kammler, Ernst Martin Witte, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
2008	J	`jnl`	Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors. ACM Trans. Embed. Comput. Syst. Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2008	A	`conf`	Retargetable Code Optimization for Predicated Execution. DATE Manuel Hohenauer, Felix Engel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gerrit Bette, Balpreet Singh
2008	J	`jnl`	SoC multiprocessor debugging and synchronisation using generic dynamic-connect debugger frontends. Int. J. Embed. Syst. Andreas Wieferink, Tim Kogel, Olaf Zerres, Rainer Leupers, Heinrich Meyr
2008	J	`jnl`	Tight Approximation of the Bit Error Rate for BICM(-ID) Assuming Imperfect CSI. IEEE Trans. Wirel. Commun. Susanne Godtmann, I-Wei Lai, Gerd Ascheid, Tzi-Dar Chiueh, Heinrich Meyr
2008	J	`jnl`	Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips. Int. J. Embed. Syst. Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Heinrich Meyr
2007	Misc	`conf`	A code-generator generator for multi-output instructions. CODES+ISSS Hanno Scharwächter, Jonghee M. Youn, Rainer Leupers, Yunheung Paek, Gerd Ascheid, Heinrich Meyr
2007	Misc	`conf`	A fast and generic hybrid simulation approach using C virtual machine. CASES Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2007	J	`jnl`	ASIP architecture exploration for efficient IPSec encryption: A case study. ACM Trans. Embed. Comput. Syst. Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2007	A	`conf`	Design space exploration of partially re-configurable embedded processors. DATE Anupam Chattopadhyay, W. Ahmed, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2007	Misc	`conf`	HySim: a fast simulation framework for embedded software development. CODES+ISSS Stefan Kraemer, Lei Gao, Jan Weinstock, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2007	A	`conf`	Increasing data-bandwidth to instruction-set extensions through register clustering. ICCAD Kingshuk Karuri, Anupam Chattopadhyay, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2007	A	`conf`	Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations. DATE Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2007	B	`conf`	Joint Reduction of Peak-to-Average Power Ratio and Out-of-Band Power in OFDM Systems. GLOBECOM Martin Senst, Markus Jordan, Meik Dorpinghaus, Michael Farber, Gerd Ascheid, Heinrich Meyr
2007	—	`conf`	On the Influence of Pilot Symbol and Data Symbol Positioning on Turbo Synchronization. VTC Spring Susanne Godtmann, André Pollok, Niels Hadaschik, Gerd Ascheid, Heinrich Meyr
2007	—	`book`	Optimized ASIP synthesis from architecture description language models. Oliver Schliebusch, Heinrich Meyr, Rainer Leupers
2007	—	`conf`	Performance Evaluation of Opportunistic Beamforming with SINR Prediction for HSDPA. VTC Spring Markus Jordan, Gerd Ascheid, Heinrich Meyr
2007	C	`conf`	Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors. IEEE International Workshop on Rapid System Prototyping Anupam Chattopadhyay, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2007	B	`conf`	Prediction of Downlink SNR for Opportunistic Beamforming. WCNC Markus Jordan, Lars Schmitt, Gerd Ascheid, Heinrich Meyr
2006	A	`conf`	A SW performance estimation framework for early system-level-design using fine-grained instrumentation. DATE Torsten Kempf, Kingshuk Karuri, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
2006	—	`conf`	ASIP design and synthesis for non linear filtering in image processing. DATE Designers' Forum Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
2006	B	`conf`	Achievable Data Rate of Wideband OFDM With Data-Aided Channel Estimation. PIMRC Niels Hadaschik, Gerd Ascheid, Heinrich Meyr
2006	C	`conf`	An efficient parallelization technique for high throughput FFT-ASIPs. ISCAS Harold Ishebabi, Gerd Ascheid, Heinrich Meyr, Oguzhan Atak, Abdullah Atalar, Erdal Arikan
2006	A	`conf`	An interprocedural code optimization technique for network processors using hardware multi-threading support. DATE Hanno Scharwächter, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2006	A	`conf`	Automatic ADL-based operand isolation for embedded processors. DATE Anupam Chattopadhyay, Benedikt Geukes, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2006	—	`conf`	Design and implementation of a modular and portable IEEE 754 compliant floating-point unit. DATE Designers' Forum Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Monu Kedia
2006	—	`conf`	Design of Application Specific Processors for the Cached FFT Algorithm. ICASSP (3) Oguzhan Atak, Abdullah Atalar, Erdal Arikan, Harold Ishebabi, David Kammler, Gerd Ascheid, Heinrich Meyr, Mario Nicola, Guido Masera
2006	—	`conf`	Enhanced Predictive Up/Down Power Control for CDMA Systems. ICC Meik Dörpinghaus, Lars Schmitt, Ingo Viering, Axel Klein, Joachim Schmid, Gerd Ascheid, Heinrich Meyr
2006	A	`conf`	Flexibility and low power: a contradiction in terms? ISLPED Peter Wintermayr, Reiner W. Hartenstein, Heinrich Meyr, Steve Leibson
2006	C	`conf`	Integrated Verification Approach during ADL-Driven Processor Design. IEEE International Workshop on Rapid System Prototyping Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2006	—	`book`	Integrated system-level modeling of network-on-chip enabled multi-processor platforms. Tim Kogel, Rainer Leupers, Heinrich Meyr
2006	—	`conf`	Memory Access Micro-Profiling for ASIP Design. DELTA Kingshuk Karuri, Christian Huben, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2006	J	`jnl`	Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. J. VLSI Signal Process. Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun
2006	Misc	`conf`	Retargetable code optimization with SIMD instructions. CODES+ISSS Manuel Hohenauer, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Hans van Someren
2005	A	`conf`	A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms. DATE Torsten Kempf, Malte Doerper, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tim Kogel, Bart Vanthournout
2005	—	`conf`	A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. ASP-DAC Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel
2005	A	`conf`	C Compiler Retargeting Based on Instruction Semantics Models. DATE Jianjiang Ceng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun
2005	A*	`conf`	Fine-grained application source code profiling for ASIP design. DAC Kingshuk Karuri, Mohammad Abdullah Al Faruque, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2005	—	`conf`	Improving MIMO phase noise estimation by exploiting spatial correlations. ICASSP (3) Niels Hadaschik, Meik Dörpinghaus, Andreas Senst, Ole Harmjanz, Uwe Käufer, Gerd Ascheid, Heinrich Meyr
2005	—	`conf`	Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study. ASAP Mohammad Mostafizur Rahman Mozumdar, Kingshuk Karuri, Anupam Chattopadhyay, Stefan Kraemer, Hanno Scharwächter, Heinrich Meyr, Gerd Ascheid, Rainer Leupers
2005	C	`conf`	Optimization Techniques for ADL-Driven RTL Processor Synthesis. IEEE International Workshop on Rapid System Prototyping Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
2005	Misc	`conf`	Retargetable generation of TLM bus interfaces for MP-SoC platforms. CODES+ISSS Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel
2004	A	`conf`	A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models. DATE Manuel Hohenauer, Hanno Scharwächter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Hans van Someren
2004	A	`conf`	A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform. DATE Andreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Achim Nohl
2004	A*	`conf`	A novel approach for flexible and consistent ADL-driven ASIP design. DAC Gunnar Braun, Achim Nohl, Weihua Sheng, Jianjiang Ceng, Manuel Hohenauer, Hanno Scharwächter, Rainer Leupers, Heinrich Meyr
2004	J	`jnl`	A universal technique for fast and flexible instruction-set architecture simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gunnar Braun, Achim Nohl, Andreas Hoffmann, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr
2004	C	`conf`	ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study. SCOPES Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2004	—	`conf`	Application specific instruction-set processors (ASIP's) for wireless communications: design, cost, and energy efficiency vs. flexibility. SoC Heinrich Meyr
2004	—	`conf`	Early ISS Integration into Network-on-Chip Designs. SAMOS Andreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2004	A*	`conf`	Heterogeneous MP-SoC: the solution to energy-efficient signal processing. DAC Tim Kogel, Heinrich Meyr
2004	—	`conf`	Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. SAMOS Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun
2004	—	`conf`	Performance of initial synchronization schemes for WCDMA systems with spatio-temporal correlations. ICC Lars Schmitt, Thomas Grundler, Christoph Schreyoegg, Gerd Ascheid, Heinrich Meyr
2004	A	`conf`	RTL Processor Synthesis for Architecture Exploration and Implementation. DATE Oliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl
2004	—	`conf`	Random beamforming in correlated MISO channels for multiuser systems. ICC Andreas Senst, Peter Schulz-Rittich, Ulrich Krause, Gerd Ascheid, Heinrich Meyr
2004	—	`conf`	Stochastic modeling of the convergence behavior of concatenated codes. VTC Fall (2) Rudolf Mathar, Heinrich Meyr
2004	—	`conf`	Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs. SAMOS Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2003	Misc	`conf`	A modular simulation framework for architectural exploration of on-chip interconnection networks. CODES+ISSS Tim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Serge Goossens
2003	C	`conf`	Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models. SCOPES Oliver Wahlen, Manuel Hohenauer, Gunnar Braun, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Xiaoning Nie
2003	B	`conf`	Initial synchronization of W-CDMA systems using a power-scaled detector with antenna diversity in frequency-selective Rayleigh fading channels. GLOBECOM Lars Schmitt, Volker Simon, Thomas Grundler, Christoph Schreyoegg, Heinrich Meyr
2003	J	`jnl`	Instruction Scheduler Generation for Retargetable Compilation. IEEE Des. Test Comput. Oliver Wahlen, Manuel Hohenauer, Rainer Leupers, Heinrich Meyr
2003	A*	`conf`	Instruction encoding synthesis for architecture exploration using hierarchical processor models. DAC Achim Nohl, Volker Greive, Gunnar Braun, Andreas Hoffmann, Rainer Leupers, Oliver Schliebusch, Heinrich Meyr
2003	J	`jnl`	Methodical Low-Power ASIP Design Space Exploration. J. VLSI Signal Process. Tilman Glökler, Andreas Hoffmann, Heinrich Meyr
2003	A	`conf`	Processor/Memory Co-Exploration on Multiple Abstraction Levels. DATE Gunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl
2003	B	`conf`	Synchronization requirements for COFDM systems with transmit diversity. GLOBECOM Michael Speth, Heinrich Meyr
2003	B	`conf`	The effect of imperfect SNR knowledge on multiantenna multiuser systems with channel aware scheduling. GLOBECOM Peter Schulz-Rittich, Andreas Senst, Thomas Bilke, Heinrich Meyr
2002	A*	`conf`	A universal technique for fast and flexible instruction-set architecture simulation. DAC Achim Nohl, Gunnar Braun, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Andreas Hoffmann
2002	—	`conf`	Application specific compiler/architecture codesign: a case study. LCTES-SCOPES Oliver Wahlen, Tilman Glökler, Achim Nohl, Andreas Hoffmann, Rainer Leupers, Heinrich Meyr
2002	—	`conf`	Architecture Implementation Using the Machine Description Language LISA. ASP-DAC/VLSI Design Oliver Schliebusch, Andreas Hoffmann, Achim Nohl, Gunnar Braun, Heinrich Meyr
2002	—	`book`	Architecture exploration for embedded processors with LISA. Andreas Hoffmann, Heinrich Meyr, Rainer Leupers
2002	J	`jnl`	Design and DSP Implementation of Fixed-Point Systems. EURASIP J. Adv. Signal Process. Martin Coors, Holger Keding, Olaf Lüthje, Heinrich Meyr
2002	A	`conf`	Designing SoC's. ISLPED Tobias Noll, Heinrich Meyr
2002	—	`conf`	Low complexity high resolution subspace-based delay estimation for DS-CDMA. ICC Gunnar Fock, Peter Schulz-Rittich, Andreas Schenke, Heinrich Meyr
2001	A	`conf`	A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) using the Machine Description Language LISA. ICCAD Andreas Hoffmann, Oliver Schliebusch, Achim Nohl, Gunnar Braun, Oliver Wahlen, Heinrich Meyr
2001	A	`conf`	A framework for fast hardware-software co-simulation. DATE Andreas Hoffmann, Tim Kogel, Heinrich Meyr
2001	J	`jnl`	A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andreas Hoffmann, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink, Heinrich Meyr
2001	Misc	`conf`	A survey on modeling issues using the machine description language LISA. ICASSP Andreas Hoffmann, Achim Nohl, Gunnar Braun, Heinrich Meyr
2001	J	`jnl`	Achievable rate of MIMO channels with data-aided channel estimation and perfect interleaving. IEEE J. Sel. Areas Commun. Jens Baltersee, Gunnar Fock, Heinrich Meyr
2001	B	`conf`	Achievable rate of MIMO channels with data-aided channel estimation. ITW Jens Baltersee, Gunnar Fock, Heinrich Meyr
2001	J	`jnl`	An information theoretic foundation of synchronized detection. IEEE Trans. Commun. Jens Baltersee, Gunnar Fock, Heinrich Meyr
2001	J	`jnl`	Channel tracking for RAKE receivers in closely spaced multipath environments. IEEE J. Sel. Areas Commun. Gunnar Fock, Jens Baltersee, Peter Schulz-Rittich, Heinrich Meyr
2001	A*	`conf`	Fast Bit-True Simulation. DAC Holger Keding, Martin Coors, Olaf Lüthje, Heinrich Meyr
2001	A	`conf`	Generating production quality software development tools using a machine description language. DATE Andreas Hoffmann, Achim Nohl, Stefan Pees, Gunnar Braun, Heinrich Meyr
2001	Misc	`conf`	Integer code generation for the TI TMS320C62X. ICASSP Martin Coors, Holger Keding, Olaf Lüthje, Heinrich Meyr
2001	J	`jnl`	Optimum receiver design for OFDM-based broadband transmission .II. A case study. IEEE Trans. Commun. Michael Speth, Stefan A. Fechtel, Gunnar Fock, Heinrich Meyr
2001	A	`conf`	The programmable platform: does one size fit all? DATE A. Lock, Raul Camposano, Heinrich Meyr
2001	—	`conf`	Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description. ISSS Gunnar Braun, Andreas Hoffmann, Achim Nohl, Heinrich Meyr
2000	Misc	`conf`	DSP core verification using automatic test case generation. ICASSP Tilman Glökler, Stefan Bitterlich, Heinrich Meyr
2000	A*	`conf`	Efficient building block based RTL code generation from synchronous data flow graphs. DAC Jens Horstmannshoff, Heinrich Meyr
2000	—	`conf`	Iterative Multiuser Detection for Bit Interleaved Coed Modulation. ICC (2) Michael Speth, Alexander Jansen, Heinrich Meyr
2000	J	`jnl`	Retargetable compiled simulation of embedded processors using a machine description language. ACM Trans. Design Autom. Electr. Syst. Stefan Pees, Andreas Hoffmann, Heinrich Meyr
2000	A	`conf`	Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description Language. DATE Stefan Pees, Andreas Hoffmann, Heinrich Meyr
1999	A*	`conf`	LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures. DAC Stefan Pees, Andreas Hoffmann, Vojin Zivojnovic, Heinrich Meyr
1999	—	`conf`	Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs. ISSS Jens Horstmannshoff, Heinrich Meyr
1999	J	`jnl`	Optimum receiver design for wireless broad-band systems using OFDM. I. IEEE Trans. Commun. Michael Speth, Stefan A. Fechtel, Gunnar Fock, Heinrich Meyr
1999	J	`jnl`	Schnelle Simulation des TI-TMS320C54x DSP. Informationstechnik Tech. Inform. Stefan Pees, Andreas Hoffmann, Andreas Ropers, Heinrich Meyr
1998	J	`jnl`	An Aliasing-Free Receiver with Variable Sample Rate Digital Feedback M/T NDA Timing Synchronization. Wirel. Pers. Commun. Uwe Lambrette, Klaus Langhammer, Heinrich Meyr
1998	J	`jnl`	Design Methodology for a DVB Satellite Receiver ASIC. Des. Autom. Embed. Syst. Martin Vaupel, Uwe Lambrette, Herbert Dawid, Olaf J. Joeressen, Stefan Bitterlich, Heinrich Meyr, Focko Frieling, Karsten Müller, Götz Kluge
1998	—	`book`	Digital communication receivers - synchronization, channel estimation, and signal processing. Heinrich Meyr, Marc Moeneclaey, Stefan A. Fechtel
1998	A	`conf`	FRIDGE: A Fixed-Point Design and Simulation Environment. DATE Holger Keding, Markus Willems, Martin Coors, Heinrich Meyr
1997	Misc	`conf`	An upper bound of the throughput of multirate multiprocessor schedules. ICASSP Rainer Schoenen, Vojin Zivojnovic, Heinrich Meyr
1997	J	`jnl`	Authors' reply [to "Comment on cycle slips in synchronizers subject to smooth narrow-band loop noise"]. IEEE Trans. Commun. Marc Moeneclaey, Heinrich Meyr
1997	J	`jnl`	Compiled Simulation of Programmable DSP Architectures. J. VLSI Signal Process. Vojin Zivojnovic, Steven W. K. Tjiang, Heinrich Meyr
1997	Misc	`conf`	FRIDGE: an interactive code generation environment for HW/SW codesign. ICASSP Markus Willems, Volker Bürsgens, Thorsten Grötker, Heinrich Meyr
1997	—	`conf`	Mapping multirate dataflow to complex RT level hardware models. ASAP Jens Horstmannshoff, Thorsten Grötker, Heinrich Meyr
1997	Misc	`conf`	Modulo-addressing utilization in automatic software synthesis for digital signal processors. ICASSP Markus Willems, Holger Keding, Vojin Zivojnovic, Heinrich Meyr
1997	J	`jnl`	OFDM burst frequency synchronization by single carrier training data. IEEE Commun. Lett. Uwe Lambrette, Michael Speth, Heinrich Meyr
1997	—	`conf`	On core and more: a design perspective for systems-on-a-chip. ASAP Stefan Pees, Martin Vaupel, Vojin Zivojnovic, Heinrich Meyr
1997	—	`conf`	PCC: a modeling technique for mixed control/data flow systems. ED&TC Thorsten Grötker, Rainer Schoenen, Heinrich Meyr
1997	A*	`conf`	System Level Fixed-Point Design Based on an Interpolative Approach. DAC Markus Willems, Volker Bürsgens, Holger Keding, Thorsten Grötker, Heinrich Meyr
1997	Misc	`conf`	Unified specification of control and data flow. ICASSP Thorsten Grötker, Rainer Schoenen, Heinrich Meyr
1996	J	`jnl`	A CMOS IC for Gb/s Viterbi decoding: system design and VLSI implementation. IEEE Trans. Very Large Scale Integr. Syst. Herbert Dawid, Gerhard P. Fettweis, Heinrich Meyr
1996	J	`jnl`	Codesign of a parallel architecture and an optimizing compiler backend: SIN rete processing as a case study. Des. Autom. Embed. Syst. Klaus ten Hagen, Dirk Steinberg, Heinrich Meyr
1996	A*	`conf`	Compiled HW/SW Co-Simulation. DAC Vojin Zivojnovic, Heinrich Meyr
1996	—	`conf`	DSP Processor/Compiler Co-Design: A Quantitative Approach. ISSS Vojin Zivojnovic, Stefan Pees, C. Schälger, Markus Willems, Rainer Schoenen, Heinrich Meyr
1996	J	`jnl`	The Differential CORDIC Algorithm: Constant Scale Factor Redundant Implementation without Correcting Iterations. IEEE Trans. Computers Herbert Dawid, Heinrich Meyr
1995	J	`jnl`	A 40 Mb/s soft-output Viterbi decoder. IEEE J. Solid State Circuits Olaf J. Joeressen, Heinrich Meyr
1995	Misc	`conf`	ADEN: an environment for digital receiver ASIC design. ICASSP Thorsten Grötker, Peter Zepter, Heinrich Meyr
1995	J	`jnl`	Advanced digital receiver principles and technologies for PCS. IEEE Commun. Mag. Heinrich Meyr, Ravi Subramanian
1995	Misc	`conf`	DSP-based mobile and satellite receivers, from algorithm to implementation: a design course at Aachen University of Technology. ICASSP Oliver Mauss, Matthias Pankert, Ferdinand Classen, Heinrich Meyr
1995	A*	`conf`	Digital Receiver Design Using VHDL Generation from Data Flow Graphs. DAC Peter Zepter, Thorsten Grötker, Heinrich Meyr
1995	B	`conf`	Real-time algorithms and VLSI architectures for soft output MAP convolutional decoding. PIMRC Herbert Dawid, Heinrich Meyr
1995	Misc	`conf`	Scheduling for optimum data memory compaction in block diagram oriented software synthesis. ICASSP Sebastian Ritz, Markus Willems, Heinrich Meyr
1995	A	`conf`	Test Point Insertion for an Area Efficient BIST. ITC Claus Schotten, Heinrich Meyr
1995	B	`conf`	Viterbi decoding with dual timescale traceback processing. PIMRC Olaf J. Joeressen, Heinrich Meyr
1994	B	`conf`	A digital feedforward differential detection MSK receiver for packet-based mobile radio. VTC Uwe Lambrette, Heinrich Meyr
1994	—	`conf`	Dynamic data flow and control flow in high level DSP code synthesis. ICASSP (2) Matthias Pankert, Oliver Mauss, Sebastian Ritz, Heinrich Meyr
1994	B	`conf`	Frequency synchronization algorithms for OFDM systems suitable for communication over frequency selective fading channels. VTC Ferdinand Classen, Heinrich Meyr
1994	C	`conf`	High Speed FIR-Filter Architectures with Scalable Sample Rates. ISCAS Martin Vaupel, Heinrich Meyr
1994	J	`jnl`	High-speed VLSI architectures for soft-output viterbi decoding. J. VLSI Signal Process. Olaf J. Joeressen, Martin Vaupel, Heinrich Meyr
1994	B	`conf`	Improved frame synchronization for spontaneous packet transmission over frequency-selective radio channels. PIMRC Stefan A. Fechtel, Heinrich Meyr
1994	C	`conf`	Is it Possible to achieve a Teraflop/s on a chip? From High Performance Algorithms to Architectures. ISCAS Francky Catthoor, Ed F. Deprettere, Yu Hen Hu, Jan M. Rabaey, Heinrich Meyr, Lothar Thiele
1994	J	`jnl`	On sampling rate, analog prefiltering, and sufficient statistics for digital receivers. IEEE Trans. Commun. Heinrich Meyr, Martin Oerder, Andreas Polydoros
1994	J	`jnl`	Optimal parametric feedforward estimation of frequency-selective fading radio channels. IEEE Trans. Commun. Stefan A. Fechtel, Heinrich Meyr
1994	—	`conf`	Retiming of DSP programs for optimum vectorization. ICASSP (2) Vojin Zivojnovic, Sebastian Ritz, Heinrich Meyr
1993	C	`conf`	Design of optimum interpolation filters for digital demodulators. ISCAS Vojin Zivojnovic, Heinrich Meyr
1993	—	`conf`	Efficient scalable architectures for Viterbi decoders. ASAP Stefan Bitterlich, Heinrich Meyr
1993	J	`jnl`	High-Level Software Synthesis for the Design of Communication Systems. IEEE J. Sel. Areas Commun. Sebastian Ritz, Matthias Pankert, Vojin Zivojnovic, Heinrich Meyr
1993	J	`jnl`	Matched Filter Bound for Trellis-Coded Transmission over Frequency-Selective Fading Channels with Diversity. Eur. Trans. Telecommun. Stefan A. Fechtel, Heinrich Meyr
1993	—	`conf`	Optimum vectorization of scalable synchronous dataflow graphs. ASAP Sebastian Ritz, Matthias Pankert, V. Zivojinovic, Heinrich Meyr
1993	C	`conf`	Partitioning and Surmounting the Software-Hardware Abstraction Gap in an ASIC Design Project. ICCD Klaus ten Hagen, Heinrich Meyr
1992	B	`conf`	A new mobile digital radio transceiver concept using low-complexity combined equalization/trellis decoding and a near-optimal receiver sync strategy. PIMRC Stefan A. Fechtel, Heinrich Meyr
1992	—	`conf`	High level software synthesis for signal processing systems. ASAP Sebastian Ritz, Matthias Pankert, Heinrich Meyr
1992	—	`conf`	High speed bit-level pipelined architectures for redundant CORDIC implementation. ASAP Herbert Dawid, Heinrich Meyr
1992	—	`conf`	High-speed VLSI architectures for soft-output Viterbi decoding. ASAP Olaf J. Joeressen, Martin Vaupel, Heinrich Meyr
1991	J	`jnl`	A new method for phase synchronization and automatic gain control of linearly modulated signals on frequency-flat fading channels. IEEE Trans. Commun. Abbas Aghamohammadi, Heinrich Meyr, Gerd Ascheid
1991	J	`jnl`	Feedforward architectures for parallel Viterbi decoding. J. VLSI Signal Process. Gerhard P. Fettweis, Heinrich Meyr
1991	J	`jnl`	High-speed parallel Viterbi decoding: algorithm and VLSI-architecture. IEEE Commun. Mag. Gerhard P. Fettweis, Heinrich Meyr
1990	J	`jnl`	High-Rate Viterbi Processor: A Systolic Array Solution. IEEE J. Sel. Areas Commun. Gerhard P. Fettweis, Heinrich Meyr
1990	J	`jnl`	On the error probability of linearly modulated signals on Rayleigh frequency-flat fading channels. IEEE Trans. Commun. Abbas Aghamohammadi, Heinrich Meyr
1989	J	`jnl`	A systematic approach to carrier recovery and detection of digitally phase modulated signals of fading channels. IEEE Trans. Commun. Reinhold Haeb, Heinrich Meyr
1989	J	`jnl`	Adaptive synchronization and channel parameter estimation using an extended Kalman filter. IEEE Trans. Commun. Abbas Aghamohammadi, Heinrich Meyr, Gerd Ascheid
1989	J	`jnl`	An all digital receiver architecture for bandwidth efficient transmission at high data rates. IEEE Trans. Commun. Gerd Ascheid, Martin Oerder, Johannes Stahl, Heinrich Meyr
1989	J	`jnl`	Parallel Viterbi algorithm implementation: breaking the ACS-bottleneck. IEEE Trans. Commun. Gerhard P. Fettweis, Heinrich Meyr
1988	J	`jnl`	Cycle slips in synchronizers subject to smooth narrow-band loop noise. IEEE Trans. Commun. Marc Moeneclaey, Stanislaw Starzak, Heinrich Meyr
1988	J	`jnl`	Digital filter and square timing recovery. IEEE Trans. Commun. Martin Oerder, Heinrich Meyr
1988	B	`conf`	Error handling performance of a token ring LAN. LCN Jürgen Tusch, Heinrich Meyr, Erwin A. Zurfluh
1988	J	`jnl`	Transit-time estimation in turbulent flows. IEEE Trans. Acoust. Speech Signal Process. Rolf Peters, Frank Blischke, Heinrich Meyr
1987	J	`jnl`	A Simple Method for Evaluating the Probability Density Function of the Sample Number for the Optimum Sequential Detector. IEEE Trans. Commun. Heinrich Meyr, Gerhard Polzer
1986	J	`jnl`	An all-digital realization of a baseband DLL implemented as a dynamical state estimator. IEEE Trans. Acoust. Speech Signal Process. Jörg Bohmann, Heinrich Meyr
1986	J	`jnl`	Synchronization Failures in a Chain of PLL Synchronizers. IEEE Trans. Commun. Heinrich Meyr, Luitjens Popken, Hans R. Müller
1983	J	`jnl`	Performance Analysis for General PN-Spread-Spectrum Acquisition Techniques. IEEE Trans. Commun. Heinrich Meyr, Gerhard Polzer
1983	J	`jnl`	Transmission Design Criteria for a Synchronous Token Ring. IEEE J. Sel. Areas Commun. Heinz J. Keller, Heinrich Meyr, Hans R. Müller
1982	J	`jnl`	Cycle Slips in Phase-Locked Loops: A Tutorial Survey. IEEE Trans. Commun. Gerd Ascheid, Heinrich Meyr
1982	Misc	`conf`	Real-time estimation of moving time delay. ICASSP Heinrich Meyr, Gerhard Spies, Jörg Bohmann
1980	J	`jnl`	Phase Acquisition Statistics for Phase-Locked Loops. IEEE Trans. Commun. Heinrich Meyr, Luitjens Popken
1978	J	`jnl`	Theory of phase tracking systems of arbitrary order: Statistics of cycle slips and probability distribution of the state vector. IEEE Trans. Inf. Theory Dietrich Ryter, Heinrich Meyr
1977	J	`jnl`	Complete statistical description of the phase-error process generated by correlative tracking systems. IEEE Trans. Inf. Theory William C. Lindsey, Heinrich Meyr
1976	J	`jnl`	Delay-Lock Tracking of Stochastic Signals. IEEE Trans. Commun. Heinrich Meyr
1975	J	`jnl`	Nonlinear Analysis of Correlative Tracking Systems Using Renewal Process Theory. IEEE Trans. Commun. Heinrich Meyr