Heinrich Klar

23 papers A 1B 1C 4Misc 3Journal 10Unranked 4
YearRankTypeTitle / Venue / Authors
2016 C conf
Implementation and design investigation of 40 Gbps driver IC for silicon photonics ring-modulator in SiGe 130-nm.
ISCAS
Adel Fatemi, Heinrich Klar, Friedel Gerfers
2005 — conf
A cascade 3-1-1 multibit ΣΔ A/D modulator with reduced sensitivity to non-idealities.
ISCAS (4)
Yi Yin, Heinrich Klar, Peter Wennekers
2005 B conf
Emulation engine for spiking neurons and adaptive synaptic weights.
IJCNN
Heik Heinrich Hellmich, M. Geike, P. Griep, Phil Mahr, Marco Rafanelli, Heinrich Klar
2004 — conf
A novel broadband cascade sigma-delta analog-to-digital converter.
Circuits, Signals, and Systems
Yi Yin, Heinrich Klar, Peter Wennekers
2003 J jnl
Image preprocessing with dynamic synapses.
Neural Comput. Appl.
Nasser Mehrtash, Dietmar Jung, Heinrich Klar
2003 J jnl
Synaptic plasticity in spiking neural networks (SP
IEEE Trans. Neural Networks
Nasser Mehrtash, Dietmar Jung, Heik Heinrich Hellmich, Tim Schönauer, Vi Thanh Lu, Heinrich Klar
2002 J jnl
NeuroPipe-Chip: A digital neuro-processor for spiking neural networks.
IEEE Trans. Neural Networks
Tim Schönauer, Sahin Atasoy, Nasser Mehrtash, Heinrich Klar
2002 J jnl
Simulation of spiking neural networks -- architectures and implementations.
Neurocomputing
Martin Schäfer, Tim Schönauer, Carsten Wolff, Georg Hartmann, Heinrich Klar, Ulrich Rückert
2000 — conf
Simulation of a Digital Neuro-Chip for Spiking Neural Networks.
IJCNN (4)
Tim Schönauer, Sahin Atasoy, Nasser Mehrtash, Heinrich Klar
1998 J jnl
A 12-bit medium-time analog storage device in a CMOS standard process.
IEEE J. Solid State Circuits
Martin Ehlert, Heinrich Klar
1997 Misc conf
A New Bio-inspired Algorithm for Early Vision Edge Detection and Image Segmentation.
IWANN
Chang-Han Yi, Robert Schlabbach, Holger Kroth, Heinrich Klar
1997 C conf
An Improved Multiplexed Resistive Network for Analog Image Preprocessing.
ICANN
Chang-Han Yi, Robert Schlabbach, Holger Kroth, Heinrich Klar
1997 Misc conf
Dynamic Path Planning with Spiking Neural Networks.
IWANN
Ulrich Roth, Marc Walker, Arne Hilmann, Heinrich Klar
1997 C conf
On-Line Hebbian Learning for Spiking Neurons: Architecture of the Weight-Unit of NESPINN.
ICANN
Ulrich Roth, Axel Jahnke, Heinrich Klar
1997 C conf
Simulation of Spiking Neural Networks on Different Hardware Platforms.
ICANN
Axel Jahnke, Tim Schönauer, Ulrich Roth, K. Mohraz, Heinrich Klar
1996 J jnl
A CMOS gate array architecture for digital signal processing applications.
IEEE J. Solid State Circuits
Jorg-Michael Green, Heinrich Klar
1995 A conf
A new algorithm for the design of stable higher order single loop sigma delta analog-to-digital converters.
ICCAD
S. R. Kadivar, Doris Schmitt-Landsiedel, Heinrich Klar
1995 J jnl
Calculation of the soft error rate of submicron CMOS logic circuits.
IEEE J. Solid State Circuits
T. Juhnke, Heinrich Klar
1995 J jnl
General algorithms for a simplified addition of 2's complement numbers.
IEEE J. Solid State Circuits
O. Salomon, Jorg-Michael Green, Heinrich Klar
1995 Misc conf
Hardware Requirements for Spike-Processing Neural Networks.
IWANN
Ulrich Roth, Axel Jahnke, Heinrich Klar
1993 J jnl
Design of a general-purpose neural signal processor.
Neurocomputing
Jörg Beichter, Nico Brüls, Elisabeth Sicheneder, Ulrich Ramacher, Heinrich Klar
1993 — conf
Self-Timed Fully Pipelined Multipliers.
Asynchronous Design Methodologies
O. Salomon, Heinrich Klar
1992 J jnl
A configurable convolution chip with programmable coefficients.
IEEE J. Solid State Circuits
Dirk Reuver, Heinrich Klar