| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2025 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2024 | J | jnl |
CoRR
|
| 2024 | J | jnl |
CoRR
|
| 2023 | J | jnl |
CoRR
|
| 2023 | J | jnl |
EPJ Data Sci.
|
| 2021 | J | jnl |
CoRR
|
| 2021 | J | jnl |
CoRR
|
| 2019 | J | jnl |
CoRR
|
| 2018 | — | conf |
Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test.
ISOCC
|
| 2018 | — | conf |
ISOCC
|
| 2018 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2017 | J | jnl |
IEICE Electron. Express
|
| 2017 | — | conf |
ISOCC
|
| 2017 | J | jnl |
Program
|
| 2017 | J | jnl |
IEICE Electron. Express
|
| 2016 | — | conf |
ISOCC
|
| 2015 | J | jnl |
IEICE Electron. Express
|
| 2015 | J | jnl |
Behav. Inf. Technol.
|
| 2014 | J | jnl |
Inf. Technol. Dev.
|
| 2011 | J | jnl |
IEICE Trans. Electron.
|