Heein Yoon

19 papers Journal 11Unranked 8
YearRankTypeTitle / Venue / Authors
2026 J jnl
A -53.7-dB PSRR, Fast-Transient Output-Capacitor-Less Digital-Assisted Analog LDO Using Seamless Digital-to-Analog Transfer Technique.
IEEE J. Solid State Circuits
Changmin An, Hyogyoung An, Hyeonjun Nam, Heein Yoon
2026 J jnl
A Multibit ReRAM Computing-in-Memory Processor With Adaptive Decision Level Nonlinear ADC for Ultra-Low-Energy Keyword Spotting in Mobile Devices.
IEEE Trans. Circuits Syst. I Regul. Pap.
Dongwook Kim, Hoichang Jeong, Seungbin Kim, Heein Yoon, Kyuho Jason Lee
2026 J jnl
Guest Editorial Introduction to the Special Section on the 2025 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits
Hyo Gyuem Rhew, Heein Yoon, Chia-Hsiang Yang, Utsav Banerjee, Xueqing Li
2025 J jnl
A 6.2b-ENOB 2.5 GS/s Flash-and-VCO-Based Subranging ADC Using a Residue Shifting Technique.
IEEE Solid State Circuits Lett.
Sungjin Kim, Jeonghyun Lee, Yoonseo Cho, Jintae Kim, Jaehyouk Choi, Heein Yoon
2025 J jnl
A Low-Jitter and Wide-Frequency-Range D-Band Frequency Synthesizer With a Subsampling PLL and a Harmonic-Boosting Frequency Multiplier.
IEEE J. Solid State Circuits
Seohee Jung, Jaeho Kim, Jooeun Bang, Sarang Lee, Heein Yoon, Jaehyouk Choi
2025 J jnl
An Area-Efficient CMOS Cross-Coupled LC-VCO Using Nested Intertwined Tail Inductors.
IEEE Trans. Circuits Syst. II Express Briefs
Hyogyoung An, Hyeonjun Nam, Sungjin Kim, Younghyun Lim, Heein Yoon
2021 — conf
An 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier- Based Phase Detector in 65nm CMOS.
ISSCC
Seyeon Yoo, Suneui Park, Seojin Choi, Yoonseo Cho, Heein Yoon, Chanwoong Hwang, Jaehyouk Choi
2020 — conf
17.8 A 170MHz-Lock-In-Range and -253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator.
ISSCC
Younghyun Lim, Juyeop Kim, Yongwoo Jo, Jooeun Bang, Seyeon Yoo, Hangi Park, Heein Yoon, Jaehyouk Choi
2019 — conf
A 76fsrms Jitter and -40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization.
ISSCC
Juyeop Kim, Heein Yoon, Younghyun Lim, Yongsun Lee, Yoonseo Cho, Taeho Seong, Jaehyouk Choi
2019 J jnl
A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally Controlled Oscillators and Time-Interleaved Calibration.
IEEE J. Solid State Circuits
Heein Yoon, Suneui Park, Jaehyouk Choi
2019 J jnl
An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators.
IEEE J. Solid State Circuits
Juyeop Kim, Younghyun Lim, Heein Yoon, Yongsun Lee, Hangi Park, Yoonseo Cho, Taeho Seong, Jaehyouk Choi
2018 — conf
A -31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection-locked frequency multipliers.
ISSCC
Heein Yoon, Juyeop Kim, Suneui Park, Younghyun Lim, Yongsun Lee, Jooeun Bang, Kyoohyun Lim, Jaehyouk Choi
2018 J jnl
A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier With an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers.
IEEE J. Solid State Circuits
Seyeon Yoo, Seojin Choi, Juyeop Kim, Heein Yoon, Yongsun Lee, Jaehyouk Choi
2018 — conf
Injection-locked frequency multiplier with a continuous frequency-tracking loop for 5G transceivers.
ASP-DAC
Seyeon Yoo, Seojin Choi, Juyeop Kim, Heein Yoon, Yongsun Lee, Jaehyouk Choi
2017 — conf
19.2 A PVT-robust -39dBc 1kHz-to-100MHz integrated-phase-noise 29GHz injection-locked frequency multiplier with a 600µW frequency-tracking loop using the averages of phase deviations for mm-band 5G transceivers.
ISSCC
Seyeon Yoo, Seojin Choi, Juyeop Kim, Heein Yoon, Yongsun Lee, Jaehyouk Choi
2017 — conf
An ultra-low phase noise all-digital multi-frequency generator using injection-locked DCOs and time-interleaved calibration.
A-SSCC
Suneui Park, Heein Yoon, Jaehyouk Choi
2016 J jnl
A 0.56-2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2G-4G Multistandard Cellular Transceivers.
IEEE J. Solid State Circuits
Heein Yoon, Yongsun Lee, Younghyun Lim, Geum-Young Tak, Hong-Teuk Kim, Yo-Chuol Ho, Jaehyouk Choi
2016 — conf
A PVT-robust -59-dBc reference spur and 450-fsRMS jitter injection-locked clock multiplier using a voltage-domain period-calibrating loop.
VLSI Circuits
Yongsun Lee, Heein Yoon, Mina Kim, Jaehyouk Choi
2014 J jnl
A Wideband Dual-Mode LC-VCO With a Switchable Gate-Biased Active Core.
IEEE Trans. Circuits Syst. II Express Briefs
Heein Yoon, Yongsun Lee, Jae Joon Kim, Jaehyouk Choi